145 lines
4.3 KiB
YAML
145 lines
4.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,sc8180x-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. SC8180X TLMM block
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm SC8180X SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,sc8180x-tlmm
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reg:
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maxItems: 3
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reg-names:
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items:
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- const: west
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- const: east
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- const: south
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interrupts:
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells': true
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gpio-controller: true
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gpio-reserved-ranges: true
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'#gpio-cells': true
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gpio-ranges: true
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wakeup-parent: true
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required:
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- compatible
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- reg
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- reg-names
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additionalProperties: false
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-sc8180x-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-sc8180x-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-sc8180x-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$"
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- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
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minItems: 1
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maxItems: 16
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens,
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atest_tsens2, atest_usb0, atest_usb1, atest_usb2, atest_usb3,
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atest_usb4, audio_ref, btfm_slimbus, cam_mclk, cci_async,
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cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
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cci_timer4, cci_timer5, cci_timer6, cci_timer7, cci_timer8,
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cci_timer9, cri_trng, dbg_out, ddr_bist, ddr_pxi, debug_hot,
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dp_hot, edp_hot, edp_lcd, emac_phy, emac_pps, gcc_gp1, gcc_gp2,
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gcc_gp3, gcc_gp4, gcc_gp5, gpio, gps, grfc, hs1_mi2s, hs2_mi2s,
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hs3_mi2s, jitter_bist, lpass_slimbus, m_voc, mdp_vsync,
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mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4,
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mdp_vsync5, mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1,
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pci_e2, pci_e3, phase_flag, pll_bist, pll_bypassnl, pll_reset,
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pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss_gpio, qlink,
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qspi0, qspi0_clk, qspi0_cs, qspi1, qspi1_clk, qspi1_cs,
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qua_mi2s, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
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qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
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qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii, sd_write, sdc4,
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sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu,
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tsense_pwm1, tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt,
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usb0_phy, usb1_phy, usb2phy_ac, vfr_1, vsense_trigger,
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wlan1_adc, wlan2_adc, wmss_reset ]
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required:
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- pins
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pinctrl@3100000 {
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compatible = "qcom,sc8180x-tlmm";
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reg = <0x03100000 0x300000>,
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<0x03500000 0x700000>,
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<0x03d00000 0x300000>;
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reg-names = "west", "east", "south";
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&tlmm 0 0 190>;
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gpio-wo-subnode-state {
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pins = "gpio1";
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function = "gpio";
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};
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uart-w-subnodes-state {
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rx-pins {
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pins = "gpio4";
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function = "qup6";
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bias-pull-up;
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};
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tx-pins {
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pins = "gpio5";
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function = "qup6";
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bias-disable;
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};
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};
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};
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...
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