167 lines
4.9 KiB
YAML
167 lines
4.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,sm8150-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SM8150 TLMM pin controller
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm SM8150 SoC.
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properties:
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compatible:
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const: qcom,sm8150-pinctrl
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reg:
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maxItems: 4
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reg-names:
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items:
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- const: west
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- const: east
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- const: north
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- const: south
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells": true
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gpio-controller: true
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"#gpio-cells": true
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gpio-ranges: true
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wakeup-parent: true
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 88
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gpio-line-names:
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maxItems: 175
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-sm8150-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-sm8150-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-sm8150-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
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- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
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atest_char0, atest_char1, atest_char2, atest_char3, audio_ref,
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atest_usb1, atest_usb2, atest_usb10, atest_usb11, atest_usb12,
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atest_usb13, atest_usb20, atest_usb21, atest_usb22,
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atest_usb23, btfm_slimbus, cam_mclk, cci_async, cci_i2c,
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cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
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cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
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ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd, emac_phy, emac_pps,
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gcc_gp1, gcc_gp2, gcc_gp3, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s,
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jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
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mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator,
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pci_e0, phase_flag, pll_bypassnl, pll_bist, pci_e1, pll_reset,
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pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti,
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qlink_request, qlink_enable, qspi0, qspi1, qspi2, qspi3,
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qspi_clk, qspi_cs, qua_mi2s, qup0, qup1, qup2, qup3, qup4,
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qup5, qup6, qup7, qup8, qup9, qup10, qup11, qup12, qup13,
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qup14, qup15, qup16, qup17, qup18, qup19, qup_l4, qup_l5,
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qup_l6, rgmii, sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu,
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ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
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tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt, usb2phy_ac,
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usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
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wlan2_adc0, wlan2_adc1, wmss_reset ]
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required:
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- pins
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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required:
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- compatible
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- reg
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- reg-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@3100000 {
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compatible = "qcom,sm8150-pinctrl";
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reg = <0x03100000 0x300000>,
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<0x03500000 0x300000>,
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<0x03900000 0x300000>,
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<0x03d00000 0x300000>;
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reg-names = "west", "east", "north", "south";
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&tlmm 0 0 176>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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wakeup-parent = <&pdc>;
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qup-spi0-default-state {
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pins = "gpio0", "gpio1", "gpio2", "gpio3";
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function = "qup0";
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drive-strength = <6>;
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bias-disable;
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};
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pcie1-default-state {
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perst-pins {
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pins = "gpio102";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-down;
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};
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clkreq-pins {
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pins = "gpio103";
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function = "pci_e1";
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drive-strength = <2>;
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bias-pull-up;
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};
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wake-pins {
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pins = "gpio104";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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