53 lines
2.3 KiB
Plaintext
53 lines
2.3 KiB
Plaintext
* Mediatek Thermal
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This describes the device tree binding for the Mediatek thermal controller
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which measures the on-SoC temperatures. This device does not have its own ADC,
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instead it directly controls the AUXADC via AHB bus accesses. For this reason
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this device needs phandles to the AUXADC. Also it controls a mux in the
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apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS
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is also needed.
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Required properties:
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- compatible:
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- "mediatek,mt8173-thermal" : For MT8173 family of SoCs
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- "mediatek,mt2701-thermal" : For MT2701 family of SoCs
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- "mediatek,mt2712-thermal" : For MT2712 family of SoCs
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- "mediatek,mt7622-thermal" : For MT7622 SoC
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- "mediatek,mt7981-thermal", "mediatek,mt7986-thermal" : For MT7981 SoC
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- "mediatek,mt7986-thermal" : For MT7986 SoC
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- "mediatek,mt8183-thermal" : For MT8183 family of SoCs
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- "mediatek,mt8365-thermal" : For MT8365 family of SoCs
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- "mediatek,mt8516-thermal", "mediatek,mt2701-thermal : For MT8516 family of SoCs
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- reg: Address range of the thermal controller
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- interrupts: IRQ for the thermal controller
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- clocks, clock-names: Clocks needed for the thermal controller. required
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clocks are:
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"therm": Main clock needed for register access
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"auxadc": The AUXADC clock
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- mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses
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- mediatek,apmixedsys: A phandle to the APMIXEDSYS controller.
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- #thermal-sensor-cells : Should be 0. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description.
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Optional properties:
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- resets: Reference to the reset controller controlling the thermal controller.
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- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
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unspecified default values shall be used.
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- nvmem-cell-names: Should be "calibration-data"
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Example:
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thermal: thermal@1100b000 {
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#thermal-sensor-cells = <1>;
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compatible = "mediatek,mt8173-thermal";
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reg = <0 0x1100b000 0 0x1000>;
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interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
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clock-names = "therm", "auxadc";
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resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
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reset-names = "therm";
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mediatek,auxadc = <&auxadc>;
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mediatek,apmixedsys = <&apmixedsys>;
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nvmem-cells = <&thermal_calibration_data>;
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nvmem-cell-names = "calibration-data";
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};
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