129 lines
4.0 KiB
YAML
129 lines
4.0 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM architected timer
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maintainers:
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- Marc Zyngier <marc.zyngier@arm.com>
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- Mark Rutland <mark.rutland@arm.com>
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description: |+
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ARM cores may have a per-core architected timer, which provides per-cpu timers,
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or a memory mapped architected timer, which provides up to 8 frames with a
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physical and optional virtual timer per frame.
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The per-core architected timer is attached to a GIC to deliver its
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per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
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to deliver its interrupts via SPIs.
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properties:
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compatible:
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oneOf:
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- items:
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- const: arm,cortex-a15-timer
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- const: arm,armv7-timer
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- items:
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- enum:
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- arm,armv7-timer
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- arm,armv8-timer
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- items:
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- const: arm,armv8-timer
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- const: arm,armv7-timer
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interrupts:
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minItems: 1
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items:
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- description: secure timer irq
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- description: non-secure timer irq
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- description: virtual timer irq
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- description: hypervisor timer irq
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- description: hypervisor virtual timer irq
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interrupt-names:
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oneOf:
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- minItems: 2
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items:
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- const: phys
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- const: virt
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- const: hyp-phys
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- const: hyp-virt
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- minItems: 3
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items:
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- const: sec-phys
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- const: phys
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- const: virt
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- const: hyp-phys
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- const: hyp-virt
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clock-frequency:
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description: The frequency of the main counter, in Hz. Should be present
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only where necessary to work around broken firmware which does not configure
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CNTFRQ on all CPUs to a uniform correct value. Use of this property is
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strongly discouraged; fix your firmware unless absolutely impossible.
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always-on:
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type: boolean
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description: If present, the timer is powered through an always-on power
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domain, therefore it never loses context.
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allwinner,erratum-unknown1:
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type: boolean
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description: Indicates the presence of an erratum found in Allwinner SoCs,
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where reading certain values from the counter is unreliable. This also
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affects writes to the tval register, due to the implicit counter read.
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fsl,erratum-a008585:
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type: boolean
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description: Indicates the presence of QorIQ erratum A-008585, which says
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that reading the counter is unreliable unless the same value is returned
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by back-to-back reads. This also affects writes to the tval register, due
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to the implicit counter read.
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hisilicon,erratum-161010101:
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type: boolean
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description: Indicates the presence of Hisilicon erratum 161010101, which
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says that reading the counters is unreliable in some cases, and reads may
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return a value 32 beyond the correct value. This also affects writes to
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the tval registers, due to the implicit counter read.
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arm,cpu-registers-not-fw-configured:
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type: boolean
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description: Firmware does not initialize any of the generic timer CPU
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registers, which contain their architecturally-defined reset values. Only
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supported for 32-bit systems which follow the ARMv7 architected reset
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values.
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arm,no-tick-in-suspend:
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type: boolean
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description: The main counter does not tick when the system is in
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low-power system suspend on some SoCs. This behavior does not match the
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Architecture Reference Manual's specification that the system counter "must
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be implemented in an always-on power domain."
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required:
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- compatible
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additionalProperties: false
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oneOf:
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- required:
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- interrupts
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- required:
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- interrupts-extended
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examples:
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- |
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timer {
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compatible = "arm,cortex-a15-timer",
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"arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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clock-frequency = <100000000>;
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};
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...
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