93 lines
1.8 KiB
YAML
93 lines
1.8 KiB
YAML
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx LogiCORE IP AXI Timer
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maintainers:
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- Sean Anderson <sean.anderson@seco.com>
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properties:
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compatible:
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contains:
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const: xlnx,xps-timer-1.00.a
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clocks:
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maxItems: 1
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clock-names:
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const: s_axi_aclk
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interrupts:
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maxItems: 1
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reg:
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maxItems: 1
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'#pwm-cells': true
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xlnx,count-width:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [8, 16, 32]
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default: 32
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description:
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The width of the counter(s), in bits.
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xlnx,one-timer-only:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 1 ]
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description:
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Whether only one timer is present in this block.
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required:
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- compatible
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- reg
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- xlnx,one-timer-only
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allOf:
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- if:
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required:
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- '#pwm-cells'
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then:
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allOf:
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- required:
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- clocks
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- properties:
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xlnx,one-timer-only:
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const: 0
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else:
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required:
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- interrupts
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- if:
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required:
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- clocks
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then:
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required:
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- clock-names
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additionalProperties: false
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examples:
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- |
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timer@800e0000 {
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clock-names = "s_axi_aclk";
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clocks = <&zynqmp_clk 71>;
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compatible = "xlnx,xps-timer-1.00.a";
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reg = <0x800e0000 0x10000>;
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interrupts = <0 39 2>;
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xlnx,count-width = <16>;
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xlnx,one-timer-only = <0x0>;
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};
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timer@800f0000 {
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#pwm-cells = <0>;
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clock-names = "s_axi_aclk";
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clocks = <&zynqmp_clk 71>;
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compatible = "xlnx,xps-timer-1.00.a";
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reg = <0x800e0000 0x10000>;
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xlnx,count-width = <32>;
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xlnx,one-timer-only = <0x0>;
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};
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