109 lines
2.2 KiB
YAML
109 lines
2.2 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip SuperSpeed DWC3 USB SoC controller
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maintainers:
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- Heiko Stuebner <heiko@sntech.de>
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description:
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The common content of the node is defined in snps,dwc3.yaml.
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Phy documentation is provided in the following places.
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USB2.0 PHY
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Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
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Type-C PHY
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Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
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allOf:
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- $ref: snps,dwc3.yaml#
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select:
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properties:
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compatible:
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contains:
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enum:
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- rockchip,rk3328-dwc3
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- rockchip,rk3568-dwc3
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required:
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- compatible
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properties:
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compatible:
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items:
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- enum:
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- rockchip,rk3328-dwc3
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- rockchip,rk3568-dwc3
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- const: snps,dwc3
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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minItems: 3
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items:
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- description:
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Controller reference clock, must to be 24 MHz
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- description:
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Controller suspend clock, must to be 24 MHz or 32 KHz
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- description:
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Master/Core clock, must to be >= 62.5 MHz for SS
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operation and >= 30MHz for HS operation
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- description:
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Controller grf clock
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clock-names:
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minItems: 3
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items:
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- const: ref_clk
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- const: suspend_clk
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- const: bus_clk
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- const: grf_clk
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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reset-names:
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const: usb3-otg
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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examples:
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- |
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#include <dt-bindings/clock/rk3328-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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usbdrd3_0: usb@fe800000 {
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compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
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reg = <0x0 0xfe800000 0x0 0x100000>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
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<&cru ACLK_USB3OTG>;
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clock-names = "ref_clk", "suspend_clk",
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"bus_clk", "grf_clk";
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dr_mode = "otg";
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};
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};
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