421 lines
10 KiB
C
421 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* linux/arch/alpha/kernel/core_apecs.c
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*
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* Rewritten for Apecs from the lca.c from:
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*
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* Written by David Mosberger (davidm@cs.arizona.edu) with some code
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* taken from Dave Rusling's (david.rusling@reo.mts.dec.com) 32-bit
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* bios code.
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*
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* Code common to all APECS core logic chips.
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*/
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#define __EXTERN_INLINE inline
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#include <asm/io.h>
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#include <asm/core_apecs.h>
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#undef __EXTERN_INLINE
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <asm/ptrace.h>
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#include <asm/smp.h>
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#include <asm/mce.h>
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#include "proto.h"
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#include "pci_impl.h"
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/*
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* NOTE: Herein lie back-to-back mb instructions. They are magic.
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* One plausible explanation is that the i/o controller does not properly
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* handle the system transaction. Another involves timing. Ho hum.
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*/
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/*
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* BIOS32-style PCI interface:
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*/
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#define DEBUG_CONFIG 0
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#if DEBUG_CONFIG
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# define DBGC(args) printk args
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#else
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# define DBGC(args)
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#endif
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#define vuip volatile unsigned int *
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/*
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* Given a bus, device, and function number, compute resulting
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* configuration space address and setup the APECS_HAXR2 register
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* accordingly. It is therefore not safe to have concurrent
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* invocations to configuration space access routines, but there
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* really shouldn't be any need for this.
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*
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* Type 0:
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*
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* 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
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* 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | | | | | | | | | | | | | | | | | | | | | | | |F|F|F|R|R|R|R|R|R|0|0|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* 31:11 Device select bit.
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* 10:8 Function number
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* 7:2 Register number
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*
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* Type 1:
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*
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* 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
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* 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* 31:24 reserved
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* 23:16 bus number (8 bits = 128 possible buses)
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* 15:11 Device number (5 bits)
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* 10:8 function number
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* 7:2 register number
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*
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* Notes:
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* The function number selects which function of a multi-function device
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* (e.g., SCSI and Ethernet).
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*
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* The register selects a DWORD (32 bit) register offset. Hence it
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* doesn't get shifted by 2 bits as we want to "drop" the bottom two
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* bits.
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*/
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static int
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mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where,
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unsigned long *pci_addr, unsigned char *type1)
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{
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unsigned long addr;
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u8 bus = pbus->number;
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DBGC(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x,"
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" pci_addr=0x%p, type1=0x%p)\n",
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bus, device_fn, where, pci_addr, type1));
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if (bus == 0) {
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int device = device_fn >> 3;
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/* type 0 configuration cycle: */
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if (device > 20) {
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DBGC(("mk_conf_addr: device (%d) > 20, returning -1\n",
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device));
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return -1;
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}
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*type1 = 0;
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addr = (device_fn << 8) | (where);
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} else {
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/* type 1 configuration cycle: */
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*type1 = 1;
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addr = (bus << 16) | (device_fn << 8) | (where);
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}
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*pci_addr = addr;
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DBGC(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
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return 0;
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}
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static unsigned int
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conf_read(unsigned long addr, unsigned char type1)
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{
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unsigned long flags;
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unsigned int stat0, value;
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unsigned int haxr2 = 0;
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local_irq_save(flags); /* avoid getting hit by machine check */
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DBGC(("conf_read(addr=0x%lx, type1=%d)\n", addr, type1));
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/* Reset status register to avoid losing errors. */
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stat0 = *(vuip)APECS_IOC_DCSR;
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*(vuip)APECS_IOC_DCSR = stat0;
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mb();
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DBGC(("conf_read: APECS DCSR was 0x%x\n", stat0));
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/* If Type1 access, must set HAE #2. */
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if (type1) {
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haxr2 = *(vuip)APECS_IOC_HAXR2;
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mb();
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*(vuip)APECS_IOC_HAXR2 = haxr2 | 1;
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DBGC(("conf_read: TYPE1 access\n"));
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}
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draina();
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mcheck_expected(0) = 1;
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mcheck_taken(0) = 0;
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mb();
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/* Access configuration space. */
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/* Some SRMs step on these registers during a machine check. */
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asm volatile("ldl %0,%1; mb; mb" : "=r"(value) : "m"(*(vuip)addr)
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: "$9", "$10", "$11", "$12", "$13", "$14", "memory");
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if (mcheck_taken(0)) {
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mcheck_taken(0) = 0;
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value = 0xffffffffU;
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mb();
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}
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mcheck_expected(0) = 0;
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mb();
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#if 1
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/*
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* david.rusling@reo.mts.dec.com. This code is needed for the
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* EB64+ as it does not generate a machine check (why I don't
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* know). When we build kernels for one particular platform
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* then we can make this conditional on the type.
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*/
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draina();
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/* Now look for any errors. */
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stat0 = *(vuip)APECS_IOC_DCSR;
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DBGC(("conf_read: APECS DCSR after read 0x%x\n", stat0));
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/* Is any error bit set? */
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if (stat0 & 0xffe0U) {
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/* If not NDEV, print status. */
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if (!(stat0 & 0x0800)) {
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printk("apecs.c:conf_read: got stat0=%x\n", stat0);
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}
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/* Reset error status. */
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*(vuip)APECS_IOC_DCSR = stat0;
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mb();
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wrmces(0x7); /* reset machine check */
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value = 0xffffffff;
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}
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#endif
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/* If Type1 access, must reset HAE #2 so normal IO space ops work. */
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if (type1) {
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*(vuip)APECS_IOC_HAXR2 = haxr2 & ~1;
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mb();
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}
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local_irq_restore(flags);
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return value;
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}
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static void
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conf_write(unsigned long addr, unsigned int value, unsigned char type1)
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{
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unsigned long flags;
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unsigned int stat0;
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unsigned int haxr2 = 0;
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local_irq_save(flags); /* avoid getting hit by machine check */
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/* Reset status register to avoid losing errors. */
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stat0 = *(vuip)APECS_IOC_DCSR;
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*(vuip)APECS_IOC_DCSR = stat0;
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mb();
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/* If Type1 access, must set HAE #2. */
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if (type1) {
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haxr2 = *(vuip)APECS_IOC_HAXR2;
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mb();
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*(vuip)APECS_IOC_HAXR2 = haxr2 | 1;
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}
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draina();
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mcheck_expected(0) = 1;
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mb();
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/* Access configuration space. */
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*(vuip)addr = value;
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mb();
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mb(); /* magic */
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mcheck_expected(0) = 0;
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mb();
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#if 1
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/*
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* david.rusling@reo.mts.dec.com. This code is needed for the
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* EB64+ as it does not generate a machine check (why I don't
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* know). When we build kernels for one particular platform
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* then we can make this conditional on the type.
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*/
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draina();
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/* Now look for any errors. */
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stat0 = *(vuip)APECS_IOC_DCSR;
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/* Is any error bit set? */
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if (stat0 & 0xffe0U) {
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/* If not NDEV, print status. */
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if (!(stat0 & 0x0800)) {
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printk("apecs.c:conf_write: got stat0=%x\n", stat0);
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}
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/* Reset error status. */
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*(vuip)APECS_IOC_DCSR = stat0;
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mb();
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wrmces(0x7); /* reset machine check */
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}
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#endif
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/* If Type1 access, must reset HAE #2 so normal IO space ops work. */
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if (type1) {
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*(vuip)APECS_IOC_HAXR2 = haxr2 & ~1;
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mb();
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}
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local_irq_restore(flags);
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}
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static int
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apecs_read_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *value)
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{
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unsigned long addr, pci_addr;
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unsigned char type1;
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long mask;
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int shift;
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if (mk_conf_addr(bus, devfn, where, &pci_addr, &type1))
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return PCIBIOS_DEVICE_NOT_FOUND;
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mask = (size - 1) * 8;
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shift = (where & 3) * 8;
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addr = (pci_addr << 5) + mask + APECS_CONF;
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*value = conf_read(addr, type1) >> (shift);
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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apecs_write_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 value)
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{
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unsigned long addr, pci_addr;
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unsigned char type1;
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long mask;
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if (mk_conf_addr(bus, devfn, where, &pci_addr, &type1))
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return PCIBIOS_DEVICE_NOT_FOUND;
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mask = (size - 1) * 8;
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addr = (pci_addr << 5) + mask + APECS_CONF;
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conf_write(addr, value << ((where & 3) * 8), type1);
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops apecs_pci_ops =
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{
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.read = apecs_read_config,
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.write = apecs_write_config,
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};
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void
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apecs_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
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{
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wmb();
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*(vip)APECS_IOC_TBIA = 0;
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mb();
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}
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void __init
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apecs_init_arch(void)
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{
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struct pci_controller *hose;
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/*
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* Create our single hose.
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*/
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pci_isa_hose = hose = alloc_pci_controller();
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hose->io_space = &ioport_resource;
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hose->mem_space = &iomem_resource;
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hose->index = 0;
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hose->sparse_mem_base = APECS_SPARSE_MEM - IDENT_ADDR;
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hose->dense_mem_base = APECS_DENSE_MEM - IDENT_ADDR;
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hose->sparse_io_base = APECS_IO - IDENT_ADDR;
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hose->dense_io_base = 0;
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/*
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* Set up the PCI to main memory translation windows.
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*
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* Window 1 is direct access 1GB at 1GB
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* Window 2 is scatter-gather 8MB at 8MB (for isa)
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*/
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hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000,
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SMP_CACHE_BYTES);
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hose->sg_pci = NULL;
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__direct_map_base = 0x40000000;
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__direct_map_size = 0x40000000;
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*(vuip)APECS_IOC_PB1R = __direct_map_base | 0x00080000;
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*(vuip)APECS_IOC_PM1R = (__direct_map_size - 1) & 0xfff00000U;
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*(vuip)APECS_IOC_TB1R = 0;
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*(vuip)APECS_IOC_PB2R = hose->sg_isa->dma_base | 0x000c0000;
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*(vuip)APECS_IOC_PM2R = (hose->sg_isa->size - 1) & 0xfff00000;
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*(vuip)APECS_IOC_TB2R = virt_to_phys(hose->sg_isa->ptes) >> 1;
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apecs_pci_tbi(hose, 0, -1);
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/*
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* Finally, clear the HAXR2 register, which gets used
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* for PCI Config Space accesses. That is the way
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* we want to use it, and we do not want to depend on
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* what ARC or SRM might have left behind...
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*/
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*(vuip)APECS_IOC_HAXR2 = 0;
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mb();
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}
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void
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apecs_pci_clr_err(void)
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{
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unsigned int jd;
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jd = *(vuip)APECS_IOC_DCSR;
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if (jd & 0xffe0L) {
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*(vuip)APECS_IOC_SEAR;
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*(vuip)APECS_IOC_DCSR = jd | 0xffe1L;
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mb();
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*(vuip)APECS_IOC_DCSR;
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}
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*(vuip)APECS_IOC_TBIA = (unsigned int)APECS_IOC_TBIA;
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mb();
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*(vuip)APECS_IOC_TBIA;
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}
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void
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apecs_machine_check(unsigned long vector, unsigned long la_ptr)
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{
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struct el_common *mchk_header;
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struct el_apecs_procdata *mchk_procdata;
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struct el_apecs_sysdata_mcheck *mchk_sysdata;
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mchk_header = (struct el_common *)la_ptr;
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mchk_procdata = (struct el_apecs_procdata *)
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(la_ptr + mchk_header->proc_offset
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- sizeof(mchk_procdata->paltemp));
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mchk_sysdata = (struct el_apecs_sysdata_mcheck *)
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(la_ptr + mchk_header->sys_offset);
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/* Clear the error before any reporting. */
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mb();
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mb(); /* magic */
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draina();
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apecs_pci_clr_err();
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wrmces(0x7); /* reset machine check pending flag */
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mb();
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process_mcheck_info(vector, la_ptr, "APECS",
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(mcheck_expected(0)
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&& (mchk_sysdata->epic_dcsr & 0x0c00UL)));
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}
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