636 lines
16 KiB
C
636 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* OMAP WakeupGen Source file
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*
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* OMAP WakeupGen is the interrupt controller extension used along
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* with ARM GIC to wake the CPU out from low power states on
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* external interrupts. It is responsible for generating wakeup
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* event from the incoming interrupts and enable bits. It is
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* implemented in MPU always ON power domain. During normal operation,
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* WakeupGen delivers external interrupts directly to the GIC.
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/cpu.h>
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#include <linux/notifier.h>
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#include <linux/cpu_pm.h>
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#include "omap-wakeupgen.h"
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#include "omap-secure.h"
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#include "soc.h"
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#include "omap4-sar-layout.h"
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#include "common.h"
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#include "pm.h"
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#define AM43XX_NR_REG_BANKS 7
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#define AM43XX_IRQS 224
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#define MAX_NR_REG_BANKS AM43XX_NR_REG_BANKS
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#define MAX_IRQS AM43XX_IRQS
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#define DEFAULT_NR_REG_BANKS 5
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#define DEFAULT_IRQS 160
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#define WKG_MASK_ALL 0x00000000
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#define WKG_UNMASK_ALL 0xffffffff
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#define CPU_ENA_OFFSET 0x400
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#define CPU0_ID 0x0
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#define CPU1_ID 0x1
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#define OMAP4_NR_BANKS 4
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#define OMAP4_NR_IRQS 128
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#define SYS_NIRQ1_EXT_SYS_IRQ_1 7
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#define SYS_NIRQ2_EXT_SYS_IRQ_2 119
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static void __iomem *wakeupgen_base;
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static void __iomem *sar_base;
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static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
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static unsigned int irq_target_cpu[MAX_IRQS];
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static unsigned int irq_banks = DEFAULT_NR_REG_BANKS;
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static unsigned int max_irqs = DEFAULT_IRQS;
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static unsigned int omap_secure_apis;
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#ifdef CONFIG_CPU_PM
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static unsigned int wakeupgen_context[MAX_NR_REG_BANKS];
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#endif
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struct omap_wakeupgen_ops {
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void (*save_context)(void);
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void (*restore_context)(void);
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};
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static struct omap_wakeupgen_ops *wakeupgen_ops;
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/*
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* Static helper functions.
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*/
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static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
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{
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return readl_relaxed(wakeupgen_base + OMAP_WKG_ENB_A_0 +
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(cpu * CPU_ENA_OFFSET) + (idx * 4));
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}
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static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
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{
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writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
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(cpu * CPU_ENA_OFFSET) + (idx * 4));
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}
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static inline void sar_writel(u32 val, u32 offset, u8 idx)
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{
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writel_relaxed(val, sar_base + offset + (idx * 4));
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}
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static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
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{
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/*
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* Each WakeupGen register controls 32 interrupt.
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* i.e. 1 bit per SPI IRQ
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*/
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*reg_index = irq >> 5;
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*bit_posn = irq %= 32;
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return 0;
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}
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static void _wakeupgen_clear(unsigned int irq, unsigned int cpu)
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{
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u32 val, bit_number;
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u8 i;
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if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
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return;
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val = wakeupgen_readl(i, cpu);
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val &= ~BIT(bit_number);
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wakeupgen_writel(val, i, cpu);
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}
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static void _wakeupgen_set(unsigned int irq, unsigned int cpu)
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{
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u32 val, bit_number;
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u8 i;
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if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
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return;
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val = wakeupgen_readl(i, cpu);
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val |= BIT(bit_number);
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wakeupgen_writel(val, i, cpu);
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}
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/*
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* Architecture specific Mask extension
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*/
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static void wakeupgen_mask(struct irq_data *d)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&wakeupgen_lock, flags);
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_wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]);
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raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
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irq_chip_mask_parent(d);
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}
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/*
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* Architecture specific Unmask extension
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*/
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static void wakeupgen_unmask(struct irq_data *d)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&wakeupgen_lock, flags);
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_wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]);
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raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
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irq_chip_unmask_parent(d);
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}
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/*
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* The sys_nirq pins bypass peripheral modules and are wired directly
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* to MPUSS wakeupgen. They get automatically inverted for GIC.
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*/
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static int wakeupgen_irq_set_type(struct irq_data *d, unsigned int type)
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{
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bool inverted = false;
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switch (type) {
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case IRQ_TYPE_LEVEL_LOW:
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type &= ~IRQ_TYPE_LEVEL_MASK;
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type |= IRQ_TYPE_LEVEL_HIGH;
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inverted = true;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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type &= ~IRQ_TYPE_EDGE_BOTH;
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type |= IRQ_TYPE_EDGE_RISING;
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inverted = true;
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break;
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default:
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break;
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}
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if (inverted && d->hwirq != SYS_NIRQ1_EXT_SYS_IRQ_1 &&
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d->hwirq != SYS_NIRQ2_EXT_SYS_IRQ_2)
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pr_warn("wakeupgen: irq%li polarity inverted in dts\n",
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d->hwirq);
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return irq_chip_set_type_parent(d, type);
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
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static void _wakeupgen_save_masks(unsigned int cpu)
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{
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u8 i;
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for (i = 0; i < irq_banks; i++)
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per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
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}
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static void _wakeupgen_restore_masks(unsigned int cpu)
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{
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u8 i;
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for (i = 0; i < irq_banks; i++)
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wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
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}
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static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
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{
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u8 i;
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for (i = 0; i < irq_banks; i++)
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wakeupgen_writel(reg, i, cpu);
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}
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/*
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* Mask or unmask all interrupts on given CPU.
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* 0 = Mask all interrupts on the 'cpu'
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* 1 = Unmask all interrupts on the 'cpu'
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* Ensure that the initial mask is maintained. This is faster than
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* iterating through GIC registers to arrive at the correct masks.
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*/
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static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&wakeupgen_lock, flags);
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if (set) {
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_wakeupgen_save_masks(cpu);
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_wakeupgen_set_all(cpu, WKG_MASK_ALL);
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} else {
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_wakeupgen_set_all(cpu, WKG_UNMASK_ALL);
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_wakeupgen_restore_masks(cpu);
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}
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raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
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}
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#endif
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#ifdef CONFIG_CPU_PM
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static inline void omap4_irq_save_context(void)
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{
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u32 i, val;
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if (omap_rev() == OMAP4430_REV_ES1_0)
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return;
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for (i = 0; i < irq_banks; i++) {
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/* Save the CPUx interrupt mask for IRQ 0 to 127 */
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val = wakeupgen_readl(i, 0);
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sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
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val = wakeupgen_readl(i, 1);
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sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);
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/*
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* Disable the secure interrupts for CPUx. The restore
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* code blindly restores secure and non-secure interrupt
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* masks from SAR RAM. Secure interrupts are not suppose
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* to be enabled from HLOS. So overwrite the SAR location
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* so that the secure interrupt remains disabled.
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*/
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sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
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sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
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}
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/* Save AuxBoot* registers */
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val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
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writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET);
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val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
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writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET);
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/* Save SyncReq generation logic */
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val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
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writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
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val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
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writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET);
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/* Set the Backup Bit Mask status */
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val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET);
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val |= SAR_BACKUP_STATUS_WAKEUPGEN;
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writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
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}
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static inline void omap5_irq_save_context(void)
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{
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u32 i, val;
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for (i = 0; i < irq_banks; i++) {
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/* Save the CPUx interrupt mask for IRQ 0 to 159 */
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val = wakeupgen_readl(i, 0);
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sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
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val = wakeupgen_readl(i, 1);
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sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
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sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
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sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
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}
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/* Save AuxBoot* registers */
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val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
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writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
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val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
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writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
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/* Set the Backup Bit Mask status */
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val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
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val |= SAR_BACKUP_STATUS_WAKEUPGEN;
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writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
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}
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static inline void am43xx_irq_save_context(void)
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{
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u32 i;
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for (i = 0; i < irq_banks; i++) {
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wakeupgen_context[i] = wakeupgen_readl(i, 0);
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wakeupgen_writel(0, i, CPU0_ID);
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}
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}
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/*
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* Save WakeupGen interrupt context in SAR BANK3. Restore is done by
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* ROM code. WakeupGen IP is integrated along with GIC to manage the
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* interrupt wakeups from CPU low power states. It manages
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* masking/unmasking of Shared peripheral interrupts(SPI). So the
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* interrupt enable/disable control should be in sync and consistent
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* at WakeupGen and GIC so that interrupts are not lost.
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*/
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static void irq_save_context(void)
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{
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/* DRA7 has no SAR to save */
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if (soc_is_dra7xx())
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return;
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if (wakeupgen_ops && wakeupgen_ops->save_context)
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wakeupgen_ops->save_context();
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}
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/*
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* Clear WakeupGen SAR backup status.
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*/
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static void irq_sar_clear(void)
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{
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u32 val;
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u32 offset = SAR_BACKUP_STATUS_OFFSET;
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/* DRA7 has no SAR to save */
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if (soc_is_dra7xx())
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return;
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if (soc_is_omap54xx())
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offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
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val = readl_relaxed(sar_base + offset);
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val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
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writel_relaxed(val, sar_base + offset);
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}
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static void am43xx_irq_restore_context(void)
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{
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u32 i;
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for (i = 0; i < irq_banks; i++)
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wakeupgen_writel(wakeupgen_context[i], i, CPU0_ID);
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}
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static void irq_restore_context(void)
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{
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if (wakeupgen_ops && wakeupgen_ops->restore_context)
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wakeupgen_ops->restore_context();
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}
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/*
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* Save GIC and Wakeupgen interrupt context using secure API
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* for HS/EMU devices.
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*/
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static void irq_save_secure_context(void)
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{
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u32 ret;
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ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX,
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FLAG_START_CRITICAL,
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0, 0, 0, 0, 0);
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if (ret != API_HAL_RET_VALUE_OK)
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pr_err("GIC and Wakeupgen context save failed\n");
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}
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/* Define ops for context save and restore for each SoC */
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static struct omap_wakeupgen_ops omap4_wakeupgen_ops = {
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.save_context = omap4_irq_save_context,
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.restore_context = irq_sar_clear,
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};
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static struct omap_wakeupgen_ops omap5_wakeupgen_ops = {
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.save_context = omap5_irq_save_context,
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.restore_context = irq_sar_clear,
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};
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static struct omap_wakeupgen_ops am43xx_wakeupgen_ops = {
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.save_context = am43xx_irq_save_context,
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.restore_context = am43xx_irq_restore_context,
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};
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#else
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static struct omap_wakeupgen_ops omap4_wakeupgen_ops = {};
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static struct omap_wakeupgen_ops omap5_wakeupgen_ops = {};
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static struct omap_wakeupgen_ops am43xx_wakeupgen_ops = {};
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#endif
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#ifdef CONFIG_HOTPLUG_CPU
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static int omap_wakeupgen_cpu_online(unsigned int cpu)
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{
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wakeupgen_irqmask_all(cpu, 0);
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return 0;
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}
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static int omap_wakeupgen_cpu_dead(unsigned int cpu)
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{
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wakeupgen_irqmask_all(cpu, 1);
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return 0;
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}
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static void __init irq_hotplug_init(void)
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{
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cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "arm/omap-wake:online",
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omap_wakeupgen_cpu_online, NULL);
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cpuhp_setup_state_nocalls(CPUHP_ARM_OMAP_WAKE_DEAD,
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"arm/omap-wake:dead", NULL,
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omap_wakeupgen_cpu_dead);
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}
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#else
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static void __init irq_hotplug_init(void)
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{}
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#endif
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#ifdef CONFIG_CPU_PM
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static int irq_notifier(struct notifier_block *self, unsigned long cmd, void *v)
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{
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switch (cmd) {
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case CPU_CLUSTER_PM_ENTER:
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if (omap_type() == OMAP2_DEVICE_TYPE_GP || soc_is_am43xx())
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irq_save_context();
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else
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irq_save_secure_context();
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break;
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case CPU_CLUSTER_PM_EXIT:
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if (omap_type() == OMAP2_DEVICE_TYPE_GP || soc_is_am43xx())
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irq_restore_context();
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block irq_notifier_block = {
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.notifier_call = irq_notifier,
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};
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static void __init irq_pm_init(void)
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{
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/* FIXME: Remove this when MPU OSWR support is added */
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if (!IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
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cpu_pm_register_notifier(&irq_notifier_block);
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}
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#else
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static void __init irq_pm_init(void)
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{}
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#endif
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void __iomem *omap_get_wakeupgen_base(void)
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{
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return wakeupgen_base;
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}
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int omap_secure_apis_support(void)
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{
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return omap_secure_apis;
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}
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static struct irq_chip wakeupgen_chip = {
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.name = "WUGEN",
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.irq_eoi = irq_chip_eoi_parent,
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.irq_mask = wakeupgen_mask,
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.irq_unmask = wakeupgen_unmask,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_type = wakeupgen_irq_set_type,
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.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
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#ifdef CONFIG_SMP
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.irq_set_affinity = irq_chip_set_affinity_parent,
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#endif
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};
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static int wakeupgen_domain_translate(struct irq_domain *d,
|
|
struct irq_fwspec *fwspec,
|
|
unsigned long *hwirq,
|
|
unsigned int *type)
|
|
{
|
|
if (is_of_node(fwspec->fwnode)) {
|
|
if (fwspec->param_count != 3)
|
|
return -EINVAL;
|
|
|
|
/* No PPI should point to this domain */
|
|
if (fwspec->param[0] != 0)
|
|
return -EINVAL;
|
|
|
|
*hwirq = fwspec->param[1];
|
|
*type = fwspec->param[2];
|
|
return 0;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int wakeupgen_domain_alloc(struct irq_domain *domain,
|
|
unsigned int virq,
|
|
unsigned int nr_irqs, void *data)
|
|
{
|
|
struct irq_fwspec *fwspec = data;
|
|
struct irq_fwspec parent_fwspec;
|
|
irq_hw_number_t hwirq;
|
|
int i;
|
|
|
|
if (fwspec->param_count != 3)
|
|
return -EINVAL; /* Not GIC compliant */
|
|
if (fwspec->param[0] != 0)
|
|
return -EINVAL; /* No PPI should point to this domain */
|
|
|
|
hwirq = fwspec->param[1];
|
|
if (hwirq >= MAX_IRQS)
|
|
return -EINVAL; /* Can't deal with this */
|
|
|
|
for (i = 0; i < nr_irqs; i++)
|
|
irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
|
|
&wakeupgen_chip, NULL);
|
|
|
|
parent_fwspec = *fwspec;
|
|
parent_fwspec.fwnode = domain->parent->fwnode;
|
|
return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
|
|
&parent_fwspec);
|
|
}
|
|
|
|
static const struct irq_domain_ops wakeupgen_domain_ops = {
|
|
.translate = wakeupgen_domain_translate,
|
|
.alloc = wakeupgen_domain_alloc,
|
|
.free = irq_domain_free_irqs_common,
|
|
};
|
|
|
|
/*
|
|
* Initialise the wakeupgen module.
|
|
*/
|
|
static int __init wakeupgen_init(struct device_node *node,
|
|
struct device_node *parent)
|
|
{
|
|
struct irq_domain *parent_domain, *domain;
|
|
int i;
|
|
unsigned int boot_cpu = smp_processor_id();
|
|
u32 val;
|
|
|
|
if (!parent) {
|
|
pr_err("%pOF: no parent, giving up\n", node);
|
|
return -ENODEV;
|
|
}
|
|
|
|
parent_domain = irq_find_host(parent);
|
|
if (!parent_domain) {
|
|
pr_err("%pOF: unable to obtain parent domain\n", node);
|
|
return -ENXIO;
|
|
}
|
|
/* Not supported on OMAP4 ES1.0 silicon */
|
|
if (omap_rev() == OMAP4430_REV_ES1_0) {
|
|
WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
|
|
return -EPERM;
|
|
}
|
|
|
|
/* Static mapping, never released */
|
|
wakeupgen_base = of_iomap(node, 0);
|
|
if (WARN_ON(!wakeupgen_base))
|
|
return -ENOMEM;
|
|
|
|
if (cpu_is_omap44xx()) {
|
|
irq_banks = OMAP4_NR_BANKS;
|
|
max_irqs = OMAP4_NR_IRQS;
|
|
omap_secure_apis = 1;
|
|
wakeupgen_ops = &omap4_wakeupgen_ops;
|
|
} else if (soc_is_omap54xx()) {
|
|
wakeupgen_ops = &omap5_wakeupgen_ops;
|
|
} else if (soc_is_am43xx()) {
|
|
irq_banks = AM43XX_NR_REG_BANKS;
|
|
max_irqs = AM43XX_IRQS;
|
|
wakeupgen_ops = &am43xx_wakeupgen_ops;
|
|
}
|
|
|
|
domain = irq_domain_add_hierarchy(parent_domain, 0, max_irqs,
|
|
node, &wakeupgen_domain_ops,
|
|
NULL);
|
|
if (!domain) {
|
|
iounmap(wakeupgen_base);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* Clear all IRQ bitmasks at wakeupGen level */
|
|
for (i = 0; i < irq_banks; i++) {
|
|
wakeupgen_writel(0, i, CPU0_ID);
|
|
if (!soc_is_am43xx())
|
|
wakeupgen_writel(0, i, CPU1_ID);
|
|
}
|
|
|
|
/*
|
|
* FIXME: Add support to set_smp_affinity() once the core
|
|
* GIC code has necessary hooks in place.
|
|
*/
|
|
|
|
/* Associate all the IRQs to boot CPU like GIC init does. */
|
|
for (i = 0; i < max_irqs; i++)
|
|
irq_target_cpu[i] = boot_cpu;
|
|
|
|
/*
|
|
* Enables OMAP5 ES2 PM Mode using ES2_PM_MODE in AMBA_IF_MODE
|
|
* 0x0: ES1 behavior, CPU cores would enter and exit OFF mode together.
|
|
* 0x1: ES2 behavior, CPU cores are allowed to enter/exit OFF mode
|
|
* independently.
|
|
* This needs to be set one time thanks to always ON domain.
|
|
*
|
|
* We do not support ES1 behavior anymore. OMAP5 is assumed to be
|
|
* ES2.0, and the same is applicable for DRA7.
|
|
*/
|
|
if (soc_is_omap54xx() || soc_is_dra7xx()) {
|
|
val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE);
|
|
val |= BIT(5);
|
|
omap_smc1(OMAP5_MON_AMBA_IF_INDEX, val);
|
|
}
|
|
|
|
irq_hotplug_init();
|
|
irq_pm_init();
|
|
|
|
sar_base = omap4_get_sar_ram_base();
|
|
|
|
return 0;
|
|
}
|
|
IRQCHIP_DECLARE(ti_wakeupgen, "ti,omap4-wugen-mpu", wakeupgen_init);
|