898 lines
22 KiB
C
898 lines
22 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
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*
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* Copyright (C) 1996-2000 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASSEMBLY__
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#error "Only include this from assembly code"
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#endif
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#ifndef __ASM_ASSEMBLER_H
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#define __ASM_ASSEMBLER_H
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#include <asm-generic/export.h>
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#include <asm/alternative.h>
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#include <asm/asm-bug.h>
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#include <asm/asm-extable.h>
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#include <asm/asm-offsets.h>
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#include <asm/cpufeature.h>
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#include <asm/cputype.h>
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#include <asm/debug-monitors.h>
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#include <asm/page.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/ptrace.h>
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#include <asm/thread_info.h>
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/*
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* Provide a wxN alias for each wN register so what we can paste a xN
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* reference after a 'w' to obtain the 32-bit version.
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*/
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.irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
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wx\n .req w\n
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.endr
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.macro disable_daif
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msr daifset, #0xf
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.endm
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.macro enable_daif
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msr daifclr, #0xf
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.endm
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/*
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* Save/restore interrupts.
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*/
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.macro save_and_disable_irq, flags
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mrs \flags, daif
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msr daifset, #3
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.endm
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.macro restore_irq, flags
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msr daif, \flags
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.endm
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.macro enable_dbg
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msr daifclr, #8
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.endm
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.macro disable_step_tsk, flgs, tmp
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tbz \flgs, #TIF_SINGLESTEP, 9990f
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mrs \tmp, mdscr_el1
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bic \tmp, \tmp, #DBG_MDSCR_SS
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msr mdscr_el1, \tmp
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isb // Synchronise with enable_dbg
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9990:
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.endm
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/* call with daif masked */
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.macro enable_step_tsk, flgs, tmp
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tbz \flgs, #TIF_SINGLESTEP, 9990f
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mrs \tmp, mdscr_el1
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orr \tmp, \tmp, #DBG_MDSCR_SS
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msr mdscr_el1, \tmp
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9990:
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.endm
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/*
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* RAS Error Synchronization barrier
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*/
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.macro esb
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#ifdef CONFIG_ARM64_RAS_EXTN
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hint #16
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#else
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nop
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#endif
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.endm
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/*
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* Value prediction barrier
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*/
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.macro csdb
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hint #20
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.endm
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/*
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* Clear Branch History instruction
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*/
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.macro clearbhb
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hint #22
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.endm
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/*
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* Speculation barrier
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*/
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.macro sb
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alternative_if_not ARM64_HAS_SB
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dsb nsh
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isb
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alternative_else
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SB_BARRIER_INSN
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nop
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alternative_endif
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.endm
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/*
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* NOP sequence
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*/
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.macro nops, num
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.rept \num
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nop
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.endr
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.endm
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/*
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* Register aliases.
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*/
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lr .req x30 // link register
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/*
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* Vector entry
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*/
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.macro ventry label
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.align 7
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b \label
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.endm
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/*
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* Select code when configured for BE.
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*/
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#ifdef CONFIG_CPU_BIG_ENDIAN
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#define CPU_BE(code...) code
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#else
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#define CPU_BE(code...)
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#endif
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/*
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* Select code when configured for LE.
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*/
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#ifdef CONFIG_CPU_BIG_ENDIAN
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#define CPU_LE(code...)
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#else
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#define CPU_LE(code...) code
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#endif
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/*
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* Define a macro that constructs a 64-bit value by concatenating two
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* 32-bit registers. Note that on big endian systems the order of the
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* registers is swapped.
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*/
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#ifndef CONFIG_CPU_BIG_ENDIAN
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.macro regs_to_64, rd, lbits, hbits
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#else
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.macro regs_to_64, rd, hbits, lbits
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#endif
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orr \rd, \lbits, \hbits, lsl #32
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.endm
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/*
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* Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
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* <symbol> is within the range +/- 4 GB of the PC.
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*/
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/*
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* @dst: destination register (64 bit wide)
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* @sym: name of the symbol
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*/
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.macro adr_l, dst, sym
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adrp \dst, \sym
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add \dst, \dst, :lo12:\sym
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.endm
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/*
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* @dst: destination register (32 or 64 bit wide)
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* @sym: name of the symbol
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* @tmp: optional 64-bit scratch register to be used if <dst> is a
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* 32-bit wide register, in which case it cannot be used to hold
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* the address
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*/
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.macro ldr_l, dst, sym, tmp=
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.ifb \tmp
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adrp \dst, \sym
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ldr \dst, [\dst, :lo12:\sym]
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.else
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adrp \tmp, \sym
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ldr \dst, [\tmp, :lo12:\sym]
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.endif
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.endm
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/*
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* @src: source register (32 or 64 bit wide)
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* @sym: name of the symbol
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* @tmp: mandatory 64-bit scratch register to calculate the address
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* while <src> needs to be preserved.
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*/
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.macro str_l, src, sym, tmp
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adrp \tmp, \sym
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str \src, [\tmp, :lo12:\sym]
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.endm
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/*
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* @dst: destination register
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*/
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#if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__)
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.macro get_this_cpu_offset, dst
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mrs \dst, tpidr_el2
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.endm
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#else
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.macro get_this_cpu_offset, dst
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alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
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mrs \dst, tpidr_el1
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alternative_else
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mrs \dst, tpidr_el2
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alternative_endif
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.endm
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.macro set_this_cpu_offset, src
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alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
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msr tpidr_el1, \src
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alternative_else
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msr tpidr_el2, \src
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alternative_endif
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.endm
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#endif
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/*
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* @dst: Result of per_cpu(sym, smp_processor_id()) (can be SP)
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* @sym: The name of the per-cpu variable
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* @tmp: scratch register
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*/
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.macro adr_this_cpu, dst, sym, tmp
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adrp \tmp, \sym
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add \dst, \tmp, #:lo12:\sym
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get_this_cpu_offset \tmp
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add \dst, \dst, \tmp
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.endm
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/*
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* @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id()))
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* @sym: The name of the per-cpu variable
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* @tmp: scratch register
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*/
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.macro ldr_this_cpu dst, sym, tmp
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adr_l \dst, \sym
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get_this_cpu_offset \tmp
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ldr \dst, [\dst, \tmp]
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.endm
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/*
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* vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
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*/
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.macro vma_vm_mm, rd, rn
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ldr \rd, [\rn, #VMA_VM_MM]
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.endm
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/*
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* read_ctr - read CTR_EL0. If the system has mismatched register fields,
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* provide the system wide safe value from arm64_ftr_reg_ctrel0.sys_val
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*/
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.macro read_ctr, reg
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#ifndef __KVM_NVHE_HYPERVISOR__
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alternative_if_not ARM64_MISMATCHED_CACHE_TYPE
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mrs \reg, ctr_el0 // read CTR
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nop
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alternative_else
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ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL
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alternative_endif
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#else
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alternative_if_not ARM64_KVM_PROTECTED_MODE
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ASM_BUG()
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alternative_else_nop_endif
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alternative_cb ARM64_ALWAYS_SYSTEM, kvm_compute_final_ctr_el0
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movz \reg, #0
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movk \reg, #0, lsl #16
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movk \reg, #0, lsl #32
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movk \reg, #0, lsl #48
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alternative_cb_end
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#endif
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.endm
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/*
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* raw_dcache_line_size - get the minimum D-cache line size on this CPU
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* from the CTR register.
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*/
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.macro raw_dcache_line_size, reg, tmp
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mrs \tmp, ctr_el0 // read CTR
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ubfm \tmp, \tmp, #16, #19 // cache line size encoding
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mov \reg, #4 // bytes per word
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lsl \reg, \reg, \tmp // actual cache line size
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.endm
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/*
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* dcache_line_size - get the safe D-cache line size across all CPUs
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*/
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.macro dcache_line_size, reg, tmp
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read_ctr \tmp
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ubfm \tmp, \tmp, #16, #19 // cache line size encoding
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mov \reg, #4 // bytes per word
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lsl \reg, \reg, \tmp // actual cache line size
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.endm
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/*
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* raw_icache_line_size - get the minimum I-cache line size on this CPU
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* from the CTR register.
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*/
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.macro raw_icache_line_size, reg, tmp
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mrs \tmp, ctr_el0 // read CTR
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and \tmp, \tmp, #0xf // cache line size encoding
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mov \reg, #4 // bytes per word
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lsl \reg, \reg, \tmp // actual cache line size
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.endm
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/*
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* icache_line_size - get the safe I-cache line size across all CPUs
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*/
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.macro icache_line_size, reg, tmp
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read_ctr \tmp
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and \tmp, \tmp, #0xf // cache line size encoding
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mov \reg, #4 // bytes per word
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lsl \reg, \reg, \tmp // actual cache line size
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.endm
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/*
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* tcr_set_t0sz - update TCR.T0SZ so that we can load the ID map
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*/
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.macro tcr_set_t0sz, valreg, t0sz
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bfi \valreg, \t0sz, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
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.endm
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/*
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* tcr_set_t1sz - update TCR.T1SZ
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*/
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.macro tcr_set_t1sz, valreg, t1sz
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bfi \valreg, \t1sz, #TCR_T1SZ_OFFSET, #TCR_TxSZ_WIDTH
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.endm
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/*
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* idmap_get_t0sz - get the T0SZ value needed to cover the ID map
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*
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* Calculate the maximum allowed value for TCR_EL1.T0SZ so that the
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* entire ID map region can be mapped. As T0SZ == (64 - #bits used),
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* this number conveniently equals the number of leading zeroes in
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* the physical address of _end.
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*/
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.macro idmap_get_t0sz, reg
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adrp \reg, _end
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orr \reg, \reg, #(1 << VA_BITS_MIN) - 1
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clz \reg, \reg
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.endm
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/*
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* tcr_compute_pa_size - set TCR.(I)PS to the highest supported
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* ID_AA64MMFR0_EL1.PARange value
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*
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* tcr: register with the TCR_ELx value to be updated
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* pos: IPS or PS bitfield position
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* tmp{0,1}: temporary registers
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*/
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.macro tcr_compute_pa_size, tcr, pos, tmp0, tmp1
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mrs \tmp0, ID_AA64MMFR0_EL1
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// Narrow PARange to fit the PS field in TCR_ELx
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ubfx \tmp0, \tmp0, #ID_AA64MMFR0_EL1_PARANGE_SHIFT, #3
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mov \tmp1, #ID_AA64MMFR0_EL1_PARANGE_MAX
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cmp \tmp0, \tmp1
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csel \tmp0, \tmp1, \tmp0, hi
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bfi \tcr, \tmp0, \pos, #3
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.endm
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.macro __dcache_op_workaround_clean_cache, op, addr
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alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
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dc \op, \addr
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alternative_else
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dc civac, \addr
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alternative_endif
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.endm
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/*
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* Macro to perform a data cache maintenance for the interval
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* [start, end) with dcache line size explicitly provided.
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*
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* op: operation passed to dc instruction
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* domain: domain used in dsb instruciton
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* start: starting virtual address of the region
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* end: end virtual address of the region
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* linesz: dcache line size
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* fixup: optional label to branch to on user fault
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* Corrupts: start, end, tmp
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*/
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.macro dcache_by_myline_op op, domain, start, end, linesz, tmp, fixup
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sub \tmp, \linesz, #1
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bic \start, \start, \tmp
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.Ldcache_op\@:
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.ifc \op, cvau
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__dcache_op_workaround_clean_cache \op, \start
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.else
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.ifc \op, cvac
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__dcache_op_workaround_clean_cache \op, \start
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.else
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.ifc \op, cvap
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sys 3, c7, c12, 1, \start // dc cvap
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.else
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.ifc \op, cvadp
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sys 3, c7, c13, 1, \start // dc cvadp
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.else
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dc \op, \start
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.endif
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.endif
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.endif
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.endif
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add \start, \start, \linesz
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cmp \start, \end
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b.lo .Ldcache_op\@
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dsb \domain
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_cond_uaccess_extable .Ldcache_op\@, \fixup
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.endm
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/*
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* Macro to perform a data cache maintenance for the interval
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* [start, end)
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*
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* op: operation passed to dc instruction
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* domain: domain used in dsb instruciton
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* start: starting virtual address of the region
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* end: end virtual address of the region
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* fixup: optional label to branch to on user fault
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* Corrupts: start, end, tmp1, tmp2
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*/
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.macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup
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dcache_line_size \tmp1, \tmp2
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dcache_by_myline_op \op, \domain, \start, \end, \tmp1, \tmp2, \fixup
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.endm
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/*
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* Macro to perform an instruction cache maintenance for the interval
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* [start, end)
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*
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* start, end: virtual addresses describing the region
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* fixup: optional label to branch to on user fault
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* Corrupts: tmp1, tmp2
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*/
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.macro invalidate_icache_by_line start, end, tmp1, tmp2, fixup
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icache_line_size \tmp1, \tmp2
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sub \tmp2, \tmp1, #1
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bic \tmp2, \start, \tmp2
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.Licache_op\@:
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ic ivau, \tmp2 // invalidate I line PoU
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add \tmp2, \tmp2, \tmp1
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cmp \tmp2, \end
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b.lo .Licache_op\@
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dsb ish
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isb
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_cond_uaccess_extable .Licache_op\@, \fixup
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.endm
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/*
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* load_ttbr1 - install @pgtbl as a TTBR1 page table
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* pgtbl preserved
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* tmp1/tmp2 clobbered, either may overlap with pgtbl
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*/
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.macro load_ttbr1, pgtbl, tmp1, tmp2
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phys_to_ttbr \tmp1, \pgtbl
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offset_ttbr1 \tmp1, \tmp2
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msr ttbr1_el1, \tmp1
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isb
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.endm
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/*
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* To prevent the possibility of old and new partial table walks being visible
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* in the tlb, switch the ttbr to a zero page when we invalidate the old
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* records. D4.7.1 'General TLB maintenance requirements' in ARM DDI 0487A.i
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* Even switching to our copied tables will cause a changed output address at
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* each stage of the walk.
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*/
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.macro break_before_make_ttbr_switch zero_page, page_table, tmp, tmp2
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phys_to_ttbr \tmp, \zero_page
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msr ttbr1_el1, \tmp
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isb
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tlbi vmalle1
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dsb nsh
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load_ttbr1 \page_table, \tmp, \tmp2
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.endm
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/*
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* reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
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*/
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.macro reset_pmuserenr_el0, tmpreg
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mrs \tmpreg, id_aa64dfr0_el1
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sbfx \tmpreg, \tmpreg, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
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cmp \tmpreg, #1 // Skip if no PMU present
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b.lt 9000f
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msr pmuserenr_el0, xzr // Disable PMU access from EL0
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9000:
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.endm
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/*
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* reset_amuserenr_el0 - reset AMUSERENR_EL0 if AMUv1 present
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*/
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.macro reset_amuserenr_el0, tmpreg
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mrs \tmpreg, id_aa64pfr0_el1 // Check ID_AA64PFR0_EL1
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ubfx \tmpreg, \tmpreg, #ID_AA64PFR0_EL1_AMU_SHIFT, #4
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cbz \tmpreg, .Lskip_\@ // Skip if no AMU present
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msr_s SYS_AMUSERENR_EL0, xzr // Disable AMU access from EL0
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.Lskip_\@:
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.endm
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/*
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* copy_page - copy src to dest using temp registers t1-t8
|
|
*/
|
|
.macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
|
|
9998: ldp \t1, \t2, [\src]
|
|
ldp \t3, \t4, [\src, #16]
|
|
ldp \t5, \t6, [\src, #32]
|
|
ldp \t7, \t8, [\src, #48]
|
|
add \src, \src, #64
|
|
stnp \t1, \t2, [\dest]
|
|
stnp \t3, \t4, [\dest, #16]
|
|
stnp \t5, \t6, [\dest, #32]
|
|
stnp \t7, \t8, [\dest, #48]
|
|
add \dest, \dest, #64
|
|
tst \src, #(PAGE_SIZE - 1)
|
|
b.ne 9998b
|
|
.endm
|
|
|
|
/*
|
|
* Annotate a function as being unsuitable for kprobes.
|
|
*/
|
|
#ifdef CONFIG_KPROBES
|
|
#define NOKPROBE(x) \
|
|
.pushsection "_kprobe_blacklist", "aw"; \
|
|
.quad x; \
|
|
.popsection;
|
|
#else
|
|
#define NOKPROBE(x)
|
|
#endif
|
|
|
|
#if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)
|
|
#define EXPORT_SYMBOL_NOKASAN(name)
|
|
#else
|
|
#define EXPORT_SYMBOL_NOKASAN(name) EXPORT_SYMBOL(name)
|
|
#endif
|
|
|
|
/*
|
|
* Emit a 64-bit absolute little endian symbol reference in a way that
|
|
* ensures that it will be resolved at build time, even when building a
|
|
* PIE binary. This requires cooperation from the linker script, which
|
|
* must emit the lo32/hi32 halves individually.
|
|
*/
|
|
.macro le64sym, sym
|
|
.long \sym\()_lo32
|
|
.long \sym\()_hi32
|
|
.endm
|
|
|
|
/*
|
|
* mov_q - move an immediate constant into a 64-bit register using
|
|
* between 2 and 4 movz/movk instructions (depending on the
|
|
* magnitude and sign of the operand)
|
|
*/
|
|
.macro mov_q, reg, val
|
|
.if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
|
|
movz \reg, :abs_g1_s:\val
|
|
.else
|
|
.if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
|
|
movz \reg, :abs_g2_s:\val
|
|
.else
|
|
movz \reg, :abs_g3:\val
|
|
movk \reg, :abs_g2_nc:\val
|
|
.endif
|
|
movk \reg, :abs_g1_nc:\val
|
|
.endif
|
|
movk \reg, :abs_g0_nc:\val
|
|
.endm
|
|
|
|
/*
|
|
* Return the current task_struct.
|
|
*/
|
|
.macro get_current_task, rd
|
|
mrs \rd, sp_el0
|
|
.endm
|
|
|
|
/*
|
|
* Offset ttbr1 to allow for 48-bit kernel VAs set with 52-bit PTRS_PER_PGD.
|
|
* orr is used as it can cover the immediate value (and is idempotent).
|
|
* In future this may be nop'ed out when dealing with 52-bit kernel VAs.
|
|
* ttbr: Value of ttbr to set, modified.
|
|
*/
|
|
.macro offset_ttbr1, ttbr, tmp
|
|
#ifdef CONFIG_ARM64_VA_BITS_52
|
|
mrs_s \tmp, SYS_ID_AA64MMFR2_EL1
|
|
and \tmp, \tmp, #(0xf << ID_AA64MMFR2_EL1_VARange_SHIFT)
|
|
cbnz \tmp, .Lskipoffs_\@
|
|
orr \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
|
|
.Lskipoffs_\@ :
|
|
#endif
|
|
.endm
|
|
|
|
/*
|
|
* Arrange a physical address in a TTBR register, taking care of 52-bit
|
|
* addresses.
|
|
*
|
|
* phys: physical address, preserved
|
|
* ttbr: returns the TTBR value
|
|
*/
|
|
.macro phys_to_ttbr, ttbr, phys
|
|
#ifdef CONFIG_ARM64_PA_BITS_52
|
|
orr \ttbr, \phys, \phys, lsr #46
|
|
and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
|
|
#else
|
|
mov \ttbr, \phys
|
|
#endif
|
|
.endm
|
|
|
|
.macro phys_to_pte, pte, phys
|
|
#ifdef CONFIG_ARM64_PA_BITS_52
|
|
/*
|
|
* We assume \phys is 64K aligned and this is guaranteed by only
|
|
* supporting this configuration with 64K pages.
|
|
*/
|
|
orr \pte, \phys, \phys, lsr #36
|
|
and \pte, \pte, #PTE_ADDR_MASK
|
|
#else
|
|
mov \pte, \phys
|
|
#endif
|
|
.endm
|
|
|
|
.macro pte_to_phys, phys, pte
|
|
and \phys, \pte, #PTE_ADDR_MASK
|
|
#ifdef CONFIG_ARM64_PA_BITS_52
|
|
orr \phys, \phys, \phys, lsl #PTE_ADDR_HIGH_SHIFT
|
|
and \phys, \phys, GENMASK_ULL(PHYS_MASK_SHIFT - 1, PAGE_SHIFT)
|
|
#endif
|
|
.endm
|
|
|
|
/*
|
|
* tcr_clear_errata_bits - Clear TCR bits that trigger an errata on this CPU.
|
|
*/
|
|
.macro tcr_clear_errata_bits, tcr, tmp1, tmp2
|
|
#ifdef CONFIG_FUJITSU_ERRATUM_010001
|
|
mrs \tmp1, midr_el1
|
|
|
|
mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001_MASK
|
|
and \tmp1, \tmp1, \tmp2
|
|
mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001
|
|
cmp \tmp1, \tmp2
|
|
b.ne 10f
|
|
|
|
mov_q \tmp2, TCR_CLEAR_FUJITSU_ERRATUM_010001
|
|
bic \tcr, \tcr, \tmp2
|
|
10:
|
|
#endif /* CONFIG_FUJITSU_ERRATUM_010001 */
|
|
.endm
|
|
|
|
/**
|
|
* Errata workaround prior to disable MMU. Insert an ISB immediately prior
|
|
* to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
|
|
*/
|
|
.macro pre_disable_mmu_workaround
|
|
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
|
|
isb
|
|
#endif
|
|
.endm
|
|
|
|
/*
|
|
* frame_push - Push @regcount callee saved registers to the stack,
|
|
* starting at x19, as well as x29/x30, and set x29 to
|
|
* the new value of sp. Add @extra bytes of stack space
|
|
* for locals.
|
|
*/
|
|
.macro frame_push, regcount:req, extra
|
|
__frame st, \regcount, \extra
|
|
.endm
|
|
|
|
/*
|
|
* frame_pop - Pop the callee saved registers from the stack that were
|
|
* pushed in the most recent call to frame_push, as well
|
|
* as x29/x30 and any extra stack space that may have been
|
|
* allocated.
|
|
*/
|
|
.macro frame_pop
|
|
__frame ld
|
|
.endm
|
|
|
|
.macro __frame_regs, reg1, reg2, op, num
|
|
.if .Lframe_regcount == \num
|
|
\op\()r \reg1, [sp, #(\num + 1) * 8]
|
|
.elseif .Lframe_regcount > \num
|
|
\op\()p \reg1, \reg2, [sp, #(\num + 1) * 8]
|
|
.endif
|
|
.endm
|
|
|
|
.macro __frame, op, regcount, extra=0
|
|
.ifc \op, st
|
|
.if (\regcount) < 0 || (\regcount) > 10
|
|
.error "regcount should be in the range [0 ... 10]"
|
|
.endif
|
|
.if ((\extra) % 16) != 0
|
|
.error "extra should be a multiple of 16 bytes"
|
|
.endif
|
|
.ifdef .Lframe_regcount
|
|
.if .Lframe_regcount != -1
|
|
.error "frame_push/frame_pop may not be nested"
|
|
.endif
|
|
.endif
|
|
.set .Lframe_regcount, \regcount
|
|
.set .Lframe_extra, \extra
|
|
.set .Lframe_local_offset, ((\regcount + 3) / 2) * 16
|
|
stp x29, x30, [sp, #-.Lframe_local_offset - .Lframe_extra]!
|
|
mov x29, sp
|
|
.endif
|
|
|
|
__frame_regs x19, x20, \op, 1
|
|
__frame_regs x21, x22, \op, 3
|
|
__frame_regs x23, x24, \op, 5
|
|
__frame_regs x25, x26, \op, 7
|
|
__frame_regs x27, x28, \op, 9
|
|
|
|
.ifc \op, ld
|
|
.if .Lframe_regcount == -1
|
|
.error "frame_push/frame_pop may not be nested"
|
|
.endif
|
|
ldp x29, x30, [sp], #.Lframe_local_offset + .Lframe_extra
|
|
.set .Lframe_regcount, -1
|
|
.endif
|
|
.endm
|
|
|
|
/*
|
|
* Set SCTLR_ELx to the @reg value, and invalidate the local icache
|
|
* in the process. This is called when setting the MMU on.
|
|
*/
|
|
.macro set_sctlr, sreg, reg
|
|
msr \sreg, \reg
|
|
isb
|
|
/*
|
|
* Invalidate the local I-cache so that any instructions fetched
|
|
* speculatively from the PoC are discarded, since they may have
|
|
* been dynamically patched at the PoU.
|
|
*/
|
|
ic iallu
|
|
dsb nsh
|
|
isb
|
|
.endm
|
|
|
|
.macro set_sctlr_el1, reg
|
|
set_sctlr sctlr_el1, \reg
|
|
.endm
|
|
|
|
.macro set_sctlr_el2, reg
|
|
set_sctlr sctlr_el2, \reg
|
|
.endm
|
|
|
|
/*
|
|
* Check whether preempt/bh-disabled asm code should yield as soon as
|
|
* it is able. This is the case if we are currently running in task
|
|
* context, and either a softirq is pending, or the TIF_NEED_RESCHED
|
|
* flag is set and re-enabling preemption a single time would result in
|
|
* a preempt count of zero. (Note that the TIF_NEED_RESCHED flag is
|
|
* stored negated in the top word of the thread_info::preempt_count
|
|
* field)
|
|
*/
|
|
.macro cond_yield, lbl:req, tmp:req, tmp2:req
|
|
get_current_task \tmp
|
|
ldr \tmp, [\tmp, #TSK_TI_PREEMPT]
|
|
/*
|
|
* If we are serving a softirq, there is no point in yielding: the
|
|
* softirq will not be preempted no matter what we do, so we should
|
|
* run to completion as quickly as we can.
|
|
*/
|
|
tbnz \tmp, #SOFTIRQ_SHIFT, .Lnoyield_\@
|
|
#ifdef CONFIG_PREEMPTION
|
|
sub \tmp, \tmp, #PREEMPT_DISABLE_OFFSET
|
|
cbz \tmp, \lbl
|
|
#endif
|
|
adr_l \tmp, irq_stat + IRQ_CPUSTAT_SOFTIRQ_PENDING
|
|
get_this_cpu_offset \tmp2
|
|
ldr w\tmp, [\tmp, \tmp2]
|
|
cbnz w\tmp, \lbl // yield on pending softirq in task context
|
|
.Lnoyield_\@:
|
|
.endm
|
|
|
|
/*
|
|
* Branch Target Identifier (BTI)
|
|
*/
|
|
.macro bti, targets
|
|
.equ .L__bti_targets_c, 34
|
|
.equ .L__bti_targets_j, 36
|
|
.equ .L__bti_targets_jc,38
|
|
hint #.L__bti_targets_\targets
|
|
.endm
|
|
|
|
/*
|
|
* This macro emits a program property note section identifying
|
|
* architecture features which require special handling, mainly for
|
|
* use in assembly files included in the VDSO.
|
|
*/
|
|
|
|
#define NT_GNU_PROPERTY_TYPE_0 5
|
|
#define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
|
|
|
|
#define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0)
|
|
#define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1)
|
|
|
|
#ifdef CONFIG_ARM64_BTI_KERNEL
|
|
#define GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT \
|
|
((GNU_PROPERTY_AARCH64_FEATURE_1_BTI | \
|
|
GNU_PROPERTY_AARCH64_FEATURE_1_PAC))
|
|
#endif
|
|
|
|
#ifdef GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT
|
|
.macro emit_aarch64_feature_1_and, feat=GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT
|
|
.pushsection .note.gnu.property, "a"
|
|
.align 3
|
|
.long 2f - 1f
|
|
.long 6f - 3f
|
|
.long NT_GNU_PROPERTY_TYPE_0
|
|
1: .string "GNU"
|
|
2:
|
|
.align 3
|
|
3: .long GNU_PROPERTY_AARCH64_FEATURE_1_AND
|
|
.long 5f - 4f
|
|
4:
|
|
/*
|
|
* This is described with an array of char in the Linux API
|
|
* spec but the text and all other usage (including binutils,
|
|
* clang and GCC) treat this as a 32 bit value so no swizzling
|
|
* is required for big endian.
|
|
*/
|
|
.long \feat
|
|
5:
|
|
.align 3
|
|
6:
|
|
.popsection
|
|
.endm
|
|
|
|
#else
|
|
.macro emit_aarch64_feature_1_and, feat=0
|
|
.endm
|
|
|
|
#endif /* GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT */
|
|
|
|
.macro __mitigate_spectre_bhb_loop tmp
|
|
#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
|
|
alternative_cb ARM64_ALWAYS_SYSTEM, spectre_bhb_patch_loop_iter
|
|
mov \tmp, #32 // Patched to correct the immediate
|
|
alternative_cb_end
|
|
.Lspectre_bhb_loop\@:
|
|
b . + 4
|
|
subs \tmp, \tmp, #1
|
|
b.ne .Lspectre_bhb_loop\@
|
|
sb
|
|
#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
|
|
.endm
|
|
|
|
.macro mitigate_spectre_bhb_loop tmp
|
|
#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
|
|
alternative_cb ARM64_ALWAYS_SYSTEM, spectre_bhb_patch_loop_mitigation_enable
|
|
b .L_spectre_bhb_loop_done\@ // Patched to NOP
|
|
alternative_cb_end
|
|
__mitigate_spectre_bhb_loop \tmp
|
|
.L_spectre_bhb_loop_done\@:
|
|
#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
|
|
.endm
|
|
|
|
/* Save/restores x0-x3 to the stack */
|
|
.macro __mitigate_spectre_bhb_fw
|
|
#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
|
|
stp x0, x1, [sp, #-16]!
|
|
stp x2, x3, [sp, #-16]!
|
|
mov w0, #ARM_SMCCC_ARCH_WORKAROUND_3
|
|
alternative_cb ARM64_ALWAYS_SYSTEM, smccc_patch_fw_mitigation_conduit
|
|
nop // Patched to SMC/HVC #0
|
|
alternative_cb_end
|
|
ldp x2, x3, [sp], #16
|
|
ldp x0, x1, [sp], #16
|
|
#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
|
|
.endm
|
|
|
|
.macro mitigate_spectre_bhb_clear_insn
|
|
#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
|
|
alternative_cb ARM64_ALWAYS_SYSTEM, spectre_bhb_patch_clearbhb
|
|
/* Patched to NOP when not supported */
|
|
clearbhb
|
|
isb
|
|
alternative_cb_end
|
|
#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
|
|
.endm
|
|
#endif /* __ASM_ASSEMBLER_H */
|