316 lines
8.2 KiB
C
316 lines
8.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Based on arch/arm/include/asm/atomic.h
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*
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* Copyright (C) 1996 Russell King.
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* Copyright (C) 2002 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_ATOMIC_LSE_H
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#define __ASM_ATOMIC_LSE_H
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#define ATOMIC_OP(op, asm_op) \
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static __always_inline void \
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__lse_atomic_##op(int i, atomic_t *v) \
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{ \
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asm volatile( \
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__LSE_PREAMBLE \
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" " #asm_op " %w[i], %[v]\n" \
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: [v] "+Q" (v->counter) \
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: [i] "r" (i)); \
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}
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ATOMIC_OP(andnot, stclr)
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ATOMIC_OP(or, stset)
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ATOMIC_OP(xor, steor)
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ATOMIC_OP(add, stadd)
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static __always_inline void __lse_atomic_sub(int i, atomic_t *v)
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{
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__lse_atomic_add(-i, v);
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}
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#undef ATOMIC_OP
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#define ATOMIC_FETCH_OP(name, mb, op, asm_op, cl...) \
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static __always_inline int \
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__lse_atomic_fetch_##op##name(int i, atomic_t *v) \
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{ \
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int old; \
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\
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asm volatile( \
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__LSE_PREAMBLE \
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" " #asm_op #mb " %w[i], %w[old], %[v]" \
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: [v] "+Q" (v->counter), \
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[old] "=r" (old) \
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: [i] "r" (i) \
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: cl); \
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\
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return old; \
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}
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#define ATOMIC_FETCH_OPS(op, asm_op) \
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ATOMIC_FETCH_OP(_relaxed, , op, asm_op) \
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ATOMIC_FETCH_OP(_acquire, a, op, asm_op, "memory") \
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ATOMIC_FETCH_OP(_release, l, op, asm_op, "memory") \
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ATOMIC_FETCH_OP( , al, op, asm_op, "memory")
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ATOMIC_FETCH_OPS(andnot, ldclr)
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ATOMIC_FETCH_OPS(or, ldset)
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ATOMIC_FETCH_OPS(xor, ldeor)
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ATOMIC_FETCH_OPS(add, ldadd)
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_FETCH_OPS
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#define ATOMIC_FETCH_OP_SUB(name) \
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static __always_inline int \
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__lse_atomic_fetch_sub##name(int i, atomic_t *v) \
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{ \
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return __lse_atomic_fetch_add##name(-i, v); \
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}
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ATOMIC_FETCH_OP_SUB(_relaxed)
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ATOMIC_FETCH_OP_SUB(_acquire)
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ATOMIC_FETCH_OP_SUB(_release)
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ATOMIC_FETCH_OP_SUB( )
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#undef ATOMIC_FETCH_OP_SUB
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#define ATOMIC_OP_ADD_SUB_RETURN(name) \
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static __always_inline int \
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__lse_atomic_add_return##name(int i, atomic_t *v) \
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{ \
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return __lse_atomic_fetch_add##name(i, v) + i; \
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} \
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\
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static __always_inline int \
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__lse_atomic_sub_return##name(int i, atomic_t *v) \
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{ \
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return __lse_atomic_fetch_sub(i, v) - i; \
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}
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ATOMIC_OP_ADD_SUB_RETURN(_relaxed)
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ATOMIC_OP_ADD_SUB_RETURN(_acquire)
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ATOMIC_OP_ADD_SUB_RETURN(_release)
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ATOMIC_OP_ADD_SUB_RETURN( )
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#undef ATOMIC_OP_ADD_SUB_RETURN
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static __always_inline void __lse_atomic_and(int i, atomic_t *v)
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{
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return __lse_atomic_andnot(~i, v);
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}
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#define ATOMIC_FETCH_OP_AND(name, mb, cl...) \
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static __always_inline int \
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__lse_atomic_fetch_and##name(int i, atomic_t *v) \
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{ \
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return __lse_atomic_fetch_andnot##name(~i, v); \
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}
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ATOMIC_FETCH_OP_AND(_relaxed, )
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ATOMIC_FETCH_OP_AND(_acquire, a, "memory")
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ATOMIC_FETCH_OP_AND(_release, l, "memory")
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ATOMIC_FETCH_OP_AND( , al, "memory")
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#undef ATOMIC_FETCH_OP_AND
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#define ATOMIC64_OP(op, asm_op) \
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static __always_inline void \
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__lse_atomic64_##op(s64 i, atomic64_t *v) \
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{ \
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asm volatile( \
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__LSE_PREAMBLE \
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" " #asm_op " %[i], %[v]\n" \
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: [v] "+Q" (v->counter) \
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: [i] "r" (i)); \
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}
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ATOMIC64_OP(andnot, stclr)
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ATOMIC64_OP(or, stset)
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ATOMIC64_OP(xor, steor)
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ATOMIC64_OP(add, stadd)
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static __always_inline void __lse_atomic64_sub(s64 i, atomic64_t *v)
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{
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__lse_atomic64_add(-i, v);
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}
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#undef ATOMIC64_OP
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#define ATOMIC64_FETCH_OP(name, mb, op, asm_op, cl...) \
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static __always_inline long \
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__lse_atomic64_fetch_##op##name(s64 i, atomic64_t *v) \
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{ \
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s64 old; \
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\
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asm volatile( \
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__LSE_PREAMBLE \
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" " #asm_op #mb " %[i], %[old], %[v]" \
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: [v] "+Q" (v->counter), \
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[old] "=r" (old) \
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: [i] "r" (i) \
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: cl); \
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\
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return old; \
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}
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#define ATOMIC64_FETCH_OPS(op, asm_op) \
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ATOMIC64_FETCH_OP(_relaxed, , op, asm_op) \
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ATOMIC64_FETCH_OP(_acquire, a, op, asm_op, "memory") \
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ATOMIC64_FETCH_OP(_release, l, op, asm_op, "memory") \
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ATOMIC64_FETCH_OP( , al, op, asm_op, "memory")
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ATOMIC64_FETCH_OPS(andnot, ldclr)
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ATOMIC64_FETCH_OPS(or, ldset)
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ATOMIC64_FETCH_OPS(xor, ldeor)
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ATOMIC64_FETCH_OPS(add, ldadd)
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#undef ATOMIC64_FETCH_OP
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#undef ATOMIC64_FETCH_OPS
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#define ATOMIC64_FETCH_OP_SUB(name) \
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static __always_inline long \
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__lse_atomic64_fetch_sub##name(s64 i, atomic64_t *v) \
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{ \
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return __lse_atomic64_fetch_add##name(-i, v); \
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}
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ATOMIC64_FETCH_OP_SUB(_relaxed)
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ATOMIC64_FETCH_OP_SUB(_acquire)
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ATOMIC64_FETCH_OP_SUB(_release)
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ATOMIC64_FETCH_OP_SUB( )
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#undef ATOMIC64_FETCH_OP_SUB
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#define ATOMIC64_OP_ADD_SUB_RETURN(name) \
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static __always_inline long \
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__lse_atomic64_add_return##name(s64 i, atomic64_t *v) \
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{ \
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return __lse_atomic64_fetch_add##name(i, v) + i; \
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} \
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\
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static __always_inline long \
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__lse_atomic64_sub_return##name(s64 i, atomic64_t *v) \
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{ \
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return __lse_atomic64_fetch_sub##name(i, v) - i; \
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}
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ATOMIC64_OP_ADD_SUB_RETURN(_relaxed)
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ATOMIC64_OP_ADD_SUB_RETURN(_acquire)
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ATOMIC64_OP_ADD_SUB_RETURN(_release)
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ATOMIC64_OP_ADD_SUB_RETURN( )
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#undef ATOMIC64_OP_ADD_SUB_RETURN
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static __always_inline void __lse_atomic64_and(s64 i, atomic64_t *v)
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{
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return __lse_atomic64_andnot(~i, v);
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}
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#define ATOMIC64_FETCH_OP_AND(name, mb, cl...) \
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static __always_inline long \
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__lse_atomic64_fetch_and##name(s64 i, atomic64_t *v) \
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{ \
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return __lse_atomic64_fetch_andnot##name(~i, v); \
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}
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ATOMIC64_FETCH_OP_AND(_relaxed, )
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ATOMIC64_FETCH_OP_AND(_acquire, a, "memory")
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ATOMIC64_FETCH_OP_AND(_release, l, "memory")
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ATOMIC64_FETCH_OP_AND( , al, "memory")
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#undef ATOMIC64_FETCH_OP_AND
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static __always_inline s64 __lse_atomic64_dec_if_positive(atomic64_t *v)
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{
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unsigned long tmp;
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asm volatile(
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__LSE_PREAMBLE
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"1: ldr %x[tmp], %[v]\n"
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" subs %[ret], %x[tmp], #1\n"
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" b.lt 2f\n"
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" casal %x[tmp], %[ret], %[v]\n"
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" sub %x[tmp], %x[tmp], #1\n"
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" sub %x[tmp], %x[tmp], %[ret]\n"
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" cbnz %x[tmp], 1b\n"
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"2:"
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: [ret] "+&r" (v), [v] "+Q" (v->counter), [tmp] "=&r" (tmp)
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:
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: "cc", "memory");
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return (long)v;
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}
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#define __CMPXCHG_CASE(w, sfx, name, sz, mb, cl...) \
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static __always_inline u##sz \
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__lse__cmpxchg_case_##name##sz(volatile void *ptr, \
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u##sz old, \
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u##sz new) \
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{ \
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asm volatile( \
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__LSE_PREAMBLE \
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" cas" #mb #sfx " %" #w "[old], %" #w "[new], %[v]\n" \
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: [v] "+Q" (*(u##sz *)ptr), \
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[old] "+r" (old) \
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: [new] "rZ" (new) \
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: cl); \
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\
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return old; \
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}
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__CMPXCHG_CASE(w, b, , 8, )
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__CMPXCHG_CASE(w, h, , 16, )
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__CMPXCHG_CASE(w, , , 32, )
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__CMPXCHG_CASE(x, , , 64, )
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__CMPXCHG_CASE(w, b, acq_, 8, a, "memory")
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__CMPXCHG_CASE(w, h, acq_, 16, a, "memory")
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__CMPXCHG_CASE(w, , acq_, 32, a, "memory")
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__CMPXCHG_CASE(x, , acq_, 64, a, "memory")
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__CMPXCHG_CASE(w, b, rel_, 8, l, "memory")
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__CMPXCHG_CASE(w, h, rel_, 16, l, "memory")
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__CMPXCHG_CASE(w, , rel_, 32, l, "memory")
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__CMPXCHG_CASE(x, , rel_, 64, l, "memory")
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__CMPXCHG_CASE(w, b, mb_, 8, al, "memory")
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__CMPXCHG_CASE(w, h, mb_, 16, al, "memory")
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__CMPXCHG_CASE(w, , mb_, 32, al, "memory")
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__CMPXCHG_CASE(x, , mb_, 64, al, "memory")
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#undef __CMPXCHG_CASE
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#define __CMPXCHG128(name, mb, cl...) \
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static __always_inline u128 \
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__lse__cmpxchg128##name(volatile u128 *ptr, u128 old, u128 new) \
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{ \
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union __u128_halves r, o = { .full = (old) }, \
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n = { .full = (new) }; \
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register unsigned long x0 asm ("x0") = o.low; \
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register unsigned long x1 asm ("x1") = o.high; \
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register unsigned long x2 asm ("x2") = n.low; \
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register unsigned long x3 asm ("x3") = n.high; \
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register unsigned long x4 asm ("x4") = (unsigned long)ptr; \
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\
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asm volatile( \
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__LSE_PREAMBLE \
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" casp" #mb "\t%[old1], %[old2], %[new1], %[new2], %[v]\n"\
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: [old1] "+&r" (x0), [old2] "+&r" (x1), \
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[v] "+Q" (*(u128 *)ptr) \
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: [new1] "r" (x2), [new2] "r" (x3), [ptr] "r" (x4), \
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[oldval1] "r" (o.low), [oldval2] "r" (o.high) \
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: cl); \
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\
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r.low = x0; r.high = x1; \
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\
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return r.full; \
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}
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__CMPXCHG128( , )
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__CMPXCHG128(_mb, al, "memory")
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#undef __CMPXCHG128
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#endif /* __ASM_ATOMIC_LSE_H */
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