366 lines
7.8 KiB
C
366 lines
7.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* FP/SIMD state saving and restoring macros
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*
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* Copyright (C) 2012 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*/
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#include <asm/assembler.h>
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.macro fpsimd_save state, tmpnr
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stp q0, q1, [\state, #16 * 0]
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stp q2, q3, [\state, #16 * 2]
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stp q4, q5, [\state, #16 * 4]
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stp q6, q7, [\state, #16 * 6]
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stp q8, q9, [\state, #16 * 8]
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stp q10, q11, [\state, #16 * 10]
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stp q12, q13, [\state, #16 * 12]
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stp q14, q15, [\state, #16 * 14]
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stp q16, q17, [\state, #16 * 16]
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stp q18, q19, [\state, #16 * 18]
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stp q20, q21, [\state, #16 * 20]
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stp q22, q23, [\state, #16 * 22]
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stp q24, q25, [\state, #16 * 24]
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stp q26, q27, [\state, #16 * 26]
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stp q28, q29, [\state, #16 * 28]
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stp q30, q31, [\state, #16 * 30]!
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mrs x\tmpnr, fpsr
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str w\tmpnr, [\state, #16 * 2]
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mrs x\tmpnr, fpcr
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str w\tmpnr, [\state, #16 * 2 + 4]
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.endm
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.macro fpsimd_restore_fpcr state, tmp
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/*
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* Writes to fpcr may be self-synchronising, so avoid restoring
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* the register if it hasn't changed.
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*/
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mrs \tmp, fpcr
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cmp \tmp, \state
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b.eq 9999f
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msr fpcr, \state
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9999:
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.endm
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/* Clobbers \state */
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.macro fpsimd_restore state, tmpnr
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ldp q0, q1, [\state, #16 * 0]
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ldp q2, q3, [\state, #16 * 2]
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ldp q4, q5, [\state, #16 * 4]
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ldp q6, q7, [\state, #16 * 6]
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ldp q8, q9, [\state, #16 * 8]
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ldp q10, q11, [\state, #16 * 10]
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ldp q12, q13, [\state, #16 * 12]
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ldp q14, q15, [\state, #16 * 14]
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ldp q16, q17, [\state, #16 * 16]
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ldp q18, q19, [\state, #16 * 18]
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ldp q20, q21, [\state, #16 * 20]
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ldp q22, q23, [\state, #16 * 22]
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ldp q24, q25, [\state, #16 * 24]
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ldp q26, q27, [\state, #16 * 26]
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ldp q28, q29, [\state, #16 * 28]
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ldp q30, q31, [\state, #16 * 30]!
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ldr w\tmpnr, [\state, #16 * 2]
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msr fpsr, x\tmpnr
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ldr w\tmpnr, [\state, #16 * 2 + 4]
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fpsimd_restore_fpcr x\tmpnr, \state
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.endm
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/* Sanity-check macros to help avoid encoding garbage instructions */
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.macro _check_general_reg nr
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.if (\nr) < 0 || (\nr) > 30
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.error "Bad register number \nr."
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.endif
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.endm
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.macro _sve_check_zreg znr
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.if (\znr) < 0 || (\znr) > 31
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.error "Bad Scalable Vector Extension vector register number \znr."
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.endif
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.endm
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.macro _sve_check_preg pnr
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.if (\pnr) < 0 || (\pnr) > 15
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.error "Bad Scalable Vector Extension predicate register number \pnr."
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.endif
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.endm
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.macro _check_num n, min, max
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.if (\n) < (\min) || (\n) > (\max)
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.error "Number \n out of range [\min,\max]"
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.endif
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.endm
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.macro _sme_check_wv v
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.if (\v) < 12 || (\v) > 15
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.error "Bad vector select register \v."
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.endif
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.endm
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/* SVE instruction encodings for non-SVE-capable assemblers */
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/* (pre binutils 2.28, all kernel capable clang versions support SVE) */
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/* STR (vector): STR Z\nz, [X\nxbase, #\offset, MUL VL] */
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.macro _sve_str_v nz, nxbase, offset=0
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_sve_check_zreg \nz
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_check_general_reg \nxbase
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_check_num (\offset), -0x100, 0xff
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.inst 0xe5804000 \
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| (\nz) \
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| ((\nxbase) << 5) \
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| (((\offset) & 7) << 10) \
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| (((\offset) & 0x1f8) << 13)
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.endm
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/* LDR (vector): LDR Z\nz, [X\nxbase, #\offset, MUL VL] */
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.macro _sve_ldr_v nz, nxbase, offset=0
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_sve_check_zreg \nz
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_check_general_reg \nxbase
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_check_num (\offset), -0x100, 0xff
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.inst 0x85804000 \
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| (\nz) \
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| ((\nxbase) << 5) \
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| (((\offset) & 7) << 10) \
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| (((\offset) & 0x1f8) << 13)
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.endm
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/* STR (predicate): STR P\np, [X\nxbase, #\offset, MUL VL] */
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.macro _sve_str_p np, nxbase, offset=0
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_sve_check_preg \np
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_check_general_reg \nxbase
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_check_num (\offset), -0x100, 0xff
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.inst 0xe5800000 \
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| (\np) \
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| ((\nxbase) << 5) \
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| (((\offset) & 7) << 10) \
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| (((\offset) & 0x1f8) << 13)
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.endm
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/* LDR (predicate): LDR P\np, [X\nxbase, #\offset, MUL VL] */
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.macro _sve_ldr_p np, nxbase, offset=0
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_sve_check_preg \np
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_check_general_reg \nxbase
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_check_num (\offset), -0x100, 0xff
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.inst 0x85800000 \
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| (\np) \
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| ((\nxbase) << 5) \
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| (((\offset) & 7) << 10) \
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| (((\offset) & 0x1f8) << 13)
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.endm
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/* RDVL X\nx, #\imm */
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.macro _sve_rdvl nx, imm
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_check_general_reg \nx
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_check_num (\imm), -0x20, 0x1f
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.inst 0x04bf5000 \
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| (\nx) \
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| (((\imm) & 0x3f) << 5)
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.endm
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/* RDFFR (unpredicated): RDFFR P\np.B */
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.macro _sve_rdffr np
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_sve_check_preg \np
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.inst 0x2519f000 \
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| (\np)
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.endm
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/* WRFFR P\np.B */
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.macro _sve_wrffr np
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_sve_check_preg \np
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.inst 0x25289000 \
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| ((\np) << 5)
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.endm
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/* PFALSE P\np.B */
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.macro _sve_pfalse np
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_sve_check_preg \np
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.inst 0x2518e400 \
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| (\np)
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.endm
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/* SME instruction encodings for non-SME-capable assemblers */
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/* (pre binutils 2.38/LLVM 13) */
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/* RDSVL X\nx, #\imm */
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.macro _sme_rdsvl nx, imm
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_check_general_reg \nx
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_check_num (\imm), -0x20, 0x1f
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.inst 0x04bf5800 \
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| (\nx) \
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| (((\imm) & 0x3f) << 5)
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.endm
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/*
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* STR (vector from ZA array):
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* STR ZA[\nw, #\offset], [X\nxbase, #\offset, MUL VL]
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*/
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.macro _sme_str_zav nw, nxbase, offset=0
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_sme_check_wv \nw
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_check_general_reg \nxbase
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_check_num (\offset), -0x100, 0xff
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.inst 0xe1200000 \
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| (((\nw) & 3) << 13) \
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| ((\nxbase) << 5) \
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| ((\offset) & 7)
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.endm
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/*
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* LDR (vector to ZA array):
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* LDR ZA[\nw, #\offset], [X\nxbase, #\offset, MUL VL]
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*/
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.macro _sme_ldr_zav nw, nxbase, offset=0
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_sme_check_wv \nw
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_check_general_reg \nxbase
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_check_num (\offset), -0x100, 0xff
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.inst 0xe1000000 \
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| (((\nw) & 3) << 13) \
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| ((\nxbase) << 5) \
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| ((\offset) & 7)
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.endm
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/*
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* LDR (ZT0)
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*
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* LDR ZT0, nx
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*/
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.macro _ldr_zt nx
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_check_general_reg \nx
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.inst 0xe11f8000 \
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| (\nx << 5)
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.endm
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/*
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* STR (ZT0)
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*
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* STR ZT0, nx
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*/
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.macro _str_zt nx
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_check_general_reg \nx
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.inst 0xe13f8000 \
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| (\nx << 5)
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.endm
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/*
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* Zero the entire ZA array
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* ZERO ZA
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*/
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.macro zero_za
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.inst 0xc00800ff
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.endm
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.macro __for from:req, to:req
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.if (\from) == (\to)
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_for__body %\from
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.else
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__for %\from, %((\from) + ((\to) - (\from)) / 2)
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__for %((\from) + ((\to) - (\from)) / 2 + 1), %\to
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.endif
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.endm
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.macro _for var:req, from:req, to:req, insn:vararg
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.macro _for__body \var:req
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.noaltmacro
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\insn
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.altmacro
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.endm
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.altmacro
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__for \from, \to
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.noaltmacro
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.purgem _for__body
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.endm
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/* Update ZCR_EL1.LEN with the new VQ */
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.macro sve_load_vq xvqminus1, xtmp, xtmp2
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mrs_s \xtmp, SYS_ZCR_EL1
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bic \xtmp2, \xtmp, ZCR_ELx_LEN_MASK
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orr \xtmp2, \xtmp2, \xvqminus1
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cmp \xtmp2, \xtmp
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b.eq 921f
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msr_s SYS_ZCR_EL1, \xtmp2 //self-synchronising
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921:
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.endm
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/* Update SMCR_EL1.LEN with the new VQ */
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.macro sme_load_vq xvqminus1, xtmp, xtmp2
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mrs_s \xtmp, SYS_SMCR_EL1
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bic \xtmp2, \xtmp, SMCR_ELx_LEN_MASK
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orr \xtmp2, \xtmp2, \xvqminus1
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cmp \xtmp2, \xtmp
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b.eq 921f
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msr_s SYS_SMCR_EL1, \xtmp2 //self-synchronising
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921:
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.endm
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/* Preserve the first 128-bits of Znz and zero the rest. */
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.macro _sve_flush_z nz
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_sve_check_zreg \nz
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mov v\nz\().16b, v\nz\().16b
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.endm
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.macro sve_flush_z
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_for n, 0, 31, _sve_flush_z \n
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.endm
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.macro sve_flush_p
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_for n, 0, 15, _sve_pfalse \n
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.endm
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.macro sve_flush_ffr
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_sve_wrffr 0
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.endm
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.macro sve_save nxbase, xpfpsr, save_ffr, nxtmp
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_for n, 0, 31, _sve_str_v \n, \nxbase, \n - 34
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_for n, 0, 15, _sve_str_p \n, \nxbase, \n - 16
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cbz \save_ffr, 921f
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_sve_rdffr 0
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b 922f
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921:
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_sve_pfalse 0 // Zero out FFR
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922:
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_sve_str_p 0, \nxbase
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_sve_ldr_p 0, \nxbase, -16
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mrs x\nxtmp, fpsr
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str w\nxtmp, [\xpfpsr]
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mrs x\nxtmp, fpcr
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str w\nxtmp, [\xpfpsr, #4]
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.endm
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.macro sve_load nxbase, xpfpsr, restore_ffr, nxtmp
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_for n, 0, 31, _sve_ldr_v \n, \nxbase, \n - 34
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cbz \restore_ffr, 921f
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_sve_ldr_p 0, \nxbase
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_sve_wrffr 0
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921:
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_for n, 0, 15, _sve_ldr_p \n, \nxbase, \n - 16
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ldr w\nxtmp, [\xpfpsr]
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msr fpsr, x\nxtmp
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ldr w\nxtmp, [\xpfpsr, #4]
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msr fpcr, x\nxtmp
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.endm
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.macro sme_save_za nxbase, xvl, nw
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mov w\nw, #0
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423:
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_sme_str_zav \nw, \nxbase
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add x\nxbase, x\nxbase, \xvl
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add x\nw, x\nw, #1
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cmp \xvl, x\nw
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bne 423b
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.endm
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.macro sme_load_za nxbase, xvl, nw
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mov w\nw, #0
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423:
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_sme_ldr_zav \nw, \nxbase
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add x\nxbase, x\nxbase, \xvl
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add x\nw, x\nw, #1
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cmp \xvl, x\nw
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bne 423b
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.endm
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