198 lines
5.0 KiB
ArmAsm
198 lines
5.0 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Cache maintenance
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 ARM Ltd.
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*/
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#include <linux/errno.h>
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/cpufeature.h>
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#include <asm/alternative.h>
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#include <asm/asm-uaccess.h>
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/*
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* caches_clean_inval_pou_macro(start,end) [fixup]
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*
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* Ensure that the I and D caches are coherent within specified region.
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* This is typically used when code has been written to a memory region,
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* and will be executed.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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* - fixup - optional label to branch to on user fault
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*/
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.macro caches_clean_inval_pou_macro, fixup
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alternative_if ARM64_HAS_CACHE_IDC
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dsb ishst
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b .Ldc_skip_\@
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alternative_else_nop_endif
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mov x2, x0
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mov x3, x1
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dcache_by_line_op cvau, ish, x2, x3, x4, x5, \fixup
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.Ldc_skip_\@:
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alternative_if ARM64_HAS_CACHE_DIC
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isb
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b .Lic_skip_\@
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alternative_else_nop_endif
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invalidate_icache_by_line x0, x1, x2, x3, \fixup
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.Lic_skip_\@:
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.endm
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/*
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* caches_clean_inval_pou(start,end)
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*
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* Ensure that the I and D caches are coherent within specified region.
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* This is typically used when code has been written to a memory region,
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* and will be executed.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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SYM_FUNC_START(caches_clean_inval_pou)
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caches_clean_inval_pou_macro
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ret
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SYM_FUNC_END(caches_clean_inval_pou)
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SYM_FUNC_ALIAS(__pi_caches_clean_inval_pou, caches_clean_inval_pou)
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/*
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* caches_clean_inval_user_pou(start,end)
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*
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* Ensure that the I and D caches are coherent within specified region.
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* This is typically used when code has been written to a memory region,
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* and will be executed.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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SYM_FUNC_START(caches_clean_inval_user_pou)
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uaccess_ttbr0_enable x2, x3, x4
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caches_clean_inval_pou_macro 2f
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mov x0, xzr
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1:
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uaccess_ttbr0_disable x1, x2
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ret
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2:
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mov x0, #-EFAULT
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b 1b
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SYM_FUNC_END(caches_clean_inval_user_pou)
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/*
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* icache_inval_pou(start,end)
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*
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* Ensure that the I cache is invalid within specified region.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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SYM_FUNC_START(icache_inval_pou)
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alternative_if ARM64_HAS_CACHE_DIC
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isb
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ret
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alternative_else_nop_endif
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invalidate_icache_by_line x0, x1, x2, x3
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ret
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SYM_FUNC_END(icache_inval_pou)
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/*
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* dcache_clean_inval_poc(start, end)
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*
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* Ensure that any D-cache lines for the interval [start, end)
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* are cleaned and invalidated to the PoC.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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SYM_FUNC_START(__pi_dcache_clean_inval_poc)
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dcache_by_line_op civac, sy, x0, x1, x2, x3
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ret
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SYM_FUNC_END(__pi_dcache_clean_inval_poc)
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SYM_FUNC_ALIAS(dcache_clean_inval_poc, __pi_dcache_clean_inval_poc)
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/*
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* dcache_clean_pou(start, end)
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*
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* Ensure that any D-cache lines for the interval [start, end)
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* are cleaned to the PoU.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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SYM_FUNC_START(dcache_clean_pou)
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alternative_if ARM64_HAS_CACHE_IDC
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dsb ishst
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ret
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alternative_else_nop_endif
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dcache_by_line_op cvau, ish, x0, x1, x2, x3
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ret
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SYM_FUNC_END(dcache_clean_pou)
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/*
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* dcache_inval_poc(start, end)
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*
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* Ensure that any D-cache lines for the interval [start, end)
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* are invalidated. Any partial lines at the ends of the interval are
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* also cleaned to PoC to prevent data loss.
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*
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* - start - kernel start address of region
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* - end - kernel end address of region
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*/
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SYM_FUNC_START(__pi_dcache_inval_poc)
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dcache_line_size x2, x3
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sub x3, x2, #1
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tst x1, x3 // end cache line aligned?
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bic x1, x1, x3
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b.eq 1f
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dc civac, x1 // clean & invalidate D / U line
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1: tst x0, x3 // start cache line aligned?
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bic x0, x0, x3
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b.eq 2f
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dc civac, x0 // clean & invalidate D / U line
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b 3f
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2: dc ivac, x0 // invalidate D / U line
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3: add x0, x0, x2
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cmp x0, x1
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b.lo 2b
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dsb sy
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ret
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SYM_FUNC_END(__pi_dcache_inval_poc)
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SYM_FUNC_ALIAS(dcache_inval_poc, __pi_dcache_inval_poc)
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/*
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* dcache_clean_poc(start, end)
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*
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* Ensure that any D-cache lines for the interval [start, end)
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* are cleaned to the PoC.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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SYM_FUNC_START(__pi_dcache_clean_poc)
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dcache_by_line_op cvac, sy, x0, x1, x2, x3
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ret
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SYM_FUNC_END(__pi_dcache_clean_poc)
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SYM_FUNC_ALIAS(dcache_clean_poc, __pi_dcache_clean_poc)
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/*
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* dcache_clean_pop(start, end)
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*
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* Ensure that any D-cache lines for the interval [start, end)
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* are cleaned to the PoP.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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SYM_FUNC_START(__pi_dcache_clean_pop)
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alternative_if_not ARM64_HAS_DCPOP
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b dcache_clean_poc
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alternative_else_nop_endif
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dcache_by_line_op cvap, sy, x0, x1, x2, x3
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ret
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SYM_FUNC_END(__pi_dcache_clean_pop)
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SYM_FUNC_ALIAS(dcache_clean_pop, __pi_dcache_clean_pop)
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