132 lines
5.0 KiB
C
132 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* cpu.h: Values of the PRID register used to match up
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* various LoongArch CPU types.
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*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_CPU_H
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#define _ASM_CPU_H
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/*
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* As described in LoongArch specs from Loongson Technology, the PRID register
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* (CPUCFG.00) has the following layout:
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*
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* +---------------+----------------+------------+--------------------+
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* | Reserved | Company ID | Series ID | Product ID |
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* +---------------+----------------+------------+--------------------+
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* 31 24 23 16 15 12 11 0
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*/
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/*
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* Assigned Company values for bits 23:16 of the PRID register.
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*/
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#define PRID_COMP_MASK 0xff0000
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#define PRID_COMP_LOONGSON 0x140000
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/*
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* Assigned Series ID values for bits 15:12 of the PRID register. In order
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* to detect a certain CPU type exactly eventually additional registers may
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* need to be examined.
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*/
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#define PRID_SERIES_MASK 0xf000
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#define PRID_SERIES_LA132 0x8000 /* Loongson 32bit */
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#define PRID_SERIES_LA264 0xa000 /* Loongson 64bit, 2-issue */
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#define PRID_SERIES_LA364 0xb000 /* Loongson 64bit, 3-issue */
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#define PRID_SERIES_LA464 0xc000 /* Loongson 64bit, 4-issue */
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#define PRID_SERIES_LA664 0xd000 /* Loongson 64bit, 6-issue */
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/*
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* Particular Product ID values for bits 11:0 of the PRID register.
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*/
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#define PRID_PRODUCT_MASK 0x0fff
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#if !defined(__ASSEMBLY__)
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enum cpu_type_enum {
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CPU_UNKNOWN,
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CPU_LOONGSON32,
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CPU_LOONGSON64,
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CPU_LAST
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};
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#endif /* !__ASSEMBLY */
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/*
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* ISA Level encodings
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*
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*/
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#define LOONGARCH_CPU_ISA_LA32R 0x00000001
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#define LOONGARCH_CPU_ISA_LA32S 0x00000002
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#define LOONGARCH_CPU_ISA_LA64 0x00000004
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#define LOONGARCH_CPU_ISA_32BIT (LOONGARCH_CPU_ISA_LA32R | LOONGARCH_CPU_ISA_LA32S)
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#define LOONGARCH_CPU_ISA_64BIT LOONGARCH_CPU_ISA_LA64
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/*
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* CPU Option encodings
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*/
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#define CPU_FEATURE_CPUCFG 0 /* CPU has CPUCFG */
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#define CPU_FEATURE_LAM 1 /* CPU has Atomic instructions */
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#define CPU_FEATURE_UAL 2 /* CPU supports unaligned access */
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#define CPU_FEATURE_FPU 3 /* CPU has FPU */
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#define CPU_FEATURE_LSX 4 /* CPU has LSX (128-bit SIMD) */
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#define CPU_FEATURE_LASX 5 /* CPU has LASX (256-bit SIMD) */
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#define CPU_FEATURE_CRC32 6 /* CPU has CRC32 instructions */
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#define CPU_FEATURE_COMPLEX 7 /* CPU has Complex instructions */
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#define CPU_FEATURE_CRYPTO 8 /* CPU has Crypto instructions */
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#define CPU_FEATURE_LVZ 9 /* CPU has Virtualization extension */
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#define CPU_FEATURE_LBT_X86 10 /* CPU has X86 Binary Translation */
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#define CPU_FEATURE_LBT_ARM 11 /* CPU has ARM Binary Translation */
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#define CPU_FEATURE_LBT_MIPS 12 /* CPU has MIPS Binary Translation */
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#define CPU_FEATURE_TLB 13 /* CPU has TLB */
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#define CPU_FEATURE_CSR 14 /* CPU has CSR */
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#define CPU_FEATURE_WATCH 15 /* CPU has watchpoint registers */
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#define CPU_FEATURE_VINT 16 /* CPU has vectored interrupts */
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#define CPU_FEATURE_CSRIPI 17 /* CPU has CSR-IPI */
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#define CPU_FEATURE_EXTIOI 18 /* CPU has EXT-IOI */
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#define CPU_FEATURE_PREFETCH 19 /* CPU has prefetch instructions */
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#define CPU_FEATURE_PMP 20 /* CPU has perfermance counter */
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#define CPU_FEATURE_SCALEFREQ 21 /* CPU supports cpufreq scaling */
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#define CPU_FEATURE_FLATMODE 22 /* CPU has flat mode */
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#define CPU_FEATURE_EIODECODE 23 /* CPU has EXTIOI interrupt pin decode mode */
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#define CPU_FEATURE_GUESTID 24 /* CPU has GuestID feature */
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#define CPU_FEATURE_HYPERVISOR 25 /* CPU has hypervisor (running in VM) */
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#define CPU_FEATURE_PTW 26 /* CPU has hardware page table walker */
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#define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG)
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#define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM)
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#define LOONGARCH_CPU_UAL BIT_ULL(CPU_FEATURE_UAL)
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#define LOONGARCH_CPU_FPU BIT_ULL(CPU_FEATURE_FPU)
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#define LOONGARCH_CPU_LSX BIT_ULL(CPU_FEATURE_LSX)
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#define LOONGARCH_CPU_LASX BIT_ULL(CPU_FEATURE_LASX)
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#define LOONGARCH_CPU_CRC32 BIT_ULL(CPU_FEATURE_CRC32)
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#define LOONGARCH_CPU_COMPLEX BIT_ULL(CPU_FEATURE_COMPLEX)
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#define LOONGARCH_CPU_CRYPTO BIT_ULL(CPU_FEATURE_CRYPTO)
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#define LOONGARCH_CPU_LVZ BIT_ULL(CPU_FEATURE_LVZ)
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#define LOONGARCH_CPU_LBT_X86 BIT_ULL(CPU_FEATURE_LBT_X86)
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#define LOONGARCH_CPU_LBT_ARM BIT_ULL(CPU_FEATURE_LBT_ARM)
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#define LOONGARCH_CPU_LBT_MIPS BIT_ULL(CPU_FEATURE_LBT_MIPS)
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#define LOONGARCH_CPU_TLB BIT_ULL(CPU_FEATURE_TLB)
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#define LOONGARCH_CPU_CSR BIT_ULL(CPU_FEATURE_CSR)
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#define LOONGARCH_CPU_WATCH BIT_ULL(CPU_FEATURE_WATCH)
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#define LOONGARCH_CPU_VINT BIT_ULL(CPU_FEATURE_VINT)
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#define LOONGARCH_CPU_CSRIPI BIT_ULL(CPU_FEATURE_CSRIPI)
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#define LOONGARCH_CPU_EXTIOI BIT_ULL(CPU_FEATURE_EXTIOI)
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#define LOONGARCH_CPU_PREFETCH BIT_ULL(CPU_FEATURE_PREFETCH)
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#define LOONGARCH_CPU_PMP BIT_ULL(CPU_FEATURE_PMP)
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#define LOONGARCH_CPU_SCALEFREQ BIT_ULL(CPU_FEATURE_SCALEFREQ)
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#define LOONGARCH_CPU_FLATMODE BIT_ULL(CPU_FEATURE_FLATMODE)
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#define LOONGARCH_CPU_EIODECODE BIT_ULL(CPU_FEATURE_EIODECODE)
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#define LOONGARCH_CPU_GUESTID BIT_ULL(CPU_FEATURE_GUESTID)
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#define LOONGARCH_CPU_HYPERVISOR BIT_ULL(CPU_FEATURE_HYPERVISOR)
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#define LOONGARCH_CPU_PTW BIT_ULL(CPU_FEATURE_PTW)
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#endif /* _ASM_CPU_H */
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