222 lines
5.2 KiB
C
222 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ARCH_M68K_ATOMIC__
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#define __ARCH_M68K_ATOMIC__
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#include <linux/types.h>
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#include <linux/irqflags.h>
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#include <asm/cmpxchg.h>
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#include <asm/barrier.h>
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/*
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* Atomic operations that C can't guarantee us. Useful for
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* resource counting etc..
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*/
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/*
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* We do not have SMP m68k systems, so we don't have to deal with that.
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*/
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#define arch_atomic_read(v) READ_ONCE((v)->counter)
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#define arch_atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
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/*
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* The ColdFire parts cannot do some immediate to memory operations,
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* so for them we do not specify the "i" asm constraint.
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*/
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#ifdef CONFIG_COLDFIRE
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#define ASM_DI "d"
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#else
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#define ASM_DI "di"
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#endif
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#define ATOMIC_OP(op, c_op, asm_op) \
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static inline void arch_atomic_##op(int i, atomic_t *v) \
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{ \
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__asm__ __volatile__(#asm_op "l %1,%0" : "+m" (*v) : ASM_DI (i));\
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} \
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#ifdef CONFIG_RMW_INSNS
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#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
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static inline int arch_atomic_##op##_return(int i, atomic_t *v) \
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{ \
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int t, tmp; \
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\
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__asm__ __volatile__( \
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"1: movel %2,%1\n" \
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" " #asm_op "l %3,%1\n" \
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" casl %2,%1,%0\n" \
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" jne 1b" \
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: "+m" (*v), "=&d" (t), "=&d" (tmp) \
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: "di" (i), "2" (arch_atomic_read(v))); \
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return t; \
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}
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#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
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static inline int arch_atomic_fetch_##op(int i, atomic_t *v) \
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{ \
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int t, tmp; \
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\
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__asm__ __volatile__( \
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"1: movel %2,%1\n" \
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" " #asm_op "l %3,%1\n" \
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" casl %2,%1,%0\n" \
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" jne 1b" \
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: "+m" (*v), "=&d" (t), "=&d" (tmp) \
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: "di" (i), "2" (arch_atomic_read(v))); \
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return tmp; \
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}
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#else
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#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
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static inline int arch_atomic_##op##_return(int i, atomic_t * v) \
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{ \
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unsigned long flags; \
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int t; \
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\
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local_irq_save(flags); \
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t = (v->counter c_op i); \
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local_irq_restore(flags); \
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\
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return t; \
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}
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#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
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static inline int arch_atomic_fetch_##op(int i, atomic_t * v) \
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{ \
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unsigned long flags; \
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int t; \
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\
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local_irq_save(flags); \
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t = v->counter; \
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v->counter c_op i; \
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local_irq_restore(flags); \
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\
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return t; \
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}
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#endif /* CONFIG_RMW_INSNS */
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_OP_RETURN(op, c_op, asm_op) \
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ATOMIC_FETCH_OP(op, c_op, asm_op)
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ATOMIC_OPS(add, +=, add)
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ATOMIC_OPS(sub, -=, sub)
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#define arch_atomic_add_return arch_atomic_add_return
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#define arch_atomic_sub_return arch_atomic_sub_return
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#define arch_atomic_fetch_add arch_atomic_fetch_add
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#define arch_atomic_fetch_sub arch_atomic_fetch_sub
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_FETCH_OP(op, c_op, asm_op)
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ATOMIC_OPS(and, &=, and)
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ATOMIC_OPS(or, |=, or)
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ATOMIC_OPS(xor, ^=, eor)
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#define arch_atomic_fetch_and arch_atomic_fetch_and
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#define arch_atomic_fetch_or arch_atomic_fetch_or
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#define arch_atomic_fetch_xor arch_atomic_fetch_xor
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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static inline void arch_atomic_inc(atomic_t *v)
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{
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__asm__ __volatile__("addql #1,%0" : "+m" (*v));
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}
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#define arch_atomic_inc arch_atomic_inc
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static inline void arch_atomic_dec(atomic_t *v)
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{
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__asm__ __volatile__("subql #1,%0" : "+m" (*v));
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}
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#define arch_atomic_dec arch_atomic_dec
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static inline int arch_atomic_dec_and_test(atomic_t *v)
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{
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char c;
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__asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
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return c != 0;
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}
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#define arch_atomic_dec_and_test arch_atomic_dec_and_test
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static inline int arch_atomic_dec_and_test_lt(atomic_t *v)
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{
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char c;
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__asm__ __volatile__(
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"subql #1,%1; slt %0"
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: "=d" (c), "=m" (*v)
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: "m" (*v));
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return c != 0;
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}
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static inline int arch_atomic_inc_and_test(atomic_t *v)
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{
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char c;
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__asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
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return c != 0;
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}
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#define arch_atomic_inc_and_test arch_atomic_inc_and_test
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#ifndef CONFIG_RMW_INSNS
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static inline int arch_atomic_cmpxchg(atomic_t *v, int old, int new)
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{
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unsigned long flags;
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int prev;
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local_irq_save(flags);
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prev = arch_atomic_read(v);
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if (prev == old)
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arch_atomic_set(v, new);
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local_irq_restore(flags);
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return prev;
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}
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#define arch_atomic_cmpxchg arch_atomic_cmpxchg
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static inline int arch_atomic_xchg(atomic_t *v, int new)
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{
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unsigned long flags;
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int prev;
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local_irq_save(flags);
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prev = arch_atomic_read(v);
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arch_atomic_set(v, new);
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local_irq_restore(flags);
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return prev;
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}
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#define arch_atomic_xchg arch_atomic_xchg
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#endif /* !CONFIG_RMW_INSNS */
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static inline int arch_atomic_sub_and_test(int i, atomic_t *v)
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{
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char c;
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__asm__ __volatile__("subl %2,%1; seq %0"
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: "=d" (c), "+m" (*v)
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: ASM_DI (i));
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return c != 0;
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}
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#define arch_atomic_sub_and_test arch_atomic_sub_and_test
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static inline int arch_atomic_add_negative(int i, atomic_t *v)
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{
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char c;
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__asm__ __volatile__("addl %2,%1; smi %0"
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: "=d" (c), "+m" (*v)
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: ASM_DI (i));
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return c != 0;
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}
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#define arch_atomic_add_negative arch_atomic_add_negative
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#endif /* __ARCH_M68K_ATOMIC __ */
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