506 lines
11 KiB
Plaintext
506 lines
11 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2009 Extreme Engineering Solutions, Inc.
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* Based on TQM8548 device tree
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*
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* XPedite5200 PrPMC/XMC module based on MPC8548E. This dts is for the
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* xMon boot loader memory map which differs from U-Boot's.
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*/
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/dts-v1/;
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/ {
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model = "xes,xpedite5200";
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compatible = "xes,xpedite5200", "xes,MPC8548";
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#address-cells = <1>;
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#size-cells = <1>;
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form-factor = "PMC/XMC";
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boot-bank = <0x0>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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ethernet3 = &enet3;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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pci1 = &pci1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8548@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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next-level-cache = <&L2>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x0>; // Filled in by boot loader
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};
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soc@ef000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <0x0 0xef000000 0x100000>;
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bus-frequency = <0>;
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compatible = "fsl,mpc8548-immr", "simple-bus";
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ecm-law@0 {
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compatible = "fsl,ecm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <12>;
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};
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ecm@1000 {
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compatible = "fsl,mpc8548-ecm", "fsl,ecm";
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reg = <0x1000 0x1000>;
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interrupts = <17 2>;
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interrupt-parent = <&mpic>;
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};
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memory-controller@2000 {
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compatible = "fsl,mpc8548-memory-controller";
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reg = <0x2000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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};
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L2: l2-cache-controller@20000 {
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compatible = "fsl,mpc8548-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <32>; // 32 bytes
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cache-size = <0x80000>; // L2, 512K
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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};
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/* On-card I2C */
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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/*
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* Board GPIO:
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* 0: BRD_CFG0 (1: P14 IO present)
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* 1: BRD_CFG1 (1: FP ethernet present)
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* 2: BRD_CFG2 (1: XMC IO present)
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* 3: XMC root complex indicator
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* 4: Flash boot device indicator
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* 5: Flash write protect enable
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* 6: PMC monarch indicator
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* 7: PMC EREADY
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*/
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gpio1: gpio@18 {
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compatible = "nxp,pca9556";
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reg = <0x18>;
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#gpio-cells = <2>;
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gpio-controller;
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polarity = <0x00>;
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};
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/* P14 GPIO */
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gpio2: gpio@19 {
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compatible = "nxp,pca9556";
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reg = <0x19>;
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#gpio-cells = <2>;
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gpio-controller;
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polarity = <0x00>;
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};
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eeprom@50 {
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compatible = "atmel,at24c16";
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reg = <0x50>;
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};
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rtc@68 {
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compatible = "st,m41t00",
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"dallas,ds1338";
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reg = <0x68>;
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};
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dtt@34 {
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compatible = "maxim,max1237";
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reg = <0x34>;
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};
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};
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/* Off-card I2C */
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
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reg = <0x21300 0x4>;
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ranges = <0x0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8548-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8548-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8548-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8548-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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/* eTSEC1: Front panel port 0 */
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enet0: ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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ranges = <0x0 0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <29 2 30 2 34 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi0>;
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phy-handle = <&phy0>;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x520 0x20>;
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phy0: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <8 1>;
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reg = <0x1>;
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};
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phy1: ethernet-phy@2 {
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interrupt-parent = <&mpic>;
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interrupts = <8 1>;
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reg = <0x2>;
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};
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phy2: ethernet-phy@3 {
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interrupt-parent = <&mpic>;
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interrupts = <8 1>;
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reg = <0x3>;
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};
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phy3: ethernet-phy@4 {
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interrupt-parent = <&mpic>;
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interrupts = <8 1>;
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reg = <0x4>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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/* eTSEC2: Front panel port 1 */
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enet1: ethernet@25000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <1>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x25000 0x1000>;
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ranges = <0x0 0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <35 2 36 2 40 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi1>;
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phy-handle = <&phy1>;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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/* eTSEC3: Rear panel port 2 */
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enet2: ethernet@26000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <2>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x26000 0x1000>;
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ranges = <0x0 0x26000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <31 2 32 2 33 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi2>;
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phy-handle = <&phy2>;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi2: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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/* eTSEC4: Rear panel port 3 */
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enet3: ethernet@27000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <3>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x27000 0x1000>;
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ranges = <0x0 0x27000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <37 2 38 2 39 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi3>;
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phy-handle = <&phy3>;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi3: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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current-speed = <9600>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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current-speed = <9600>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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global-utilities@e0000 { // global utilities reg
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compatible = "fsl,mpc8548-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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};
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};
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localbus@ef005000 {
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compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
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"simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <0xef005000 0x100>; // BRx, ORx, etc.
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interrupt-parent = <&mpic>;
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interrupts = <19 2>;
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ranges = <
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0 0x0 0xf8000000 0x08000000 // NOR boot flash
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1 0x0 0xf0000000 0x08000000 // NOR expansion flash
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2 0x0 0xe8000000 0x00010000 // NAND CE1
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3 0x0 0xe8010000 0x00010000 // NAND CE2
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>;
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nor-boot@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0 0x0 0x4000000>;
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bank-width = <2>;
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partition@0 {
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label = "Primary OS";
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reg = <0x00000000 0x180000>;
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};
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partition@180000 {
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label = "Secondary OS";
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reg = <0x00180000 0x180000>;
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};
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partition@300000 {
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label = "User";
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reg = <0x00300000 0x3c80000>;
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};
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partition@3f80000 {
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label = "Boot firmware";
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reg = <0x03f80000 0x80000>;
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};
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};
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nor-alternate@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <1 0x0 0x4000000>;
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bank-width = <2>;
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partition@0 {
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label = "Filesystem";
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reg = <0x00000000 0x3f80000>;
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};
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partition@3f80000 {
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label = "Alternate boot firmware";
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reg = <0x03f80000 0x80000>;
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};
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};
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nand@2,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xes,address-ctl-nand";
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reg = <2 0x0 0x10000>;
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cle-line = <0x8>; /* CLE tied to A3 */
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ale-line = <0x10>; /* ALE tied to A4 */
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partition@0 {
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label = "NAND Filesystem";
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reg = <0 0x40000000>;
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};
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};
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};
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/* PMC interface */
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pci0: pci@ef008000 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
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device_type = "pci";
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reg = <0xef008000 0x1000>;
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clock-frequency = <33333333>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL */
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0xe000 0 0 1 &mpic 2 1
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0xe000 0 0 2 &mpic 3 1>;
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interrupt-parent = <&mpic>;
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interrupts = <24 2>;
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bus-range = <0 0>;
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ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
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0x01000000 0 0x00000000 0xd0000000 0 0x01000000>;
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};
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/* XMC PCIe */
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pci1: pcie@ef00a000 {
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0x00000 0 0 1 &mpic 0 1
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0x00000 0 0 2 &mpic 1 1
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0x00000 0 0 3 &mpic 2 1
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0x00000 0 0 4 &mpic 3 1>;
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interrupt-parent = <&mpic>;
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interrupts = <26 2>;
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bus-range = <0 0xff>;
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ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
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0x01000000 0 0x00000000 0xd1000000 0 0x01000000>;
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clock-frequency = <33333333>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xef00a000 0x1000>;
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compatible = "fsl,mpc8548-pcie";
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device_type = "pci";
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <0x02000000 0 0xc0000000 0x02000000 0
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0xc0000000 0 0x20000000
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0x01000000 0 0x00000000 0x01000000 0
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0x00000000 0 0x08000000>;
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};
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};
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/* Needed for dtbImage boot wrapper compatibility */
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chosen {
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stdout-path = &serial0;
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};
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};
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