175 lines
5.4 KiB
C
175 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2021 Western Digital Corporation or its affiliates.
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* Copyright (C) 2022 Ventana Micro Systems Inc.
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*
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* Authors:
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* Anup Patel <apatel@ventanamicro.com>
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*/
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#ifndef __KVM_RISCV_AIA_H
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#define __KVM_RISCV_AIA_H
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#include <linux/jump_label.h>
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#include <linux/kvm_types.h>
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#include <asm/csr.h>
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struct kvm_aia {
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/* In-kernel irqchip created */
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bool in_kernel;
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/* In-kernel irqchip initialized */
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bool initialized;
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/* Virtualization mode (Emulation, HW Accelerated, or Auto) */
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u32 mode;
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/* Number of MSIs */
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u32 nr_ids;
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/* Number of wired IRQs */
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u32 nr_sources;
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/* Number of group bits in IMSIC address */
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u32 nr_group_bits;
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/* Position of group bits in IMSIC address */
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u32 nr_group_shift;
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/* Number of hart bits in IMSIC address */
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u32 nr_hart_bits;
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/* Number of guest bits in IMSIC address */
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u32 nr_guest_bits;
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/* Guest physical address of APLIC */
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gpa_t aplic_addr;
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/* Internal state of APLIC */
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void *aplic_state;
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};
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struct kvm_vcpu_aia_csr {
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unsigned long vsiselect;
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unsigned long hviprio1;
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unsigned long hviprio2;
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unsigned long vsieh;
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unsigned long hviph;
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unsigned long hviprio1h;
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unsigned long hviprio2h;
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};
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struct kvm_vcpu_aia {
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/* CPU AIA CSR context of Guest VCPU */
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struct kvm_vcpu_aia_csr guest_csr;
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/* CPU AIA CSR context upon Guest VCPU reset */
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struct kvm_vcpu_aia_csr guest_reset_csr;
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/* Guest physical address of IMSIC for this VCPU */
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gpa_t imsic_addr;
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/* HART index of IMSIC extacted from guest physical address */
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u32 hart_index;
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/* Internal state of IMSIC for this VCPU */
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void *imsic_state;
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};
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#define KVM_RISCV_AIA_UNDEF_ADDR (-1)
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#define kvm_riscv_aia_initialized(k) ((k)->arch.aia.initialized)
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#define irqchip_in_kernel(k) ((k)->arch.aia.in_kernel)
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extern unsigned int kvm_riscv_aia_nr_hgei;
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extern unsigned int kvm_riscv_aia_max_ids;
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DECLARE_STATIC_KEY_FALSE(kvm_riscv_aia_available);
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#define kvm_riscv_aia_available() \
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static_branch_unlikely(&kvm_riscv_aia_available)
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extern struct kvm_device_ops kvm_riscv_aia_device_ops;
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void kvm_riscv_vcpu_aia_imsic_release(struct kvm_vcpu *vcpu);
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int kvm_riscv_vcpu_aia_imsic_update(struct kvm_vcpu *vcpu);
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#define KVM_RISCV_AIA_IMSIC_TOPEI (ISELECT_MASK + 1)
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int kvm_riscv_vcpu_aia_imsic_rmw(struct kvm_vcpu *vcpu, unsigned long isel,
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unsigned long *val, unsigned long new_val,
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unsigned long wr_mask);
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int kvm_riscv_aia_imsic_rw_attr(struct kvm *kvm, unsigned long type,
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bool write, unsigned long *val);
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int kvm_riscv_aia_imsic_has_attr(struct kvm *kvm, unsigned long type);
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void kvm_riscv_vcpu_aia_imsic_reset(struct kvm_vcpu *vcpu);
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int kvm_riscv_vcpu_aia_imsic_inject(struct kvm_vcpu *vcpu,
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u32 guest_index, u32 offset, u32 iid);
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int kvm_riscv_vcpu_aia_imsic_init(struct kvm_vcpu *vcpu);
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void kvm_riscv_vcpu_aia_imsic_cleanup(struct kvm_vcpu *vcpu);
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int kvm_riscv_aia_aplic_set_attr(struct kvm *kvm, unsigned long type, u32 v);
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int kvm_riscv_aia_aplic_get_attr(struct kvm *kvm, unsigned long type, u32 *v);
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int kvm_riscv_aia_aplic_has_attr(struct kvm *kvm, unsigned long type);
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int kvm_riscv_aia_aplic_inject(struct kvm *kvm, u32 source, bool level);
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int kvm_riscv_aia_aplic_init(struct kvm *kvm);
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void kvm_riscv_aia_aplic_cleanup(struct kvm *kvm);
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#ifdef CONFIG_32BIT
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void kvm_riscv_vcpu_aia_flush_interrupts(struct kvm_vcpu *vcpu);
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void kvm_riscv_vcpu_aia_sync_interrupts(struct kvm_vcpu *vcpu);
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#else
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static inline void kvm_riscv_vcpu_aia_flush_interrupts(struct kvm_vcpu *vcpu)
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{
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}
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static inline void kvm_riscv_vcpu_aia_sync_interrupts(struct kvm_vcpu *vcpu)
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{
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}
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#endif
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bool kvm_riscv_vcpu_aia_has_interrupts(struct kvm_vcpu *vcpu, u64 mask);
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void kvm_riscv_vcpu_aia_update_hvip(struct kvm_vcpu *vcpu);
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void kvm_riscv_vcpu_aia_load(struct kvm_vcpu *vcpu, int cpu);
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void kvm_riscv_vcpu_aia_put(struct kvm_vcpu *vcpu);
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int kvm_riscv_vcpu_aia_get_csr(struct kvm_vcpu *vcpu,
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unsigned long reg_num,
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unsigned long *out_val);
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int kvm_riscv_vcpu_aia_set_csr(struct kvm_vcpu *vcpu,
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unsigned long reg_num,
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unsigned long val);
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int kvm_riscv_vcpu_aia_rmw_topei(struct kvm_vcpu *vcpu,
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unsigned int csr_num,
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unsigned long *val,
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unsigned long new_val,
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unsigned long wr_mask);
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int kvm_riscv_vcpu_aia_rmw_ireg(struct kvm_vcpu *vcpu, unsigned int csr_num,
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unsigned long *val, unsigned long new_val,
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unsigned long wr_mask);
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#define KVM_RISCV_VCPU_AIA_CSR_FUNCS \
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{ .base = CSR_SIREG, .count = 1, .func = kvm_riscv_vcpu_aia_rmw_ireg }, \
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{ .base = CSR_STOPEI, .count = 1, .func = kvm_riscv_vcpu_aia_rmw_topei },
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int kvm_riscv_vcpu_aia_update(struct kvm_vcpu *vcpu);
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void kvm_riscv_vcpu_aia_reset(struct kvm_vcpu *vcpu);
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int kvm_riscv_vcpu_aia_init(struct kvm_vcpu *vcpu);
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void kvm_riscv_vcpu_aia_deinit(struct kvm_vcpu *vcpu);
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int kvm_riscv_aia_inject_msi_by_id(struct kvm *kvm, u32 hart_index,
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u32 guest_index, u32 iid);
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int kvm_riscv_aia_inject_msi(struct kvm *kvm, struct kvm_msi *msi);
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int kvm_riscv_aia_inject_irq(struct kvm *kvm, unsigned int irq, bool level);
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void kvm_riscv_aia_init_vm(struct kvm *kvm);
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void kvm_riscv_aia_destroy_vm(struct kvm *kvm);
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int kvm_riscv_aia_alloc_hgei(int cpu, struct kvm_vcpu *owner,
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void __iomem **hgei_va, phys_addr_t *hgei_pa);
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void kvm_riscv_aia_free_hgei(int cpu, int hgei);
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void kvm_riscv_aia_wakeon_hgei(struct kvm_vcpu *owner, bool enable);
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void kvm_riscv_aia_enable(void);
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void kvm_riscv_aia_disable(void);
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int kvm_riscv_aia_init(void);
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void kvm_riscv_aia_exit(void);
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#endif
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