426 lines
9.0 KiB
C
426 lines
9.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* arch/sh/drivers/dma/dma-sh.c
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*
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* SuperH On-chip DMAC Support
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*
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* Copyright (C) 2000 Takashi YOSHII
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* Copyright (C) 2003, 2004 Paul Mundt
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* Copyright (C) 2005 Andriy Skulysh
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <mach-dreamcast/mach/dma.h>
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#include <asm/dma.h>
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#include <asm/dma-register.h>
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#include <cpu/dma-register.h>
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#include <cpu/dma.h>
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/*
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* Some of the SoCs feature two DMAC modules. In such a case, the channels are
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* distributed equally among them.
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*/
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#ifdef SH_DMAC_BASE1
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#define SH_DMAC_NR_MD_CH (CONFIG_NR_ONCHIP_DMA_CHANNELS / 2)
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#else
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#define SH_DMAC_NR_MD_CH CONFIG_NR_ONCHIP_DMA_CHANNELS
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#endif
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#define SH_DMAC_CH_SZ 0x10
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/*
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* Define the default configuration for dual address memory-memory transfer.
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* The 0x400 value represents auto-request, external->external.
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*/
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#define RS_DUAL (DM_INC | SM_INC | RS_AUTO | TS_INDEX2VAL(XMIT_SZ_32BIT))
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static unsigned long dma_find_base(unsigned int chan)
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{
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unsigned long base = SH_DMAC_BASE0;
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#ifdef SH_DMAC_BASE1
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if (chan >= SH_DMAC_NR_MD_CH)
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base = SH_DMAC_BASE1;
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#endif
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return base;
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}
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static unsigned long dma_base_addr(unsigned int chan)
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{
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unsigned long base = dma_find_base(chan);
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chan = (chan % SH_DMAC_NR_MD_CH) * SH_DMAC_CH_SZ;
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/* DMAOR is placed inside the channel register space. Step over it. */
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if (chan >= DMAOR)
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base += SH_DMAC_CH_SZ;
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return base + chan;
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}
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#ifdef CONFIG_SH_DMA_IRQ_MULTI
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static inline unsigned int get_dmte_irq(unsigned int chan)
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{
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return chan >= 6 ? DMTE6_IRQ : DMTE0_IRQ;
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}
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#else
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static unsigned int dmte_irq_map[] = {
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DMTE0_IRQ, DMTE0_IRQ + 1, DMTE0_IRQ + 2, DMTE0_IRQ + 3,
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#ifdef DMTE4_IRQ
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DMTE4_IRQ, DMTE4_IRQ + 1,
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#endif
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#ifdef DMTE6_IRQ
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DMTE6_IRQ, DMTE6_IRQ + 1,
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#endif
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#ifdef DMTE8_IRQ
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DMTE8_IRQ, DMTE9_IRQ, DMTE10_IRQ, DMTE11_IRQ,
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#endif
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};
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static inline unsigned int get_dmte_irq(unsigned int chan)
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{
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return dmte_irq_map[chan];
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}
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#endif
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/*
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* We determine the correct shift size based off of the CHCR transmit size
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* for the given channel. Since we know that it will take:
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*
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* info->count >> ts_shift[transmit_size]
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*
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* iterations to complete the transfer.
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*/
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static unsigned int ts_shift[] = TS_SHIFT;
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static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
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{
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u32 chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
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int cnt = ((chcr & CHCR_TS_LOW_MASK) >> CHCR_TS_LOW_SHIFT) |
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((chcr & CHCR_TS_HIGH_MASK) >> CHCR_TS_HIGH_SHIFT);
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return ts_shift[cnt];
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}
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/*
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* The transfer end interrupt must read the chcr register to end the
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* hardware interrupt active condition.
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* Besides that it needs to waken any waiting process, which should handle
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* setting up the next transfer.
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*/
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static irqreturn_t dma_tei(int irq, void *dev_id)
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{
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struct dma_channel *chan = dev_id;
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u32 chcr;
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chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
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if (!(chcr & CHCR_TE))
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return IRQ_NONE;
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chcr &= ~(CHCR_IE | CHCR_DE);
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__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
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wake_up(&chan->wait_queue);
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return IRQ_HANDLED;
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}
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static int sh_dmac_request_dma(struct dma_channel *chan)
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{
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if (unlikely(!(chan->flags & DMA_TEI_CAPABLE)))
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return 0;
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return request_irq(get_dmte_irq(chan->chan), dma_tei, IRQF_SHARED,
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chan->dev_id, chan);
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}
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static void sh_dmac_free_dma(struct dma_channel *chan)
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{
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free_irq(get_dmte_irq(chan->chan), chan);
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}
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static int
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sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
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{
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if (!chcr)
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chcr = RS_DUAL | CHCR_IE;
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if (chcr & CHCR_IE) {
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chcr &= ~CHCR_IE;
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chan->flags |= DMA_TEI_CAPABLE;
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} else {
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chan->flags &= ~DMA_TEI_CAPABLE;
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}
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__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
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chan->flags |= DMA_CONFIGURED;
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return 0;
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}
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static void sh_dmac_enable_dma(struct dma_channel *chan)
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{
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int irq;
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u32 chcr;
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chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
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chcr |= CHCR_DE;
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if (chan->flags & DMA_TEI_CAPABLE)
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chcr |= CHCR_IE;
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__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
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if (chan->flags & DMA_TEI_CAPABLE) {
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irq = get_dmte_irq(chan->chan);
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enable_irq(irq);
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}
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}
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static void sh_dmac_disable_dma(struct dma_channel *chan)
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{
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int irq;
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u32 chcr;
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if (chan->flags & DMA_TEI_CAPABLE) {
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irq = get_dmte_irq(chan->chan);
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disable_irq(irq);
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}
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chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
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chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
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__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
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}
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static int sh_dmac_xfer_dma(struct dma_channel *chan)
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{
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/*
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* If we haven't pre-configured the channel with special flags, use
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* the defaults.
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*/
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if (unlikely(!(chan->flags & DMA_CONFIGURED)))
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sh_dmac_configure_channel(chan, 0);
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sh_dmac_disable_dma(chan);
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/*
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* Single-address mode usage note!
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*
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* It's important that we don't accidentally write any value to SAR/DAR
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* (this includes 0) that hasn't been directly specified by the user if
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* we're in single-address mode.
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*
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* In this case, only one address can be defined, anything else will
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* result in a DMA address error interrupt (at least on the SH-4),
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* which will subsequently halt the transfer.
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*
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* Channel 2 on the Dreamcast is a special case, as this is used for
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* cascading to the PVR2 DMAC. In this case, we still need to write
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* SAR and DAR, regardless of value, in order for cascading to work.
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*/
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if (chan->sar || (mach_is_dreamcast() &&
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chan->chan == PVR2_CASCADE_CHAN))
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__raw_writel(chan->sar, (dma_base_addr(chan->chan) + SAR));
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if (chan->dar || (mach_is_dreamcast() &&
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chan->chan == PVR2_CASCADE_CHAN))
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__raw_writel(chan->dar, (dma_base_addr(chan->chan) + DAR));
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__raw_writel(chan->count >> calc_xmit_shift(chan),
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(dma_base_addr(chan->chan) + TCR));
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sh_dmac_enable_dma(chan);
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return 0;
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}
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static int sh_dmac_get_dma_residue(struct dma_channel *chan)
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{
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if (!(__raw_readl(dma_base_addr(chan->chan) + CHCR) & CHCR_DE))
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return 0;
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return __raw_readl(dma_base_addr(chan->chan) + TCR)
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<< calc_xmit_shift(chan);
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}
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/*
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* DMAOR handling
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*/
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#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
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defined(CONFIG_CPU_SUBTYPE_SH7724) || \
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defined(CONFIG_CPU_SUBTYPE_SH7780) || \
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defined(CONFIG_CPU_SUBTYPE_SH7785)
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#define NR_DMAOR 2
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#else
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#define NR_DMAOR 1
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#endif
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#define dmaor_read_reg(n) __raw_readw(dma_find_base((n) * \
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SH_DMAC_NR_MD_CH) + DMAOR)
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#define dmaor_write_reg(n, data) __raw_writew(data, \
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dma_find_base((n) * \
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SH_DMAC_NR_MD_CH) + DMAOR)
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static inline int dmaor_reset(int no)
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{
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unsigned long dmaor = dmaor_read_reg(no);
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/* Try to clear the error flags first, incase they are set */
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dmaor &= ~(DMAOR_NMIF | DMAOR_AE);
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dmaor_write_reg(no, dmaor);
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dmaor |= DMAOR_INIT;
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dmaor_write_reg(no, dmaor);
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/* See if we got an error again */
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if ((dmaor_read_reg(no) & (DMAOR_AE | DMAOR_NMIF))) {
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printk(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
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return -EINVAL;
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}
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return 0;
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}
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/*
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* DMAE handling
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*/
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#ifdef CONFIG_CPU_SH4
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#if defined(DMAE1_IRQ)
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#define NR_DMAE 2
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#else
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#define NR_DMAE 1
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#endif
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static const char *dmae_name[] = {
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"DMAC Address Error0",
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"DMAC Address Error1"
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};
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#ifdef CONFIG_SH_DMA_IRQ_MULTI
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static inline unsigned int get_dma_error_irq(int n)
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{
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return get_dmte_irq(n * 6);
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}
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#else
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static unsigned int dmae_irq_map[] = {
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DMAE0_IRQ,
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#ifdef DMAE1_IRQ
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DMAE1_IRQ,
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#endif
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};
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static inline unsigned int get_dma_error_irq(int n)
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{
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return dmae_irq_map[n];
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}
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#endif
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static irqreturn_t dma_err(int irq, void *dummy)
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{
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int i;
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for (i = 0; i < NR_DMAOR; i++)
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dmaor_reset(i);
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disable_irq(irq);
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return IRQ_HANDLED;
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}
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static int dmae_irq_init(void)
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{
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int n;
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for (n = 0; n < NR_DMAE; n++) {
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int i = request_irq(get_dma_error_irq(n), dma_err,
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IRQF_SHARED, dmae_name[n], (void *)dmae_name[n]);
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if (unlikely(i < 0)) {
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printk(KERN_ERR "%s request_irq fail\n", dmae_name[n]);
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return i;
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}
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}
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return 0;
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}
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static void dmae_irq_free(void)
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{
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int n;
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for (n = 0; n < NR_DMAE; n++)
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free_irq(get_dma_error_irq(n), NULL);
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}
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#else
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static inline int dmae_irq_init(void)
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{
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return 0;
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}
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static void dmae_irq_free(void)
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{
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}
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#endif
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static struct dma_ops sh_dmac_ops = {
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.request = sh_dmac_request_dma,
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.free = sh_dmac_free_dma,
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.get_residue = sh_dmac_get_dma_residue,
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.xfer = sh_dmac_xfer_dma,
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.configure = sh_dmac_configure_channel,
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};
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static struct dma_info sh_dmac_info = {
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.name = "sh_dmac",
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.nr_channels = CONFIG_NR_ONCHIP_DMA_CHANNELS,
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.ops = &sh_dmac_ops,
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.flags = DMAC_CHANNELS_TEI_CAPABLE,
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};
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static int __init sh_dmac_init(void)
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{
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struct dma_info *info = &sh_dmac_info;
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int i, rc;
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/*
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* Initialize DMAE, for parts that support it.
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*/
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rc = dmae_irq_init();
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if (unlikely(rc != 0))
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return rc;
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/*
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* Initialize DMAOR, and clean up any error flags that may have
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* been set.
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*/
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for (i = 0; i < NR_DMAOR; i++) {
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rc = dmaor_reset(i);
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if (unlikely(rc != 0))
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return rc;
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}
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return register_dmac(info);
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}
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static void __exit sh_dmac_exit(void)
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{
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dmae_irq_free();
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unregister_dmac(&sh_dmac_info);
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}
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subsys_initcall(sh_dmac_init);
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module_exit(sh_dmac_exit);
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MODULE_AUTHOR("Takashi YOSHII, Paul Mundt, Andriy Skulysh");
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MODULE_DESCRIPTION("SuperH On-Chip DMAC Support");
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MODULE_LICENSE("GPL v2");
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