917 lines
28 KiB
Plaintext
917 lines
28 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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# Put here option for CPU selection and depending optimization
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choice
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prompt "Processor family"
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default M686 if X86_32
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default GENERIC_CPU if X86_64
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help
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This is the processor type of your CPU. This information is
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used for optimizing purposes. In order to compile a kernel
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that can run on all supported x86 CPU types (albeit not
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optimally fast), you can specify "486" here.
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Note that the 386 is no longer supported, this includes
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AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI 486DLC/DLC2,
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UMC 486SX-S and the NexGen Nx586.
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The kernel will not necessarily run on earlier architectures than
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the one you have chosen, e.g. a Pentium optimized kernel will run on
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a PPro, but not necessarily on a i486.
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Here are the settings recommended for greatest speed:
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- "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or
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SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S.
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- "586" for generic Pentium CPUs lacking the TSC
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(time stamp counter) register.
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- "Pentium-Classic" for the Intel Pentium.
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- "Pentium-MMX" for the Intel Pentium MMX.
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- "Pentium-Pro" for the Intel Pentium Pro.
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- "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron.
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- "Pentium-III" for the Intel Pentium III or Coppermine Celeron.
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- "Pentium-4" for the Intel Pentium 4 or P4-based Celeron.
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- "K6" for the AMD K6, K6-II and K6-III (aka K6-3D).
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- "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird).
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- "Opteron/Athlon64/Hammer/K8" for all K8 and newer AMD CPUs.
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- "Crusoe" for the Transmeta Crusoe series.
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- "Efficeon" for the Transmeta Efficeon series.
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- "Winchip-C6" for original IDT Winchip.
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- "Winchip-2" for IDT Winchips with 3dNow! capabilities.
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- "AMD Elan" for the 32-bit AMD Elan embedded CPU.
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- "GeodeGX1" for Geode GX1 (Cyrix MediaGX).
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- "Geode GX/LX" For AMD Geode GX and LX processors.
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- "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
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- "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above).
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- "VIA C7" for VIA C7.
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- "Intel P4" for the Pentium 4/Netburst microarchitecture.
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- "Core 2/newer Xeon" for all core2 and newer Intel CPUs.
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- "Intel Atom" for the Atom-microarchitecture CPUs.
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- "Generic-x86-64" for a kernel which runs on any x86-64 CPU.
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See each option's help text for additional details. If you don't know
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what to do, choose "486".
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config M486SX
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bool "486SX"
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depends on X86_32
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help
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Select this for an 486-class CPU without an FPU such as
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AMD/Cyrix/IBM/Intel SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5S.
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config M486
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bool "486DX"
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depends on X86_32
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help
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Select this for an 486-class CPU such as AMD/Cyrix/IBM/Intel
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486DX/DX2/DX4 and UMC U5D.
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config M586
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bool "586/K5/5x86/6x86/6x86MX"
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depends on X86_32
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help
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Select this for an 586 or 686 series processor such as the AMD K5,
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the Cyrix 5x86, 6x86 and 6x86MX. This choice does not
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assume the RDTSC (Read Time Stamp Counter) instruction.
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config M586TSC
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bool "Pentium-Classic"
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depends on X86_32
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help
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Select this for a Pentium Classic processor with the RDTSC (Read
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Time Stamp Counter) instruction for benchmarking.
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config M586MMX
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bool "Pentium-MMX"
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depends on X86_32
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help
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Select this for a Pentium with the MMX graphics/multimedia
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extended instructions.
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config M686
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bool "Pentium-Pro"
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depends on X86_32
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help
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Select this for Intel Pentium Pro chips. This enables the use of
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Pentium Pro extended instructions, and disables the init-time guard
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against the f00f bug found in earlier Pentiums.
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config MPENTIUMII
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bool "Pentium-II/Celeron(pre-Coppermine)"
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depends on X86_32
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help
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Select this for Intel chips based on the Pentium-II and
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pre-Coppermine Celeron core. This option enables an unaligned
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copy optimization, compiles the kernel with optimization flags
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tailored for the chip, and applies any applicable Pentium Pro
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optimizations.
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config MPENTIUMIII
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bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon"
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depends on X86_32
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help
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Select this for Intel chips based on the Pentium-III and
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Celeron-Coppermine core. This option enables use of some
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extended prefetch instructions in addition to the Pentium II
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extensions.
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config MPENTIUMM
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bool "Pentium M"
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depends on X86_32
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help
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Select this for Intel Pentium M (not Pentium-4 M)
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notebook chips.
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config MPENTIUM4
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bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon"
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depends on X86_32
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help
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Select this for Intel Pentium 4 chips. This includes the
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Pentium 4, Pentium D, P4-based Celeron and Xeon, and
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Pentium-4 M (not Pentium M) chips. This option enables compile
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flags optimized for the chip, uses the correct cache line size, and
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applies any applicable optimizations.
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CPUIDs: F[0-6][1-A] (in /proc/cpuinfo show = cpu family : 15 )
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Select this for:
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Pentiums (Pentium 4, Pentium D, Celeron, Celeron D) corename:
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-Willamette
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-Northwood
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-Mobile Pentium 4
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-Mobile Pentium 4 M
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-Extreme Edition (Gallatin)
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-Prescott
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-Prescott 2M
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-Cedar Mill
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-Presler
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-Smithfiled
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Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename:
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-Foster
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-Prestonia
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-Gallatin
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-Nocona
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-Irwindale
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-Cranford
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-Potomac
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-Paxville
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-Dempsey
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config MK6
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bool "AMD K6/K6-II/K6-III"
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depends on X86_32
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help
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Select this for an AMD K6-family processor. Enables use of
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some extended instructions, and passes appropriate optimization
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flags to GCC.
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config MK7
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bool "AMD Athlon/Duron/K7"
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depends on X86_32
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help
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Select this for an AMD Athlon K7-family processor. Enables use of
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some extended instructions, and passes appropriate optimization
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flags to GCC.
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config MK8
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bool "AMD Opteron/Athlon64/Hammer/K8"
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help
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Select this for an AMD Opteron or Athlon64 Hammer-family processor.
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Enables use of some extended instructions, and passes appropriate
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optimization flags to GCC.
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config MK8SSE3
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bool "AMD Opteron/Athlon64/Hammer/K8 with SSE3"
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help
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Select this for improved AMD Opteron or Athlon64 Hammer-family processors.
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Enables use of some extended instructions, and passes appropriate
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optimization flags to GCC.
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config MK10
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bool "AMD 61xx/7x50/PhenomX3/X4/II/K10"
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help
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Select this for an AMD 61xx Eight-Core Magny-Cours, Athlon X2 7x50,
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Phenom X3/X4/II, Athlon II X2/X3/X4, or Turion II-family processor.
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Enables use of some extended instructions, and passes appropriate
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optimization flags to GCC.
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config MBARCELONA
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bool "AMD Barcelona"
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help
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Select this for AMD Family 10h Barcelona processors.
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Enables -march=barcelona
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config MBOBCAT
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bool "AMD Bobcat"
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help
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Select this for AMD Family 14h Bobcat processors.
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Enables -march=btver1
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config MJAGUAR
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bool "AMD Jaguar"
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help
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Select this for AMD Family 16h Jaguar processors.
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Enables -march=btver2
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config MBULLDOZER
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bool "AMD Bulldozer"
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help
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Select this for AMD Family 15h Bulldozer processors.
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Enables -march=bdver1
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config MPILEDRIVER
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bool "AMD Piledriver"
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help
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Select this for AMD Family 15h Piledriver processors.
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Enables -march=bdver2
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config MSTEAMROLLER
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bool "AMD Steamroller"
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help
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Select this for AMD Family 15h Steamroller processors.
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Enables -march=bdver3
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config MEXCAVATOR
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bool "AMD Excavator"
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help
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Select this for AMD Family 15h Excavator processors.
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Enables -march=bdver4
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config MZEN
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bool "AMD Zen"
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help
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Select this for AMD Family 17h Zen processors.
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Enables -march=znver1
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config MZEN2
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bool "AMD Zen 2"
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help
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Select this for AMD Family 17h Zen 2 processors.
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Enables -march=znver2
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config MZEN3
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bool "AMD Zen 3"
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depends on (CC_IS_GCC && GCC_VERSION >= 100300) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
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help
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Select this for AMD Family 19h Zen 3 processors.
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Enables -march=znver3
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config MZEN4
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bool "AMD Zen 4"
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depends on (CC_IS_GCC && GCC_VERSION >= 130000) || (CC_IS_CLANG && CLANG_VERSION >= 160000)
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help
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Select this for AMD Family 19h Zen 4 processors.
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Enables -march=znver4
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config MCRUSOE
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bool "Crusoe"
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depends on X86_32
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help
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Select this for a Transmeta Crusoe processor. Treats the processor
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like a 586 with TSC, and sets some GCC optimization flags (like a
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Pentium Pro with no alignment requirements).
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config MEFFICEON
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bool "Efficeon"
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depends on X86_32
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help
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Select this for a Transmeta Efficeon processor.
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config MWINCHIPC6
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bool "Winchip-C6"
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depends on X86_32
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help
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Select this for an IDT Winchip C6 chip. Linux and GCC
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treat this chip as a 586TSC with some extended instructions
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and alignment requirements.
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config MWINCHIP3D
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bool "Winchip-2/Winchip-2A/Winchip-3"
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depends on X86_32
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help
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Select this for an IDT Winchip-2, 2A or 3. Linux and GCC
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treat this chip as a 586TSC with some extended instructions
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and alignment requirements. Also enable out of order memory
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stores for this CPU, which can increase performance of some
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operations.
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config MELAN
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bool "AMD Elan"
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depends on X86_32
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help
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Select this for an AMD Elan processor.
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Do not use this option for K6/Athlon/Opteron processors!
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config MGEODEGX1
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bool "GeodeGX1"
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depends on X86_32
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help
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Select this for a Geode GX1 (Cyrix MediaGX) chip.
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config MGEODE_LX
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bool "Geode GX/LX"
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depends on X86_32
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help
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Select this for AMD Geode GX and LX processors.
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config MCYRIXIII
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bool "CyrixIII/VIA-C3"
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depends on X86_32
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help
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Select this for a Cyrix III or C3 chip. Presently Linux and GCC
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treat this chip as a generic 586. Whilst the CPU is 686 class,
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it lacks the cmov extension which gcc assumes is present when
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generating 686 code.
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Note that Nehemiah (Model 9) and above will not boot with this
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kernel due to them lacking the 3DNow! instructions used in earlier
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incarnations of the CPU.
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config MVIAC3_2
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bool "VIA C3-2 (Nehemiah)"
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depends on X86_32
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help
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Select this for a VIA C3 "Nehemiah". Selecting this enables usage
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of SSE and tells gcc to treat the CPU as a 686.
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Note, this kernel will not boot on older (pre model 9) C3s.
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config MVIAC7
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bool "VIA C7"
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depends on X86_32
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help
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Select this for a VIA C7. Selecting this uses the correct cache
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shift and tells gcc to treat the CPU as a 686.
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config MPSC
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bool "Intel P4 / older Netburst based Xeon"
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depends on X86_64
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help
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Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey
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Xeon CPUs with Intel 64bit which is compatible with x86-64.
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Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the
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Netburst core and shouldn't use this option. You can distinguish them
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using the cpu family field
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in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one.
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config MCORE2
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bool "Intel Core 2"
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help
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Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and
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53xx) CPUs. You can distinguish newer from older Xeons by the CPU
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family in /proc/cpuinfo. Newer ones have 6 and older ones 15
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(not a typo)
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Enables -march=core2
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config MATOM
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bool "Intel Atom"
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help
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Select this for the Intel Atom platform. Intel Atom CPUs have an
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in-order pipelining architecture and thus can benefit from
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accordingly optimized code. Use a recent GCC with specific Atom
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support in order to fully benefit from selecting this option.
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config MNEHALEM
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bool "Intel Nehalem"
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select X86_P6_NOP
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help
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Select this for 1st Gen Core processors in the Nehalem family.
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Enables -march=nehalem
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config MWESTMERE
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bool "Intel Westmere"
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select X86_P6_NOP
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help
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Select this for the Intel Westmere formerly Nehalem-C family.
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Enables -march=westmere
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config MSILVERMONT
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bool "Intel Silvermont"
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select X86_P6_NOP
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help
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Select this for the Intel Silvermont platform.
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Enables -march=silvermont
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config MGOLDMONT
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bool "Intel Goldmont"
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select X86_P6_NOP
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help
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Select this for the Intel Goldmont platform including Apollo Lake and Denverton.
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Enables -march=goldmont
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config MGOLDMONTPLUS
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bool "Intel Goldmont Plus"
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select X86_P6_NOP
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help
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Select this for the Intel Goldmont Plus platform including Gemini Lake.
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Enables -march=goldmont-plus
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config MSANDYBRIDGE
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bool "Intel Sandy Bridge"
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select X86_P6_NOP
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help
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Select this for 2nd Gen Core processors in the Sandy Bridge family.
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Enables -march=sandybridge
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config MIVYBRIDGE
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bool "Intel Ivy Bridge"
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select X86_P6_NOP
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help
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Select this for 3rd Gen Core processors in the Ivy Bridge family.
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Enables -march=ivybridge
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config MHASWELL
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bool "Intel Haswell"
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select X86_P6_NOP
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help
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Select this for 4th Gen Core processors in the Haswell family.
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Enables -march=haswell
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config MBROADWELL
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bool "Intel Broadwell"
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select X86_P6_NOP
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help
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Select this for 5th Gen Core processors in the Broadwell family.
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Enables -march=broadwell
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config MSKYLAKE
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bool "Intel Skylake"
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select X86_P6_NOP
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help
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Select this for 6th Gen Core processors in the Skylake family.
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Enables -march=skylake
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config MSKYLAKEX
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bool "Intel Skylake X"
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select X86_P6_NOP
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help
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Select this for 6th Gen Core processors in the Skylake X family.
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Enables -march=skylake-avx512
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config MCANNONLAKE
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bool "Intel Cannon Lake"
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select X86_P6_NOP
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help
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Select this for 8th Gen Core processors
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Enables -march=cannonlake
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config MICELAKE
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bool "Intel Ice Lake"
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select X86_P6_NOP
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help
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Select this for 10th Gen Core processors in the Ice Lake family.
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Enables -march=icelake-client
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config MCASCADELAKE
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bool "Intel Cascade Lake"
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select X86_P6_NOP
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help
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Select this for Xeon processors in the Cascade Lake family.
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Enables -march=cascadelake
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config MCOOPERLAKE
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bool "Intel Cooper Lake"
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depends on (CC_IS_GCC && GCC_VERSION > 100100) || (CC_IS_CLANG && CLANG_VERSION >= 100000)
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select X86_P6_NOP
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help
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Select this for Xeon processors in the Cooper Lake family.
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Enables -march=cooperlake
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config MTIGERLAKE
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bool "Intel Tiger Lake"
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depends on (CC_IS_GCC && GCC_VERSION > 100100) || (CC_IS_CLANG && CLANG_VERSION >= 100000)
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select X86_P6_NOP
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help
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Select this for third-generation 10 nm process processors in the Tiger Lake family.
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Enables -march=tigerlake
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config MSAPPHIRERAPIDS
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bool "Intel Sapphire Rapids"
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depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
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select X86_P6_NOP
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help
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Select this for fourth-generation 10 nm process processors in the Sapphire Rapids family.
|
|
|
|
Enables -march=sapphirerapids
|
|
|
|
config MROCKETLAKE
|
|
bool "Intel Rocket Lake"
|
|
depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
|
|
select X86_P6_NOP
|
|
help
|
|
|
|
Select this for eleventh-generation processors in the Rocket Lake family.
|
|
|
|
Enables -march=rocketlake
|
|
|
|
config MALDERLAKE
|
|
bool "Intel Alder Lake"
|
|
depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
|
|
select X86_P6_NOP
|
|
help
|
|
|
|
Select this for twelfth-generation processors in the Alder Lake family.
|
|
|
|
Enables -march=alderlake
|
|
|
|
config MRAPTORLAKE
|
|
bool "Intel Raptor Lake"
|
|
depends on (CC_IS_GCC && GCC_VERSION >= 130000) || (CC_IS_CLANG && CLANG_VERSION >= 150500)
|
|
select X86_P6_NOP
|
|
help
|
|
|
|
Select this for thirteenth-generation processors in the Raptor Lake family.
|
|
|
|
Enables -march=raptorlake
|
|
|
|
config MMETEORLAKE
|
|
bool "Intel Meteor Lake"
|
|
depends on (CC_IS_GCC && GCC_VERSION >= 130000) || (CC_IS_CLANG && CLANG_VERSION >= 150500)
|
|
select X86_P6_NOP
|
|
help
|
|
|
|
Select this for fourteenth-generation processors in the Meteor Lake family.
|
|
|
|
Enables -march=meteorlake
|
|
|
|
config MEMERALDRAPIDS
|
|
bool "Intel Emerald Rapids"
|
|
depends on (CC_IS_GCC && GCC_VERSION > 130000) || (CC_IS_CLANG && CLANG_VERSION >= 150500)
|
|
select X86_P6_NOP
|
|
help
|
|
|
|
Select this for fifth-generation 10 nm process processors in the Emerald Rapids family.
|
|
|
|
Enables -march=emeraldrapids
|
|
|
|
config GENERIC_CPU
|
|
bool "Generic-x86-64"
|
|
depends on X86_64
|
|
help
|
|
Generic x86-64 CPU.
|
|
Run equally well on all x86-64 CPUs.
|
|
|
|
config GENERIC_CPU2
|
|
bool "Generic-x86-64-v2"
|
|
depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
|
|
depends on X86_64
|
|
help
|
|
Generic x86-64 CPU.
|
|
Run equally well on all x86-64 CPUs with min support of x86-64-v2.
|
|
|
|
config GENERIC_CPU3
|
|
bool "Generic-x86-64-v3"
|
|
depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
|
|
depends on X86_64
|
|
help
|
|
Generic x86-64-v3 CPU with v3 instructions.
|
|
Run equally well on all x86-64 CPUs with min support of x86-64-v3.
|
|
|
|
config GENERIC_CPU4
|
|
bool "Generic-x86-64-v4"
|
|
depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
|
|
depends on X86_64
|
|
help
|
|
Generic x86-64 CPU with v4 instructions.
|
|
Run equally well on all x86-64 CPUs with min support of x86-64-v4.
|
|
|
|
config MNATIVE_INTEL
|
|
bool "Intel-Native optimizations autodetected by the compiler"
|
|
help
|
|
|
|
Clang 3.8, GCC 4.2 and above support -march=native, which automatically detects
|
|
the optimum settings to use based on your processor. Do NOT use this
|
|
for AMD CPUs. Intel Only!
|
|
|
|
Enables -march=native
|
|
|
|
config MNATIVE_AMD
|
|
bool "AMD-Native optimizations autodetected by the compiler"
|
|
help
|
|
|
|
Clang 3.8, GCC 4.2 and above support -march=native, which automatically detects
|
|
the optimum settings to use based on your processor. Do NOT use this
|
|
for Intel CPUs. AMD Only!
|
|
|
|
Enables -march=native
|
|
|
|
endchoice
|
|
|
|
config X86_GENERIC
|
|
bool "Generic x86 support"
|
|
depends on X86_32
|
|
help
|
|
Instead of just including optimizations for the selected
|
|
x86 variant (e.g. PII, Crusoe or Athlon), include some more
|
|
generic optimizations as well. This will make the kernel
|
|
perform better on x86 CPUs other than that selected.
|
|
|
|
This is really intended for distributors who need more
|
|
generic optimizations.
|
|
|
|
#
|
|
# Define implied options from the CPU selection here
|
|
config X86_INTERNODE_CACHE_SHIFT
|
|
int
|
|
default "12" if X86_VSMP
|
|
default X86_L1_CACHE_SHIFT
|
|
|
|
config X86_L1_CACHE_SHIFT
|
|
int
|
|
default "7" if MPENTIUM4 || MPSC
|
|
default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || MK8SSE3 || MK10 \
|
|
|| MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER \
|
|
|| MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MZEN4 || MNEHALEM || MWESTMERE || MSILVERMONT \
|
|
|| MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL \
|
|
|| MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE \
|
|
|| MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MRAPTORLAKE || MMETEORLAKE \
|
|
|| MEMERALDRAPIDS || MNATIVE_INTEL || MNATIVE_AMD || X86_GENERIC || GENERIC_CPU || GENERIC_CPU2 \
|
|
|| GENERIC_CPU3 || GENERIC_CPU4
|
|
default "4" if MELAN || M486SX || M486 || MGEODEGX1
|
|
default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII \
|
|
|| MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
|
|
|
|
config X86_F00F_BUG
|
|
def_bool y
|
|
depends on M586MMX || M586TSC || M586 || M486SX || M486
|
|
|
|
config X86_INVD_BUG
|
|
def_bool y
|
|
depends on M486SX || M486
|
|
|
|
config X86_ALIGNMENT_16
|
|
def_bool y
|
|
depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MELAN || MK6 || M586MMX || M586TSC \
|
|
|| M586 || M486SX || M486 || MVIAC3_2 || MGEODEGX1
|
|
|
|
config X86_INTEL_USERCOPY
|
|
def_bool y
|
|
depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC \
|
|
|| MK8 || MK7 || MEFFICEON || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT \
|
|
|| MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX \
|
|
|| MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS \
|
|
|| MROCKETLAKE || MALDERLAKE || MRAPTORLAKE || MMETEORLAKE || MEMERALDRAPIDS || MNATIVE_INTEL
|
|
|
|
config X86_USE_PPRO_CHECKSUM
|
|
def_bool y
|
|
depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM \
|
|
|| MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX \
|
|
|| MCORE2 || MATOM || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER \
|
|
|| MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MZEN4 || MNEHALEM \
|
|
|| MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE \
|
|
|| MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE \
|
|
|| MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE \
|
|
|| MALDERLAKE || MRAPTORLAKE || MMETEORLAKE || MEMERALDRAPIDS || MNATIVE_INTEL || MNATIVE_AMD
|
|
|
|
#
|
|
# P6_NOPs are a relatively minor optimization that require a family >=
|
|
# 6 processor, except that it is broken on certain VIA chips.
|
|
# Furthermore, AMD chips prefer a totally different sequence of NOPs
|
|
# (which work on all CPUs). In addition, it looks like Virtual PC
|
|
# does not understand them.
|
|
#
|
|
# As a result, disallow these if we're not compiling for X86_64 (these
|
|
# NOPs do work on all x86-64 capable chips); the list of processors in
|
|
# the right-hand clause are the cores that benefit from this optimization.
|
|
#
|
|
config X86_P6_NOP
|
|
def_bool y
|
|
depends on X86_64
|
|
depends on (MCORE2 || MPENTIUM4 || MPSC || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT \
|
|
|| MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE \
|
|
|| MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE \
|
|
|| MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MRAPTORLAKE || MMETEORLAKE || MEMERALDRAPIDS \
|
|
|| MNATIVE_INTEL)
|
|
|
|
config X86_TSC
|
|
def_bool y
|
|
depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM \
|
|
|| MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 \
|
|
|| MGEODE_LX || MCORE2 || MATOM || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER \
|
|
|| MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MZEN4 || MNEHALEM \
|
|
|| MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL \
|
|
|| MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE \
|
|
|| MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MRAPTORLAKE || MMETEORLAKE || MEMERALDRAPIDS \
|
|
|| MNATIVE_INTEL || MNATIVE_AMD) || X86_64
|
|
|
|
config X86_CMPXCHG64
|
|
def_bool y
|
|
depends on X86_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 \
|
|
|| M586TSC || M586MMX || MATOM || MGEODE_LX || MGEODEGX1 || MK6 || MK7 || MK8 || MK8SSE3 || MK10 \
|
|
|| MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN \
|
|
|| MZEN2 || MZEN3 || MZEN4 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS \
|
|
|| MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE \
|
|
|| MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE \
|
|
|| MALDERLAKE || MRAPTORLAKE || MMETEORLAKE || MEMERALDRAPIDS || MNATIVE_INTEL || MNATIVE_AMD
|
|
|
|
# this should be set for all -march=.. options where the compiler
|
|
# generates cmov.
|
|
config X86_CMOV
|
|
def_bool y
|
|
depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 \
|
|
|| MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX || MK8SSE3 || MK10 \
|
|
|| MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR \
|
|
|| MZEN || MZEN2 || MZEN3 || MZEN4 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT \
|
|
|| MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX \
|
|
|| MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS \
|
|
|| MROCKETLAKE || MALDERLAKE || MRAPTORLAKE || MMETEORLAKE || MEMERALDRAPIDS || MNATIVE_INTEL || MNATIVE_AMD)
|
|
|
|
config X86_MINIMUM_CPU_FAMILY
|
|
int
|
|
default "64" if X86_64
|
|
default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 \
|
|
|| MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MCRUSOE || MCORE2 || MK7 || MK8 || MK8SSE3 \
|
|
|| MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER \
|
|
|| MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MZEN4 || MNEHALEM || MWESTMERE || MSILVERMONT \
|
|
|| MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL \
|
|
|| MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE \
|
|
|| MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MRAPTORLAKE || MRAPTORLAKE \
|
|
|| MNATIVE_INTEL || MNATIVE_AMD)
|
|
default "5" if X86_32 && X86_CMPXCHG64
|
|
default "4"
|
|
|
|
config X86_DEBUGCTLMSR
|
|
def_bool y
|
|
depends on !(MK6 || MWINCHIPC6 || MWINCHIP3D || MCYRIXIII || M586MMX || M586TSC || M586 \
|
|
|| M486SX || M486) && !UML
|
|
|
|
config IA32_FEAT_CTL
|
|
def_bool y
|
|
depends on CPU_SUP_INTEL || CPU_SUP_CENTAUR || CPU_SUP_ZHAOXIN
|
|
|
|
config X86_VMX_FEATURE_NAMES
|
|
def_bool y
|
|
depends on IA32_FEAT_CTL
|
|
|
|
menuconfig PROCESSOR_SELECT
|
|
bool "Supported processor vendors" if EXPERT
|
|
help
|
|
This lets you choose what x86 vendor support code your kernel
|
|
will include.
|
|
|
|
config CPU_SUP_INTEL
|
|
default y
|
|
bool "Support Intel processors" if PROCESSOR_SELECT
|
|
help
|
|
This enables detection, tunings and quirks for Intel processors
|
|
|
|
You need this enabled if you want your kernel to run on an
|
|
Intel CPU. Disabling this option on other types of CPUs
|
|
makes the kernel a tiny bit smaller. Disabling it on an Intel
|
|
CPU might render the kernel unbootable.
|
|
|
|
If unsure, say N.
|
|
|
|
config CPU_SUP_CYRIX_32
|
|
default y
|
|
bool "Support Cyrix processors" if PROCESSOR_SELECT
|
|
depends on M486SX || M486 || M586 || M586TSC || M586MMX || (EXPERT && !64BIT)
|
|
help
|
|
This enables detection, tunings and quirks for Cyrix processors
|
|
|
|
You need this enabled if you want your kernel to run on a
|
|
Cyrix CPU. Disabling this option on other types of CPUs
|
|
makes the kernel a tiny bit smaller. Disabling it on a Cyrix
|
|
CPU might render the kernel unbootable.
|
|
|
|
If unsure, say N.
|
|
|
|
config CPU_SUP_AMD
|
|
default y
|
|
bool "Support AMD processors" if PROCESSOR_SELECT
|
|
help
|
|
This enables detection, tunings and quirks for AMD processors
|
|
|
|
You need this enabled if you want your kernel to run on an
|
|
AMD CPU. Disabling this option on other types of CPUs
|
|
makes the kernel a tiny bit smaller. Disabling it on an AMD
|
|
CPU might render the kernel unbootable.
|
|
|
|
If unsure, say N.
|
|
|
|
config CPU_SUP_HYGON
|
|
default y
|
|
bool "Support Hygon processors" if PROCESSOR_SELECT
|
|
select CPU_SUP_AMD
|
|
help
|
|
This enables detection, tunings and quirks for Hygon processors
|
|
|
|
You need this enabled if you want your kernel to run on an
|
|
Hygon CPU. Disabling this option on other types of CPUs
|
|
makes the kernel a tiny bit smaller. Disabling it on an Hygon
|
|
CPU might render the kernel unbootable.
|
|
|
|
If unsure, say N.
|
|
|
|
config CPU_SUP_CENTAUR
|
|
default y
|
|
bool "Support Centaur processors" if PROCESSOR_SELECT
|
|
help
|
|
This enables detection, tunings and quirks for Centaur processors
|
|
|
|
You need this enabled if you want your kernel to run on a
|
|
Centaur CPU. Disabling this option on other types of CPUs
|
|
makes the kernel a tiny bit smaller. Disabling it on a Centaur
|
|
CPU might render the kernel unbootable.
|
|
|
|
If unsure, say N.
|
|
|
|
config CPU_SUP_TRANSMETA_32
|
|
default y
|
|
bool "Support Transmeta processors" if PROCESSOR_SELECT
|
|
depends on !64BIT
|
|
help
|
|
This enables detection, tunings and quirks for Transmeta processors
|
|
|
|
You need this enabled if you want your kernel to run on a
|
|
Transmeta CPU. Disabling this option on other types of CPUs
|
|
makes the kernel a tiny bit smaller. Disabling it on a Transmeta
|
|
CPU might render the kernel unbootable.
|
|
|
|
If unsure, say N.
|
|
|
|
config CPU_SUP_UMC_32
|
|
default y
|
|
bool "Support UMC processors" if PROCESSOR_SELECT
|
|
depends on M486SX || M486 || (EXPERT && !64BIT)
|
|
help
|
|
This enables detection, tunings and quirks for UMC processors
|
|
|
|
You need this enabled if you want your kernel to run on a
|
|
UMC CPU. Disabling this option on other types of CPUs
|
|
makes the kernel a tiny bit smaller. Disabling it on a UMC
|
|
CPU might render the kernel unbootable.
|
|
|
|
If unsure, say N.
|
|
|
|
config CPU_SUP_ZHAOXIN
|
|
default y
|
|
bool "Support Zhaoxin processors" if PROCESSOR_SELECT
|
|
help
|
|
This enables detection, tunings and quirks for Zhaoxin processors
|
|
|
|
You need this enabled if you want your kernel to run on a
|
|
Zhaoxin CPU. Disabling this option on other types of CPUs
|
|
makes the kernel a tiny bit smaller. Disabling it on a Zhaoxin
|
|
CPU might render the kernel unbootable.
|
|
|
|
If unsure, say N.
|
|
|
|
config CPU_SUP_VORTEX_32
|
|
default y
|
|
bool "Support Vortex processors" if PROCESSOR_SELECT
|
|
depends on X86_32
|
|
help
|
|
This enables detection, tunings and quirks for Vortex processors
|
|
|
|
You need this enabled if you want your kernel to run on a
|
|
Vortex CPU. Disabling this option on other types of CPUs
|
|
makes the kernel a tiny bit smaller.
|
|
|
|
If unsure, say N.
|