571 lines
15 KiB
C
571 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* HyperV Detection code.
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*
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* Copyright (C) 2010, Novell, Inc.
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* Author : K. Y. Srinivasan <ksrinivasan@novell.com>
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*/
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#include <linux/types.h>
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#include <linux/time.h>
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#include <linux/clocksource.h>
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#include <linux/init.h>
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#include <linux/export.h>
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#include <linux/hardirq.h>
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#include <linux/efi.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kexec.h>
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#include <linux/i8253.h>
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#include <linux/random.h>
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#include <asm/processor.h>
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#include <asm/hypervisor.h>
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#include <asm/hyperv-tlfs.h>
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#include <asm/mshyperv.h>
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#include <asm/desc.h>
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#include <asm/idtentry.h>
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#include <asm/irq_regs.h>
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#include <asm/i8259.h>
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#include <asm/apic.h>
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#include <asm/timer.h>
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#include <asm/reboot.h>
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#include <asm/nmi.h>
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#include <clocksource/hyperv_timer.h>
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#include <asm/numa.h>
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/* Is Linux running as the root partition? */
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bool hv_root_partition;
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/* Is Linux running on nested Microsoft Hypervisor */
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bool hv_nested;
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struct ms_hyperv_info ms_hyperv;
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#if IS_ENABLED(CONFIG_HYPERV)
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static inline unsigned int hv_get_nested_reg(unsigned int reg)
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{
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if (hv_is_sint_reg(reg))
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return reg - HV_REGISTER_SINT0 + HV_REGISTER_NESTED_SINT0;
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switch (reg) {
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case HV_REGISTER_SIMP:
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return HV_REGISTER_NESTED_SIMP;
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case HV_REGISTER_SIEFP:
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return HV_REGISTER_NESTED_SIEFP;
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case HV_REGISTER_SVERSION:
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return HV_REGISTER_NESTED_SVERSION;
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case HV_REGISTER_SCONTROL:
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return HV_REGISTER_NESTED_SCONTROL;
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case HV_REGISTER_EOM:
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return HV_REGISTER_NESTED_EOM;
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default:
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return reg;
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}
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}
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u64 hv_get_non_nested_register(unsigned int reg)
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{
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u64 value;
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if (hv_is_synic_reg(reg) && hv_isolation_type_snp())
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hv_ghcb_msr_read(reg, &value);
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else
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rdmsrl(reg, value);
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return value;
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}
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EXPORT_SYMBOL_GPL(hv_get_non_nested_register);
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void hv_set_non_nested_register(unsigned int reg, u64 value)
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{
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if (hv_is_synic_reg(reg) && hv_isolation_type_snp()) {
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hv_ghcb_msr_write(reg, value);
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/* Write proxy bit via wrmsl instruction */
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if (hv_is_sint_reg(reg))
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wrmsrl(reg, value | 1 << 20);
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} else {
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wrmsrl(reg, value);
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}
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}
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EXPORT_SYMBOL_GPL(hv_set_non_nested_register);
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u64 hv_get_register(unsigned int reg)
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{
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if (hv_nested)
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reg = hv_get_nested_reg(reg);
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return hv_get_non_nested_register(reg);
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}
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EXPORT_SYMBOL_GPL(hv_get_register);
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void hv_set_register(unsigned int reg, u64 value)
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{
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if (hv_nested)
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reg = hv_get_nested_reg(reg);
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hv_set_non_nested_register(reg, value);
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}
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EXPORT_SYMBOL_GPL(hv_set_register);
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static void (*vmbus_handler)(void);
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static void (*hv_stimer0_handler)(void);
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static void (*hv_kexec_handler)(void);
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static void (*hv_crash_handler)(struct pt_regs *regs);
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DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_callback)
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{
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struct pt_regs *old_regs = set_irq_regs(regs);
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inc_irq_stat(irq_hv_callback_count);
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if (vmbus_handler)
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vmbus_handler();
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if (ms_hyperv.hints & HV_DEPRECATING_AEOI_RECOMMENDED)
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ack_APIC_irq();
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set_irq_regs(old_regs);
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}
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void hv_setup_vmbus_handler(void (*handler)(void))
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{
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vmbus_handler = handler;
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}
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void hv_remove_vmbus_handler(void)
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{
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/* We have no way to deallocate the interrupt gate */
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vmbus_handler = NULL;
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}
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/*
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* Routines to do per-architecture handling of stimer0
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* interrupts when in Direct Mode
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*/
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DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_stimer0)
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{
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struct pt_regs *old_regs = set_irq_regs(regs);
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inc_irq_stat(hyperv_stimer0_count);
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if (hv_stimer0_handler)
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hv_stimer0_handler();
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add_interrupt_randomness(HYPERV_STIMER0_VECTOR);
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ack_APIC_irq();
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set_irq_regs(old_regs);
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}
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/* For x86/x64, override weak placeholders in hyperv_timer.c */
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void hv_setup_stimer0_handler(void (*handler)(void))
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{
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hv_stimer0_handler = handler;
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}
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void hv_remove_stimer0_handler(void)
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{
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/* We have no way to deallocate the interrupt gate */
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hv_stimer0_handler = NULL;
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}
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void hv_setup_kexec_handler(void (*handler)(void))
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{
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hv_kexec_handler = handler;
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}
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void hv_remove_kexec_handler(void)
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{
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hv_kexec_handler = NULL;
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}
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void hv_setup_crash_handler(void (*handler)(struct pt_regs *regs))
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{
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hv_crash_handler = handler;
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}
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void hv_remove_crash_handler(void)
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{
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hv_crash_handler = NULL;
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}
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#ifdef CONFIG_KEXEC_CORE
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static void hv_machine_shutdown(void)
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{
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if (kexec_in_progress && hv_kexec_handler)
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hv_kexec_handler();
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/*
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* Call hv_cpu_die() on all the CPUs, otherwise later the hypervisor
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* corrupts the old VP Assist Pages and can crash the kexec kernel.
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*/
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if (kexec_in_progress && hyperv_init_cpuhp > 0)
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cpuhp_remove_state(hyperv_init_cpuhp);
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/* The function calls stop_other_cpus(). */
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native_machine_shutdown();
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/* Disable the hypercall page when there is only 1 active CPU. */
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if (kexec_in_progress)
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hyperv_cleanup();
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}
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static void hv_machine_crash_shutdown(struct pt_regs *regs)
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{
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if (hv_crash_handler)
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hv_crash_handler(regs);
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/* The function calls crash_smp_send_stop(). */
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native_machine_crash_shutdown(regs);
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/* Disable the hypercall page when there is only 1 active CPU. */
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hyperv_cleanup();
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}
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#endif /* CONFIG_KEXEC_CORE */
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#endif /* CONFIG_HYPERV */
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static uint32_t __init ms_hyperv_platform(void)
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{
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u32 eax;
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u32 hyp_signature[3];
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if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
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return 0;
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cpuid(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS,
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&eax, &hyp_signature[0], &hyp_signature[1], &hyp_signature[2]);
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if (eax < HYPERV_CPUID_MIN || eax > HYPERV_CPUID_MAX ||
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memcmp("Microsoft Hv", hyp_signature, 12))
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return 0;
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/* HYPERCALL and VP_INDEX MSRs are mandatory for all features. */
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eax = cpuid_eax(HYPERV_CPUID_FEATURES);
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if (!(eax & HV_MSR_HYPERCALL_AVAILABLE)) {
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pr_warn("x86/hyperv: HYPERCALL MSR not available.\n");
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return 0;
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}
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if (!(eax & HV_MSR_VP_INDEX_AVAILABLE)) {
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pr_warn("x86/hyperv: VP_INDEX MSR not available.\n");
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return 0;
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}
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return HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
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}
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#ifdef CONFIG_X86_LOCAL_APIC
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/*
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* Prior to WS2016 Debug-VM sends NMIs to all CPUs which makes
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* it difficult to process CHANNELMSG_UNLOAD in case of crash. Handle
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* unknown NMI on the first CPU which gets it.
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*/
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static int hv_nmi_unknown(unsigned int val, struct pt_regs *regs)
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{
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static atomic_t nmi_cpu = ATOMIC_INIT(-1);
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if (!unknown_nmi_panic)
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return NMI_DONE;
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if (atomic_cmpxchg(&nmi_cpu, -1, raw_smp_processor_id()) != -1)
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return NMI_HANDLED;
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return NMI_DONE;
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}
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#endif
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static unsigned long hv_get_tsc_khz(void)
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{
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unsigned long freq;
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rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq);
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return freq / 1000;
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}
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#if defined(CONFIG_SMP) && IS_ENABLED(CONFIG_HYPERV)
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static void __init hv_smp_prepare_boot_cpu(void)
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{
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native_smp_prepare_boot_cpu();
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#if defined(CONFIG_X86_64) && defined(CONFIG_PARAVIRT_SPINLOCKS)
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hv_init_spinlocks();
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#endif
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}
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static void __init hv_smp_prepare_cpus(unsigned int max_cpus)
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{
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#ifdef CONFIG_X86_64
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int i;
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int ret;
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#endif
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native_smp_prepare_cpus(max_cpus);
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#ifdef CONFIG_X86_64
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for_each_present_cpu(i) {
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if (i == 0)
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continue;
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ret = hv_call_add_logical_proc(numa_cpu_node(i), i, cpu_physical_id(i));
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BUG_ON(ret);
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}
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for_each_present_cpu(i) {
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if (i == 0)
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continue;
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ret = hv_call_create_vp(numa_cpu_node(i), hv_current_partition_id, i, i);
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BUG_ON(ret);
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}
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#endif
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}
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#endif
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static void __init ms_hyperv_init_platform(void)
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{
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int hv_max_functions_eax;
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int hv_host_info_eax;
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int hv_host_info_ebx;
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int hv_host_info_ecx;
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int hv_host_info_edx;
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#ifdef CONFIG_PARAVIRT
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pv_info.name = "Hyper-V";
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#endif
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/*
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* Extract the features and hints
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*/
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ms_hyperv.features = cpuid_eax(HYPERV_CPUID_FEATURES);
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ms_hyperv.priv_high = cpuid_ebx(HYPERV_CPUID_FEATURES);
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ms_hyperv.misc_features = cpuid_edx(HYPERV_CPUID_FEATURES);
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ms_hyperv.hints = cpuid_eax(HYPERV_CPUID_ENLIGHTMENT_INFO);
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hv_max_functions_eax = cpuid_eax(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS);
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pr_info("Hyper-V: privilege flags low 0x%x, high 0x%x, hints 0x%x, misc 0x%x\n",
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ms_hyperv.features, ms_hyperv.priv_high, ms_hyperv.hints,
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ms_hyperv.misc_features);
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ms_hyperv.max_vp_index = cpuid_eax(HYPERV_CPUID_IMPLEMENT_LIMITS);
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ms_hyperv.max_lp_index = cpuid_ebx(HYPERV_CPUID_IMPLEMENT_LIMITS);
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pr_debug("Hyper-V: max %u virtual processors, %u logical processors\n",
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ms_hyperv.max_vp_index, ms_hyperv.max_lp_index);
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/*
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* Check CPU management privilege.
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*
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* To mirror what Windows does we should extract CPU management
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* features and use the ReservedIdentityBit to detect if Linux is the
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* root partition. But that requires negotiating CPU management
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* interface (a process to be finalized). For now, use the privilege
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* flag as the indicator for running as root.
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*
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* Hyper-V should never specify running as root and as a Confidential
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* VM. But to protect against a compromised/malicious Hyper-V trying
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* to exploit root behavior to expose Confidential VM memory, ignore
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* the root partition setting if also a Confidential VM.
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*/
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if ((ms_hyperv.priv_high & HV_CPU_MANAGEMENT) &&
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!(ms_hyperv.priv_high & HV_ISOLATION)) {
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hv_root_partition = true;
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pr_info("Hyper-V: running as root partition\n");
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}
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if (ms_hyperv.hints & HV_X64_HYPERV_NESTED) {
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hv_nested = true;
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pr_info("Hyper-V: running on a nested hypervisor\n");
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}
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/*
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* Extract host information.
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*/
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if (hv_max_functions_eax >= HYPERV_CPUID_VERSION) {
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hv_host_info_eax = cpuid_eax(HYPERV_CPUID_VERSION);
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hv_host_info_ebx = cpuid_ebx(HYPERV_CPUID_VERSION);
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hv_host_info_ecx = cpuid_ecx(HYPERV_CPUID_VERSION);
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hv_host_info_edx = cpuid_edx(HYPERV_CPUID_VERSION);
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pr_info("Hyper-V: Host Build %d.%d.%d.%d-%d-%d\n",
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hv_host_info_ebx >> 16, hv_host_info_ebx & 0xFFFF,
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hv_host_info_eax, hv_host_info_edx & 0xFFFFFF,
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hv_host_info_ecx, hv_host_info_edx >> 24);
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}
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if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS &&
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ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) {
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x86_platform.calibrate_tsc = hv_get_tsc_khz;
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x86_platform.calibrate_cpu = hv_get_tsc_khz;
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}
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if (ms_hyperv.priv_high & HV_ISOLATION) {
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ms_hyperv.isolation_config_a = cpuid_eax(HYPERV_CPUID_ISOLATION_CONFIG);
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ms_hyperv.isolation_config_b = cpuid_ebx(HYPERV_CPUID_ISOLATION_CONFIG);
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if (ms_hyperv.shared_gpa_boundary_active)
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ms_hyperv.shared_gpa_boundary =
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BIT_ULL(ms_hyperv.shared_gpa_boundary_bits);
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pr_info("Hyper-V: Isolation Config: Group A 0x%x, Group B 0x%x\n",
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ms_hyperv.isolation_config_a, ms_hyperv.isolation_config_b);
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if (hv_get_isolation_type() == HV_ISOLATION_TYPE_SNP)
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static_branch_enable(&isolation_type_snp);
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}
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if (hv_max_functions_eax >= HYPERV_CPUID_NESTED_FEATURES) {
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ms_hyperv.nested_features =
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cpuid_eax(HYPERV_CPUID_NESTED_FEATURES);
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pr_info("Hyper-V: Nested features: 0x%x\n",
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ms_hyperv.nested_features);
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}
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#ifdef CONFIG_X86_LOCAL_APIC
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if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS &&
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ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) {
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/*
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* Get the APIC frequency.
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*/
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u64 hv_lapic_frequency;
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rdmsrl(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency);
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hv_lapic_frequency = div_u64(hv_lapic_frequency, HZ);
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lapic_timer_period = hv_lapic_frequency;
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pr_info("Hyper-V: LAPIC Timer Frequency: %#x\n",
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lapic_timer_period);
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}
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register_nmi_handler(NMI_UNKNOWN, hv_nmi_unknown, NMI_FLAG_FIRST,
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"hv_nmi_unknown");
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#endif
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#ifdef CONFIG_X86_IO_APIC
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no_timer_check = 1;
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#endif
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#if IS_ENABLED(CONFIG_HYPERV) && defined(CONFIG_KEXEC_CORE)
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machine_ops.shutdown = hv_machine_shutdown;
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machine_ops.crash_shutdown = hv_machine_crash_shutdown;
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#endif
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if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) {
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/*
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* Writing to synthetic MSR 0x40000118 updates/changes the
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* guest visible CPUIDs. Setting bit 0 of this MSR enables
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* guests to report invariant TSC feature through CPUID
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* instruction, CPUID 0x800000007/EDX, bit 8. See code in
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* early_init_intel() where this bit is examined. The
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* setting of this MSR bit should happen before init_intel()
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* is called.
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*/
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wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, HV_EXPOSE_INVARIANT_TSC);
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setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
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}
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/*
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* Generation 2 instances don't support reading the NMI status from
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* 0x61 port.
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*/
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if (efi_enabled(EFI_BOOT))
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x86_platform.get_nmi_reason = hv_get_nmi_reason;
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/*
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* Hyper-V VMs have a PIT emulation quirk such that zeroing the
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* counter register during PIT shutdown restarts the PIT. So it
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* continues to interrupt @18.2 HZ. Setting i8253_clear_counter
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* to false tells pit_shutdown() not to zero the counter so that
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* the PIT really is shutdown. Generation 2 VMs don't have a PIT,
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* and setting this value has no effect.
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*/
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i8253_clear_counter_on_shutdown = false;
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#if IS_ENABLED(CONFIG_HYPERV)
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if ((hv_get_isolation_type() == HV_ISOLATION_TYPE_VBS) ||
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(hv_get_isolation_type() == HV_ISOLATION_TYPE_SNP))
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hv_vtom_init();
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/*
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* Setup the hook to get control post apic initialization.
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*/
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x86_platform.apic_post_init = hyperv_init;
|
|
hyperv_setup_mmu_ops();
|
|
/* Setup the IDT for hypervisor callback */
|
|
alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, asm_sysvec_hyperv_callback);
|
|
|
|
/* Setup the IDT for reenlightenment notifications */
|
|
if (ms_hyperv.features & HV_ACCESS_REENLIGHTENMENT) {
|
|
alloc_intr_gate(HYPERV_REENLIGHTENMENT_VECTOR,
|
|
asm_sysvec_hyperv_reenlightenment);
|
|
}
|
|
|
|
/* Setup the IDT for stimer0 */
|
|
if (ms_hyperv.misc_features & HV_STIMER_DIRECT_MODE_AVAILABLE) {
|
|
alloc_intr_gate(HYPERV_STIMER0_VECTOR,
|
|
asm_sysvec_hyperv_stimer0);
|
|
}
|
|
|
|
# ifdef CONFIG_SMP
|
|
smp_ops.smp_prepare_boot_cpu = hv_smp_prepare_boot_cpu;
|
|
if (hv_root_partition)
|
|
smp_ops.smp_prepare_cpus = hv_smp_prepare_cpus;
|
|
# endif
|
|
|
|
/*
|
|
* Hyper-V doesn't provide irq remapping for IO-APIC. To enable x2apic,
|
|
* set x2apic destination mode to physical mode when x2apic is available
|
|
* and Hyper-V IOMMU driver makes sure cpus assigned with IO-APIC irqs
|
|
* have 8-bit APIC id.
|
|
*/
|
|
# ifdef CONFIG_X86_X2APIC
|
|
if (x2apic_supported())
|
|
x2apic_phys = 1;
|
|
# endif
|
|
|
|
/* Register Hyper-V specific clocksource */
|
|
hv_init_clocksource();
|
|
hv_vtl_init_platform();
|
|
#endif
|
|
/*
|
|
* TSC should be marked as unstable only after Hyper-V
|
|
* clocksource has been initialized. This ensures that the
|
|
* stability of the sched_clock is not altered.
|
|
*/
|
|
if (!(ms_hyperv.features & HV_ACCESS_TSC_INVARIANT))
|
|
mark_tsc_unstable("running on Hyper-V");
|
|
|
|
hardlockup_detector_disable();
|
|
}
|
|
|
|
static bool __init ms_hyperv_x2apic_available(void)
|
|
{
|
|
return x2apic_supported();
|
|
}
|
|
|
|
/*
|
|
* If ms_hyperv_msi_ext_dest_id() returns true, hyperv_prepare_irq_remapping()
|
|
* returns -ENODEV and the Hyper-V IOMMU driver is not used; instead, the
|
|
* generic support of the 15-bit APIC ID is used: see __irq_msi_compose_msg().
|
|
*
|
|
* Note: for a VM on Hyper-V, the I/O-APIC is the only device which
|
|
* (logically) generates MSIs directly to the system APIC irq domain.
|
|
* There is no HPET, and PCI MSI/MSI-X interrupts are remapped by the
|
|
* pci-hyperv host bridge.
|
|
*
|
|
* Note: for a Hyper-V root partition, this will always return false.
|
|
* The hypervisor doesn't expose these HYPERV_CPUID_VIRT_STACK_* cpuids by
|
|
* default, they are implemented as intercepts by the Windows Hyper-V stack.
|
|
* Even a nested root partition (L2 root) will not get them because the
|
|
* nested (L1) hypervisor filters them out.
|
|
*/
|
|
static bool __init ms_hyperv_msi_ext_dest_id(void)
|
|
{
|
|
u32 eax;
|
|
|
|
eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_INTERFACE);
|
|
if (eax != HYPERV_VS_INTERFACE_EAX_SIGNATURE)
|
|
return false;
|
|
|
|
eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_PROPERTIES);
|
|
return eax & HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE;
|
|
}
|
|
|
|
const __initconst struct hypervisor_x86 x86_hyper_ms_hyperv = {
|
|
.name = "Microsoft Hyper-V",
|
|
.detect = ms_hyperv_platform,
|
|
.type = X86_HYPER_MS_HYPERV,
|
|
.init.x2apic_available = ms_hyperv_x2apic_available,
|
|
.init.msi_ext_dest_id = ms_hyperv_msi_ext_dest_id,
|
|
.init.init_platform = ms_hyperv_init_platform,
|
|
};
|