927 lines
24 KiB
C
927 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 1995 Linus Torvalds
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*
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* Pentium III FXSR, SSE support
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* Gareth Hughes <gareth@valinux.com>, May 2000
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*
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* X86-64 port
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* Andi Kleen.
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*
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* CPU hotplug support - ashok.raj@intel.com
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*/
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/*
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* This file handles the architecture-dependent parts of process handling..
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*/
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#include <linux/cpu.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/sched/task.h>
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#include <linux/sched/task_stack.h>
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#include <linux/fs.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/elfcore.h>
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#include <linux/smp.h>
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#include <linux/slab.h>
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#include <linux/user.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/ptrace.h>
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#include <linux/notifier.h>
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#include <linux/kprobes.h>
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#include <linux/kdebug.h>
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#include <linux/prctl.h>
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#include <linux/uaccess.h>
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#include <linux/io.h>
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#include <linux/ftrace.h>
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#include <linux/syscalls.h>
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#include <linux/iommu.h>
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#include <asm/processor.h>
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#include <asm/pkru.h>
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#include <asm/fpu/sched.h>
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#include <asm/mmu_context.h>
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#include <asm/prctl.h>
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#include <asm/desc.h>
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#include <asm/proto.h>
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#include <asm/ia32.h>
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#include <asm/debugreg.h>
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#include <asm/switch_to.h>
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#include <asm/xen/hypervisor.h>
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#include <asm/vdso.h>
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#include <asm/resctrl.h>
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#include <asm/unistd.h>
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#include <asm/fsgsbase.h>
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#ifdef CONFIG_IA32_EMULATION
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/* Not included via unistd.h */
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#include <asm/unistd_32_ia32.h>
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#endif
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#include "process.h"
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/* Prints also some state that isn't saved in the pt_regs */
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void __show_regs(struct pt_regs *regs, enum show_regs_mode mode,
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const char *log_lvl)
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{
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unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L, fs, gs, shadowgs;
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unsigned long d0, d1, d2, d3, d6, d7;
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unsigned int fsindex, gsindex;
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unsigned int ds, es;
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show_iret_regs(regs, log_lvl);
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if (regs->orig_ax != -1)
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pr_cont(" ORIG_RAX: %016lx\n", regs->orig_ax);
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else
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pr_cont("\n");
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printk("%sRAX: %016lx RBX: %016lx RCX: %016lx\n",
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log_lvl, regs->ax, regs->bx, regs->cx);
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printk("%sRDX: %016lx RSI: %016lx RDI: %016lx\n",
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log_lvl, regs->dx, regs->si, regs->di);
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printk("%sRBP: %016lx R08: %016lx R09: %016lx\n",
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log_lvl, regs->bp, regs->r8, regs->r9);
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printk("%sR10: %016lx R11: %016lx R12: %016lx\n",
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log_lvl, regs->r10, regs->r11, regs->r12);
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printk("%sR13: %016lx R14: %016lx R15: %016lx\n",
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log_lvl, regs->r13, regs->r14, regs->r15);
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if (mode == SHOW_REGS_SHORT)
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return;
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if (mode == SHOW_REGS_USER) {
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rdmsrl(MSR_FS_BASE, fs);
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rdmsrl(MSR_KERNEL_GS_BASE, shadowgs);
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printk("%sFS: %016lx GS: %016lx\n",
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log_lvl, fs, shadowgs);
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return;
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}
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asm("movl %%ds,%0" : "=r" (ds));
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asm("movl %%es,%0" : "=r" (es));
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asm("movl %%fs,%0" : "=r" (fsindex));
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asm("movl %%gs,%0" : "=r" (gsindex));
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rdmsrl(MSR_FS_BASE, fs);
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rdmsrl(MSR_GS_BASE, gs);
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rdmsrl(MSR_KERNEL_GS_BASE, shadowgs);
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cr0 = read_cr0();
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cr2 = read_cr2();
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cr3 = __read_cr3();
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cr4 = __read_cr4();
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printk("%sFS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n",
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log_lvl, fs, fsindex, gs, gsindex, shadowgs);
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printk("%sCS: %04lx DS: %04x ES: %04x CR0: %016lx\n",
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log_lvl, regs->cs, ds, es, cr0);
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printk("%sCR2: %016lx CR3: %016lx CR4: %016lx\n",
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log_lvl, cr2, cr3, cr4);
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get_debugreg(d0, 0);
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get_debugreg(d1, 1);
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get_debugreg(d2, 2);
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get_debugreg(d3, 3);
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get_debugreg(d6, 6);
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get_debugreg(d7, 7);
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/* Only print out debug registers if they are in their non-default state. */
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if (!((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
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(d6 == DR6_RESERVED) && (d7 == 0x400))) {
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printk("%sDR0: %016lx DR1: %016lx DR2: %016lx\n",
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log_lvl, d0, d1, d2);
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printk("%sDR3: %016lx DR6: %016lx DR7: %016lx\n",
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log_lvl, d3, d6, d7);
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}
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if (cpu_feature_enabled(X86_FEATURE_OSPKE))
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printk("%sPKRU: %08x\n", log_lvl, read_pkru());
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}
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void release_thread(struct task_struct *dead_task)
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{
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WARN_ON(dead_task->mm);
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}
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enum which_selector {
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FS,
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GS
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};
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/*
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* Out of line to be protected from kprobes and tracing. If this would be
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* traced or probed than any access to a per CPU variable happens with
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* the wrong GS.
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*
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* It is not used on Xen paravirt. When paravirt support is needed, it
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* needs to be renamed with native_ prefix.
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*/
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static noinstr unsigned long __rdgsbase_inactive(void)
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{
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unsigned long gsbase;
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lockdep_assert_irqs_disabled();
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if (!cpu_feature_enabled(X86_FEATURE_XENPV)) {
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native_swapgs();
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gsbase = rdgsbase();
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native_swapgs();
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} else {
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instrumentation_begin();
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rdmsrl(MSR_KERNEL_GS_BASE, gsbase);
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instrumentation_end();
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}
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return gsbase;
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}
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/*
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* Out of line to be protected from kprobes and tracing. If this would be
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* traced or probed than any access to a per CPU variable happens with
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* the wrong GS.
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*
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* It is not used on Xen paravirt. When paravirt support is needed, it
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* needs to be renamed with native_ prefix.
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*/
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static noinstr void __wrgsbase_inactive(unsigned long gsbase)
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{
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lockdep_assert_irqs_disabled();
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if (!cpu_feature_enabled(X86_FEATURE_XENPV)) {
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native_swapgs();
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wrgsbase(gsbase);
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native_swapgs();
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} else {
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instrumentation_begin();
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wrmsrl(MSR_KERNEL_GS_BASE, gsbase);
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instrumentation_end();
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}
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}
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/*
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* Saves the FS or GS base for an outgoing thread if FSGSBASE extensions are
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* not available. The goal is to be reasonably fast on non-FSGSBASE systems.
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* It's forcibly inlined because it'll generate better code and this function
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* is hot.
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*/
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static __always_inline void save_base_legacy(struct task_struct *prev_p,
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unsigned short selector,
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enum which_selector which)
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{
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if (likely(selector == 0)) {
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/*
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* On Intel (without X86_BUG_NULL_SEG), the segment base could
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* be the pre-existing saved base or it could be zero. On AMD
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* (with X86_BUG_NULL_SEG), the segment base could be almost
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* anything.
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*
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* This branch is very hot (it's hit twice on almost every
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* context switch between 64-bit programs), and avoiding
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* the RDMSR helps a lot, so we just assume that whatever
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* value is already saved is correct. This matches historical
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* Linux behavior, so it won't break existing applications.
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*
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* To avoid leaking state, on non-X86_BUG_NULL_SEG CPUs, if we
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* report that the base is zero, it needs to actually be zero:
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* see the corresponding logic in load_seg_legacy.
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*/
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} else {
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/*
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* If the selector is 1, 2, or 3, then the base is zero on
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* !X86_BUG_NULL_SEG CPUs and could be anything on
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* X86_BUG_NULL_SEG CPUs. In the latter case, Linux
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* has never attempted to preserve the base across context
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* switches.
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*
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* If selector > 3, then it refers to a real segment, and
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* saving the base isn't necessary.
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*/
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if (which == FS)
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prev_p->thread.fsbase = 0;
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else
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prev_p->thread.gsbase = 0;
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}
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}
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static __always_inline void save_fsgs(struct task_struct *task)
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{
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savesegment(fs, task->thread.fsindex);
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savesegment(gs, task->thread.gsindex);
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if (static_cpu_has(X86_FEATURE_FSGSBASE)) {
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/*
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* If FSGSBASE is enabled, we can't make any useful guesses
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* about the base, and user code expects us to save the current
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* value. Fortunately, reading the base directly is efficient.
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*/
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task->thread.fsbase = rdfsbase();
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task->thread.gsbase = __rdgsbase_inactive();
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} else {
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save_base_legacy(task, task->thread.fsindex, FS);
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save_base_legacy(task, task->thread.gsindex, GS);
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}
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}
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/*
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* While a process is running,current->thread.fsbase and current->thread.gsbase
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* may not match the corresponding CPU registers (see save_base_legacy()).
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*/
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void current_save_fsgs(void)
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{
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unsigned long flags;
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/* Interrupts need to be off for FSGSBASE */
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local_irq_save(flags);
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save_fsgs(current);
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local_irq_restore(flags);
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}
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#if IS_ENABLED(CONFIG_KVM)
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EXPORT_SYMBOL_GPL(current_save_fsgs);
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#endif
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static __always_inline void loadseg(enum which_selector which,
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unsigned short sel)
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{
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if (which == FS)
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loadsegment(fs, sel);
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else
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load_gs_index(sel);
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}
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static __always_inline void load_seg_legacy(unsigned short prev_index,
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unsigned long prev_base,
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unsigned short next_index,
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unsigned long next_base,
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enum which_selector which)
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{
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if (likely(next_index <= 3)) {
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/*
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* The next task is using 64-bit TLS, is not using this
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* segment at all, or is having fun with arcane CPU features.
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*/
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if (next_base == 0) {
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/*
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* Nasty case: on AMD CPUs, we need to forcibly zero
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* the base.
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*/
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if (static_cpu_has_bug(X86_BUG_NULL_SEG)) {
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loadseg(which, __USER_DS);
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loadseg(which, next_index);
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} else {
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/*
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* We could try to exhaustively detect cases
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* under which we can skip the segment load,
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* but there's really only one case that matters
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* for performance: if both the previous and
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* next states are fully zeroed, we can skip
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* the load.
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*
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* (This assumes that prev_base == 0 has no
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* false positives. This is the case on
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* Intel-style CPUs.)
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*/
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if (likely(prev_index | next_index | prev_base))
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loadseg(which, next_index);
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}
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} else {
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if (prev_index != next_index)
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loadseg(which, next_index);
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wrmsrl(which == FS ? MSR_FS_BASE : MSR_KERNEL_GS_BASE,
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next_base);
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}
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} else {
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/*
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* The next task is using a real segment. Loading the selector
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* is sufficient.
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*/
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loadseg(which, next_index);
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}
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}
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/*
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* Store prev's PKRU value and load next's PKRU value if they differ. PKRU
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* is not XSTATE managed on context switch because that would require a
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* lookup in the task's FPU xsave buffer and require to keep that updated
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* in various places.
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*/
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static __always_inline void x86_pkru_load(struct thread_struct *prev,
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struct thread_struct *next)
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{
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if (!cpu_feature_enabled(X86_FEATURE_OSPKE))
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return;
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/* Stash the prev task's value: */
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prev->pkru = rdpkru();
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/*
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* PKRU writes are slightly expensive. Avoid them when not
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* strictly necessary:
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*/
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if (prev->pkru != next->pkru)
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wrpkru(next->pkru);
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}
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static __always_inline void x86_fsgsbase_load(struct thread_struct *prev,
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struct thread_struct *next)
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{
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if (static_cpu_has(X86_FEATURE_FSGSBASE)) {
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/* Update the FS and GS selectors if they could have changed. */
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if (unlikely(prev->fsindex || next->fsindex))
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loadseg(FS, next->fsindex);
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if (unlikely(prev->gsindex || next->gsindex))
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loadseg(GS, next->gsindex);
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/* Update the bases. */
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wrfsbase(next->fsbase);
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__wrgsbase_inactive(next->gsbase);
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} else {
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load_seg_legacy(prev->fsindex, prev->fsbase,
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next->fsindex, next->fsbase, FS);
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load_seg_legacy(prev->gsindex, prev->gsbase,
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next->gsindex, next->gsbase, GS);
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}
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}
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unsigned long x86_fsgsbase_read_task(struct task_struct *task,
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unsigned short selector)
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{
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unsigned short idx = selector >> 3;
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unsigned long base;
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if (likely((selector & SEGMENT_TI_MASK) == 0)) {
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if (unlikely(idx >= GDT_ENTRIES))
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return 0;
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/*
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* There are no user segments in the GDT with nonzero bases
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* other than the TLS segments.
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*/
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if (idx < GDT_ENTRY_TLS_MIN || idx > GDT_ENTRY_TLS_MAX)
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return 0;
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idx -= GDT_ENTRY_TLS_MIN;
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base = get_desc_base(&task->thread.tls_array[idx]);
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} else {
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#ifdef CONFIG_MODIFY_LDT_SYSCALL
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struct ldt_struct *ldt;
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/*
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* If performance here mattered, we could protect the LDT
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* with RCU. This is a slow path, though, so we can just
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* take the mutex.
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*/
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mutex_lock(&task->mm->context.lock);
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ldt = task->mm->context.ldt;
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if (unlikely(!ldt || idx >= ldt->nr_entries))
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base = 0;
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else
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base = get_desc_base(ldt->entries + idx);
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mutex_unlock(&task->mm->context.lock);
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#else
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base = 0;
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#endif
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}
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return base;
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}
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unsigned long x86_gsbase_read_cpu_inactive(void)
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{
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unsigned long gsbase;
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if (boot_cpu_has(X86_FEATURE_FSGSBASE)) {
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unsigned long flags;
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local_irq_save(flags);
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gsbase = __rdgsbase_inactive();
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local_irq_restore(flags);
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} else {
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rdmsrl(MSR_KERNEL_GS_BASE, gsbase);
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}
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return gsbase;
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}
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void x86_gsbase_write_cpu_inactive(unsigned long gsbase)
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{
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if (boot_cpu_has(X86_FEATURE_FSGSBASE)) {
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unsigned long flags;
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local_irq_save(flags);
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__wrgsbase_inactive(gsbase);
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local_irq_restore(flags);
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} else {
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wrmsrl(MSR_KERNEL_GS_BASE, gsbase);
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}
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}
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unsigned long x86_fsbase_read_task(struct task_struct *task)
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{
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unsigned long fsbase;
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if (task == current)
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fsbase = x86_fsbase_read_cpu();
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else if (boot_cpu_has(X86_FEATURE_FSGSBASE) ||
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(task->thread.fsindex == 0))
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fsbase = task->thread.fsbase;
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else
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fsbase = x86_fsgsbase_read_task(task, task->thread.fsindex);
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return fsbase;
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}
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unsigned long x86_gsbase_read_task(struct task_struct *task)
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{
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unsigned long gsbase;
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if (task == current)
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gsbase = x86_gsbase_read_cpu_inactive();
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else if (boot_cpu_has(X86_FEATURE_FSGSBASE) ||
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(task->thread.gsindex == 0))
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gsbase = task->thread.gsbase;
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else
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gsbase = x86_fsgsbase_read_task(task, task->thread.gsindex);
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return gsbase;
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}
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void x86_fsbase_write_task(struct task_struct *task, unsigned long fsbase)
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{
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WARN_ON_ONCE(task == current);
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task->thread.fsbase = fsbase;
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}
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void x86_gsbase_write_task(struct task_struct *task, unsigned long gsbase)
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{
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WARN_ON_ONCE(task == current);
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task->thread.gsbase = gsbase;
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}
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static void
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start_thread_common(struct pt_regs *regs, unsigned long new_ip,
|
|
unsigned long new_sp,
|
|
unsigned int _cs, unsigned int _ss, unsigned int _ds)
|
|
{
|
|
WARN_ON_ONCE(regs != current_pt_regs());
|
|
|
|
if (static_cpu_has(X86_BUG_NULL_SEG)) {
|
|
/* Loading zero below won't clear the base. */
|
|
loadsegment(fs, __USER_DS);
|
|
load_gs_index(__USER_DS);
|
|
}
|
|
|
|
loadsegment(fs, 0);
|
|
loadsegment(es, _ds);
|
|
loadsegment(ds, _ds);
|
|
load_gs_index(0);
|
|
|
|
regs->ip = new_ip;
|
|
regs->sp = new_sp;
|
|
regs->cs = _cs;
|
|
regs->ss = _ss;
|
|
regs->flags = X86_EFLAGS_IF;
|
|
}
|
|
|
|
void
|
|
start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
|
|
{
|
|
start_thread_common(regs, new_ip, new_sp,
|
|
__USER_CS, __USER_DS, 0);
|
|
}
|
|
EXPORT_SYMBOL_GPL(start_thread);
|
|
|
|
#ifdef CONFIG_COMPAT
|
|
void compat_start_thread(struct pt_regs *regs, u32 new_ip, u32 new_sp, bool x32)
|
|
{
|
|
start_thread_common(regs, new_ip, new_sp,
|
|
x32 ? __USER_CS : __USER32_CS,
|
|
__USER_DS, __USER_DS);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* switch_to(x,y) should switch tasks from x to y.
|
|
*
|
|
* This could still be optimized:
|
|
* - fold all the options into a flag word and test it with a single test.
|
|
* - could test fs/gs bitsliced
|
|
*
|
|
* Kprobes not supported here. Set the probe on schedule instead.
|
|
* Function graph tracer not supported too.
|
|
*/
|
|
__no_kmsan_checks
|
|
__visible __notrace_funcgraph struct task_struct *
|
|
__switch_to(struct task_struct *prev_p, struct task_struct *next_p)
|
|
{
|
|
struct thread_struct *prev = &prev_p->thread;
|
|
struct thread_struct *next = &next_p->thread;
|
|
struct fpu *prev_fpu = &prev->fpu;
|
|
int cpu = smp_processor_id();
|
|
|
|
WARN_ON_ONCE(IS_ENABLED(CONFIG_DEBUG_ENTRY) &&
|
|
this_cpu_read(pcpu_hot.hardirq_stack_inuse));
|
|
|
|
if (!test_thread_flag(TIF_NEED_FPU_LOAD))
|
|
switch_fpu_prepare(prev_fpu, cpu);
|
|
|
|
/* We must save %fs and %gs before load_TLS() because
|
|
* %fs and %gs may be cleared by load_TLS().
|
|
*
|
|
* (e.g. xen_load_tls())
|
|
*/
|
|
save_fsgs(prev_p);
|
|
|
|
/*
|
|
* Load TLS before restoring any segments so that segment loads
|
|
* reference the correct GDT entries.
|
|
*/
|
|
load_TLS(next, cpu);
|
|
|
|
/*
|
|
* Leave lazy mode, flushing any hypercalls made here. This
|
|
* must be done after loading TLS entries in the GDT but before
|
|
* loading segments that might reference them.
|
|
*/
|
|
arch_end_context_switch(next_p);
|
|
|
|
/* Switch DS and ES.
|
|
*
|
|
* Reading them only returns the selectors, but writing them (if
|
|
* nonzero) loads the full descriptor from the GDT or LDT. The
|
|
* LDT for next is loaded in switch_mm, and the GDT is loaded
|
|
* above.
|
|
*
|
|
* We therefore need to write new values to the segment
|
|
* registers on every context switch unless both the new and old
|
|
* values are zero.
|
|
*
|
|
* Note that we don't need to do anything for CS and SS, as
|
|
* those are saved and restored as part of pt_regs.
|
|
*/
|
|
savesegment(es, prev->es);
|
|
if (unlikely(next->es | prev->es))
|
|
loadsegment(es, next->es);
|
|
|
|
savesegment(ds, prev->ds);
|
|
if (unlikely(next->ds | prev->ds))
|
|
loadsegment(ds, next->ds);
|
|
|
|
x86_fsgsbase_load(prev, next);
|
|
|
|
x86_pkru_load(prev, next);
|
|
|
|
/*
|
|
* Switch the PDA and FPU contexts.
|
|
*/
|
|
raw_cpu_write(pcpu_hot.current_task, next_p);
|
|
raw_cpu_write(pcpu_hot.top_of_stack, task_top_of_stack(next_p));
|
|
|
|
switch_fpu_finish();
|
|
|
|
/* Reload sp0. */
|
|
update_task_stack(next_p);
|
|
|
|
switch_to_extra(prev_p, next_p);
|
|
|
|
if (static_cpu_has_bug(X86_BUG_SYSRET_SS_ATTRS)) {
|
|
/*
|
|
* AMD CPUs have a misfeature: SYSRET sets the SS selector but
|
|
* does not update the cached descriptor. As a result, if we
|
|
* do SYSRET while SS is NULL, we'll end up in user mode with
|
|
* SS apparently equal to __USER_DS but actually unusable.
|
|
*
|
|
* The straightforward workaround would be to fix it up just
|
|
* before SYSRET, but that would slow down the system call
|
|
* fast paths. Instead, we ensure that SS is never NULL in
|
|
* system call context. We do this by replacing NULL SS
|
|
* selectors at every context switch. SYSCALL sets up a valid
|
|
* SS, so the only way to get NULL is to re-enter the kernel
|
|
* from CPL 3 through an interrupt. Since that can't happen
|
|
* in the same task as a running syscall, we are guaranteed to
|
|
* context switch between every interrupt vector entry and a
|
|
* subsequent SYSRET.
|
|
*
|
|
* We read SS first because SS reads are much faster than
|
|
* writes. Out of caution, we force SS to __KERNEL_DS even if
|
|
* it previously had a different non-NULL value.
|
|
*/
|
|
unsigned short ss_sel;
|
|
savesegment(ss, ss_sel);
|
|
if (ss_sel != __KERNEL_DS)
|
|
loadsegment(ss, __KERNEL_DS);
|
|
}
|
|
|
|
/* Load the Intel cache allocation PQR MSR. */
|
|
resctrl_sched_in(next_p);
|
|
|
|
return prev_p;
|
|
}
|
|
|
|
void set_personality_64bit(void)
|
|
{
|
|
/* inherit personality from parent */
|
|
|
|
/* Make sure to be in 64bit mode */
|
|
clear_thread_flag(TIF_ADDR32);
|
|
/* Pretend that this comes from a 64bit execve */
|
|
task_pt_regs(current)->orig_ax = __NR_execve;
|
|
current_thread_info()->status &= ~TS_COMPAT;
|
|
if (current->mm)
|
|
__set_bit(MM_CONTEXT_HAS_VSYSCALL, ¤t->mm->context.flags);
|
|
|
|
/* TBD: overwrites user setup. Should have two bits.
|
|
But 64bit processes have always behaved this way,
|
|
so it's not too bad. The main problem is just that
|
|
32bit children are affected again. */
|
|
current->personality &= ~READ_IMPLIES_EXEC;
|
|
}
|
|
|
|
static void __set_personality_x32(void)
|
|
{
|
|
#ifdef CONFIG_X86_X32_ABI
|
|
if (current->mm)
|
|
current->mm->context.flags = 0;
|
|
|
|
current->personality &= ~READ_IMPLIES_EXEC;
|
|
/*
|
|
* in_32bit_syscall() uses the presence of the x32 syscall bit
|
|
* flag to determine compat status. The x86 mmap() code relies on
|
|
* the syscall bitness so set x32 syscall bit right here to make
|
|
* in_32bit_syscall() work during exec().
|
|
*
|
|
* Pretend to come from a x32 execve.
|
|
*/
|
|
task_pt_regs(current)->orig_ax = __NR_x32_execve | __X32_SYSCALL_BIT;
|
|
current_thread_info()->status &= ~TS_COMPAT;
|
|
#endif
|
|
}
|
|
|
|
static void __set_personality_ia32(void)
|
|
{
|
|
#ifdef CONFIG_IA32_EMULATION
|
|
if (current->mm) {
|
|
/*
|
|
* uprobes applied to this MM need to know this and
|
|
* cannot use user_64bit_mode() at that time.
|
|
*/
|
|
__set_bit(MM_CONTEXT_UPROBE_IA32, ¤t->mm->context.flags);
|
|
}
|
|
|
|
current->personality |= force_personality32;
|
|
/* Prepare the first "return" to user space */
|
|
task_pt_regs(current)->orig_ax = __NR_ia32_execve;
|
|
current_thread_info()->status |= TS_COMPAT;
|
|
#endif
|
|
}
|
|
|
|
void set_personality_ia32(bool x32)
|
|
{
|
|
/* Make sure to be in 32bit mode */
|
|
set_thread_flag(TIF_ADDR32);
|
|
|
|
if (x32)
|
|
__set_personality_x32();
|
|
else
|
|
__set_personality_ia32();
|
|
}
|
|
EXPORT_SYMBOL_GPL(set_personality_ia32);
|
|
|
|
#ifdef CONFIG_CHECKPOINT_RESTORE
|
|
static long prctl_map_vdso(const struct vdso_image *image, unsigned long addr)
|
|
{
|
|
int ret;
|
|
|
|
ret = map_vdso_once(image, addr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return (long)image->size;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_ADDRESS_MASKING
|
|
|
|
#define LAM_U57_BITS 6
|
|
|
|
static int prctl_enable_tagged_addr(struct mm_struct *mm, unsigned long nr_bits)
|
|
{
|
|
if (!cpu_feature_enabled(X86_FEATURE_LAM))
|
|
return -ENODEV;
|
|
|
|
/* PTRACE_ARCH_PRCTL */
|
|
if (current->mm != mm)
|
|
return -EINVAL;
|
|
|
|
if (mm_valid_pasid(mm) &&
|
|
!test_bit(MM_CONTEXT_FORCE_TAGGED_SVA, &mm->context.flags))
|
|
return -EINVAL;
|
|
|
|
if (mmap_write_lock_killable(mm))
|
|
return -EINTR;
|
|
|
|
if (test_bit(MM_CONTEXT_LOCK_LAM, &mm->context.flags)) {
|
|
mmap_write_unlock(mm);
|
|
return -EBUSY;
|
|
}
|
|
|
|
if (!nr_bits) {
|
|
mmap_write_unlock(mm);
|
|
return -EINVAL;
|
|
} else if (nr_bits <= LAM_U57_BITS) {
|
|
mm->context.lam_cr3_mask = X86_CR3_LAM_U57;
|
|
mm->context.untag_mask = ~GENMASK(62, 57);
|
|
} else {
|
|
mmap_write_unlock(mm);
|
|
return -EINVAL;
|
|
}
|
|
|
|
write_cr3(__read_cr3() | mm->context.lam_cr3_mask);
|
|
set_tlbstate_lam_mode(mm);
|
|
set_bit(MM_CONTEXT_LOCK_LAM, &mm->context.flags);
|
|
|
|
mmap_write_unlock(mm);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
long do_arch_prctl_64(struct task_struct *task, int option, unsigned long arg2)
|
|
{
|
|
int ret = 0;
|
|
|
|
switch (option) {
|
|
case ARCH_SET_GS: {
|
|
if (unlikely(arg2 >= TASK_SIZE_MAX))
|
|
return -EPERM;
|
|
|
|
preempt_disable();
|
|
/*
|
|
* ARCH_SET_GS has always overwritten the index
|
|
* and the base. Zero is the most sensible value
|
|
* to put in the index, and is the only value that
|
|
* makes any sense if FSGSBASE is unavailable.
|
|
*/
|
|
if (task == current) {
|
|
loadseg(GS, 0);
|
|
x86_gsbase_write_cpu_inactive(arg2);
|
|
|
|
/*
|
|
* On non-FSGSBASE systems, save_base_legacy() expects
|
|
* that we also fill in thread.gsbase.
|
|
*/
|
|
task->thread.gsbase = arg2;
|
|
|
|
} else {
|
|
task->thread.gsindex = 0;
|
|
x86_gsbase_write_task(task, arg2);
|
|
}
|
|
preempt_enable();
|
|
break;
|
|
}
|
|
case ARCH_SET_FS: {
|
|
/*
|
|
* Not strictly needed for %fs, but do it for symmetry
|
|
* with %gs
|
|
*/
|
|
if (unlikely(arg2 >= TASK_SIZE_MAX))
|
|
return -EPERM;
|
|
|
|
preempt_disable();
|
|
/*
|
|
* Set the selector to 0 for the same reason
|
|
* as %gs above.
|
|
*/
|
|
if (task == current) {
|
|
loadseg(FS, 0);
|
|
x86_fsbase_write_cpu(arg2);
|
|
|
|
/*
|
|
* On non-FSGSBASE systems, save_base_legacy() expects
|
|
* that we also fill in thread.fsbase.
|
|
*/
|
|
task->thread.fsbase = arg2;
|
|
} else {
|
|
task->thread.fsindex = 0;
|
|
x86_fsbase_write_task(task, arg2);
|
|
}
|
|
preempt_enable();
|
|
break;
|
|
}
|
|
case ARCH_GET_FS: {
|
|
unsigned long base = x86_fsbase_read_task(task);
|
|
|
|
ret = put_user(base, (unsigned long __user *)arg2);
|
|
break;
|
|
}
|
|
case ARCH_GET_GS: {
|
|
unsigned long base = x86_gsbase_read_task(task);
|
|
|
|
ret = put_user(base, (unsigned long __user *)arg2);
|
|
break;
|
|
}
|
|
|
|
#ifdef CONFIG_CHECKPOINT_RESTORE
|
|
# ifdef CONFIG_X86_X32_ABI
|
|
case ARCH_MAP_VDSO_X32:
|
|
return prctl_map_vdso(&vdso_image_x32, arg2);
|
|
# endif
|
|
# if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
|
|
case ARCH_MAP_VDSO_32:
|
|
return prctl_map_vdso(&vdso_image_32, arg2);
|
|
# endif
|
|
case ARCH_MAP_VDSO_64:
|
|
return prctl_map_vdso(&vdso_image_64, arg2);
|
|
#endif
|
|
#ifdef CONFIG_ADDRESS_MASKING
|
|
case ARCH_GET_UNTAG_MASK:
|
|
return put_user(task->mm->context.untag_mask,
|
|
(unsigned long __user *)arg2);
|
|
case ARCH_ENABLE_TAGGED_ADDR:
|
|
return prctl_enable_tagged_addr(task->mm, arg2);
|
|
case ARCH_FORCE_TAGGED_SVA:
|
|
if (current != task)
|
|
return -EINVAL;
|
|
set_bit(MM_CONTEXT_FORCE_TAGGED_SVA, &task->mm->context.flags);
|
|
return 0;
|
|
case ARCH_GET_MAX_TAG_BITS:
|
|
if (!cpu_feature_enabled(X86_FEATURE_LAM))
|
|
return put_user(0, (unsigned long __user *)arg2);
|
|
else
|
|
return put_user(LAM_U57_BITS, (unsigned long __user *)arg2);
|
|
#endif
|
|
default:
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2)
|
|
{
|
|
long ret;
|
|
|
|
ret = do_arch_prctl_64(current, option, arg2);
|
|
if (ret == -EINVAL)
|
|
ret = do_arch_prctl_common(option, arg2);
|
|
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONFIG_IA32_EMULATION
|
|
COMPAT_SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2)
|
|
{
|
|
return do_arch_prctl_common(option, arg2);
|
|
}
|
|
#endif
|
|
|
|
unsigned long KSTK_ESP(struct task_struct *task)
|
|
{
|
|
return task_pt_regs(task)->sp;
|
|
}
|