122 lines
3.3 KiB
C
122 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
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*
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* Baikal-T1 CCU Dividers interface driver
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*/
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#ifndef __CLK_BT1_CCU_DIV_H__
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#define __CLK_BT1_CCU_DIV_H__
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#include <linux/clk-provider.h>
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#include <linux/spinlock.h>
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#include <linux/regmap.h>
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#include <linux/bits.h>
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#include <linux/of.h>
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/*
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* CCU Divider private clock IDs
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* @CCU_SYS_SATA_CLK: CCU SATA internal clock
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* @CCU_SYS_XGMAC_CLK: CCU XGMAC internal clock
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*/
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#define CCU_SYS_SATA_CLK -1
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#define CCU_SYS_XGMAC_CLK -2
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/*
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* CCU Divider private flags
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* @CCU_DIV_BASIC: Basic divider clock required by the kernel as early as
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* possible.
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* @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
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* It can be 0 though, which is functionally the same.
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* @CCU_DIV_SKIP_ONE_TO_THREE: For some reason divider can't be within [1,3].
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* It can be either 0 or greater than 3.
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* @CCU_DIV_LOCK_SHIFTED: Find lock-bit at non-standard position.
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* @CCU_DIV_RESET_DOMAIN: There is a clock domain reset handle.
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*/
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#define CCU_DIV_BASIC BIT(0)
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#define CCU_DIV_SKIP_ONE BIT(1)
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#define CCU_DIV_SKIP_ONE_TO_THREE BIT(2)
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#define CCU_DIV_LOCK_SHIFTED BIT(3)
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#define CCU_DIV_RESET_DOMAIN BIT(4)
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/*
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* enum ccu_div_type - CCU Divider types
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* @CCU_DIV_VAR: Clocks gate with variable divider.
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* @CCU_DIV_GATE: Clocks gate with fixed divider.
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* @CCU_DIV_BUF: Clock gate with no divider.
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* @CCU_DIV_FIXED: Ungateable clock with fixed divider.
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*/
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enum ccu_div_type {
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CCU_DIV_VAR,
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CCU_DIV_GATE,
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CCU_DIV_BUF,
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CCU_DIV_FIXED
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};
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/*
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* struct ccu_div_init_data - CCU Divider initialization data
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* @id: Clocks private identifier.
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* @name: Clocks name.
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* @parent_name: Parent clocks name in a fw node.
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* @base: Divider register base address with respect to the sys_regs base.
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* @sys_regs: Baikal-T1 System Controller registers map.
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* @np: Pointer to the node describing the CCU Dividers.
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* @type: CCU divider type (variable, fixed with and without gate).
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* @width: Divider width if it's variable.
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* @divider: Divider fixed value.
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* @flags: CCU Divider clock flags.
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* @features: CCU Divider private features.
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*/
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struct ccu_div_init_data {
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unsigned int id;
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const char *name;
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const char *parent_name;
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unsigned int base;
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struct regmap *sys_regs;
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struct device_node *np;
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enum ccu_div_type type;
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union {
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unsigned int width;
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unsigned int divider;
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};
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unsigned long flags;
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unsigned long features;
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};
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/*
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* struct ccu_div - CCU Divider descriptor
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* @hw: clk_hw of the divider.
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* @id: Clock private identifier.
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* @reg_ctl: Divider control register base address.
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* @sys_regs: Baikal-T1 System Controller registers map.
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* @lock: Divider state change spin-lock.
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* @mask: Divider field mask.
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* @divider: Divider fixed value.
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* @flags: Divider clock flags.
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* @features: CCU Divider private features.
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*/
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struct ccu_div {
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struct clk_hw hw;
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unsigned int id;
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unsigned int reg_ctl;
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struct regmap *sys_regs;
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spinlock_t lock;
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union {
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u32 mask;
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unsigned int divider;
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};
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unsigned long flags;
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unsigned long features;
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};
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#define to_ccu_div(_hw) container_of(_hw, struct ccu_div, hw)
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static inline struct clk_hw *ccu_div_get_clk_hw(struct ccu_div *div)
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{
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return div ? &div->hw : NULL;
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}
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struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *init);
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void ccu_div_hw_unregister(struct ccu_div *div);
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#endif /* __CLK_BT1_CCU_DIV_H__ */
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