562 lines
14 KiB
C
562 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
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* M (part of the Centrino chipset).
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*
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* Since the original Pentium M, most new Intel CPUs support Enhanced
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* SpeedStep.
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*
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* Despite the "SpeedStep" in the name, this is almost entirely unlike
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* traditional SpeedStep.
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*
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* Modelled on speedstep.c
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*
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* Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <linux/sched.h> /* current */
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#include <linux/delay.h>
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#include <linux/compiler.h>
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#include <linux/gfp.h>
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#include <asm/msr.h>
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#include <asm/processor.h>
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#include <asm/cpufeature.h>
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#include <asm/cpu_device_id.h>
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#define MAINTAINER "linux-pm@vger.kernel.org"
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#define INTEL_MSR_RANGE (0xffff)
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struct cpu_id
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{
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__u8 x86; /* CPU family */
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__u8 x86_model; /* model */
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__u8 x86_stepping; /* stepping */
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};
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enum {
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CPU_BANIAS,
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CPU_DOTHAN_A1,
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CPU_DOTHAN_A2,
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CPU_DOTHAN_B0,
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CPU_MP4HT_D0,
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CPU_MP4HT_E0,
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};
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static const struct cpu_id cpu_ids[] = {
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[CPU_BANIAS] = { 6, 9, 5 },
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[CPU_DOTHAN_A1] = { 6, 13, 1 },
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[CPU_DOTHAN_A2] = { 6, 13, 2 },
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[CPU_DOTHAN_B0] = { 6, 13, 6 },
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[CPU_MP4HT_D0] = {15, 3, 4 },
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[CPU_MP4HT_E0] = {15, 4, 1 },
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};
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#define N_IDS ARRAY_SIZE(cpu_ids)
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struct cpu_model
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{
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const struct cpu_id *cpu_id;
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const char *model_name;
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unsigned max_freq; /* max clock in kHz */
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struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
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};
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static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
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const struct cpu_id *x);
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/* Operating points for current CPU */
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static DEFINE_PER_CPU(struct cpu_model *, centrino_model);
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static DEFINE_PER_CPU(const struct cpu_id *, centrino_cpu);
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static struct cpufreq_driver centrino_driver;
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#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
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/* Computes the correct form for IA32_PERF_CTL MSR for a particular
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frequency/voltage operating point; frequency in MHz, volts in mV.
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This is stored as "driver_data" in the structure. */
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#define OP(mhz, mv) \
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{ \
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.frequency = (mhz) * 1000, \
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.driver_data = (((mhz)/100) << 8) | ((mv - 700) / 16) \
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}
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/*
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* These voltage tables were derived from the Intel Pentium M
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* datasheet, document 25261202.pdf, Table 5. I have verified they
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* are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
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* M.
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*/
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/* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
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static struct cpufreq_frequency_table banias_900[] =
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{
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OP(600, 844),
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OP(800, 988),
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OP(900, 1004),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
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static struct cpufreq_frequency_table banias_1000[] =
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{
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OP(600, 844),
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OP(800, 972),
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OP(900, 988),
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OP(1000, 1004),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
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static struct cpufreq_frequency_table banias_1100[] =
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{
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OP( 600, 956),
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OP( 800, 1020),
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OP( 900, 1100),
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OP(1000, 1164),
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OP(1100, 1180),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
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static struct cpufreq_frequency_table banias_1200[] =
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{
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OP( 600, 956),
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OP( 800, 1004),
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OP( 900, 1020),
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OP(1000, 1100),
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OP(1100, 1164),
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OP(1200, 1180),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Intel Pentium M processor 1.30GHz (Banias) */
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static struct cpufreq_frequency_table banias_1300[] =
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{
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OP( 600, 956),
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OP( 800, 1260),
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OP(1000, 1292),
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OP(1200, 1356),
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OP(1300, 1388),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Intel Pentium M processor 1.40GHz (Banias) */
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static struct cpufreq_frequency_table banias_1400[] =
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{
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OP( 600, 956),
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OP( 800, 1180),
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OP(1000, 1308),
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OP(1200, 1436),
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OP(1400, 1484),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Intel Pentium M processor 1.50GHz (Banias) */
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static struct cpufreq_frequency_table banias_1500[] =
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{
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OP( 600, 956),
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OP( 800, 1116),
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OP(1000, 1228),
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OP(1200, 1356),
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OP(1400, 1452),
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OP(1500, 1484),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Intel Pentium M processor 1.60GHz (Banias) */
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static struct cpufreq_frequency_table banias_1600[] =
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{
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OP( 600, 956),
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OP( 800, 1036),
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OP(1000, 1164),
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OP(1200, 1276),
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OP(1400, 1420),
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OP(1600, 1484),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Intel Pentium M processor 1.70GHz (Banias) */
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static struct cpufreq_frequency_table banias_1700[] =
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{
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OP( 600, 956),
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OP( 800, 1004),
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OP(1000, 1116),
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OP(1200, 1228),
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OP(1400, 1308),
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OP(1700, 1484),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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#undef OP
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#define _BANIAS(cpuid, max, name) \
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{ .cpu_id = cpuid, \
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.model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
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.max_freq = (max)*1000, \
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.op_points = banias_##max, \
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}
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#define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
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/* CPU models, their operating frequency range, and freq/voltage
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operating points */
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static struct cpu_model models[] =
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{
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_BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
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BANIAS(1000),
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BANIAS(1100),
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BANIAS(1200),
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BANIAS(1300),
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BANIAS(1400),
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BANIAS(1500),
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BANIAS(1600),
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BANIAS(1700),
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/* NULL model_name is a wildcard */
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{ &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
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{ &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
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{ &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
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{ &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
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{ &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
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{ NULL, }
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};
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#undef _BANIAS
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#undef BANIAS
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static int centrino_cpu_init_table(struct cpufreq_policy *policy)
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{
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struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
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struct cpu_model *model;
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for(model = models; model->cpu_id != NULL; model++)
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if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
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(model->model_name == NULL ||
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strcmp(cpu->x86_model_id, model->model_name) == 0))
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break;
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if (model->cpu_id == NULL) {
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/* No match at all */
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pr_debug("no support for CPU model \"%s\": "
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"send /proc/cpuinfo to " MAINTAINER "\n",
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cpu->x86_model_id);
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return -ENOENT;
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}
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if (model->op_points == NULL) {
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/* Matched a non-match */
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pr_debug("no table support for CPU model \"%s\"\n",
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cpu->x86_model_id);
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pr_debug("try using the acpi-cpufreq driver\n");
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return -ENOENT;
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}
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per_cpu(centrino_model, policy->cpu) = model;
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pr_debug("found \"%s\": max frequency: %dkHz\n",
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model->model_name, model->max_freq);
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return 0;
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}
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#else
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static inline int centrino_cpu_init_table(struct cpufreq_policy *policy)
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{
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return -ENODEV;
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}
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#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
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static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
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const struct cpu_id *x)
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{
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if ((c->x86 == x->x86) &&
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(c->x86_model == x->x86_model) &&
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(c->x86_stepping == x->x86_stepping))
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return 1;
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return 0;
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}
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/* To be called only after centrino_model is initialized */
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static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
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{
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int i;
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/*
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* Extract clock in kHz from PERF_CTL value
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* for centrino, as some DSDTs are buggy.
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* Ideally, this can be done using the acpi_data structure.
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*/
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if ((per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_BANIAS]) ||
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(per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_A1]) ||
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(per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_B0])) {
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msr = (msr >> 8) & 0xff;
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return msr * 100000;
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}
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if ((!per_cpu(centrino_model, cpu)) ||
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(!per_cpu(centrino_model, cpu)->op_points))
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return 0;
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msr &= 0xffff;
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for (i = 0;
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per_cpu(centrino_model, cpu)->op_points[i].frequency
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!= CPUFREQ_TABLE_END;
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i++) {
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if (msr == per_cpu(centrino_model, cpu)->op_points[i].driver_data)
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return per_cpu(centrino_model, cpu)->
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op_points[i].frequency;
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}
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if (failsafe)
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return per_cpu(centrino_model, cpu)->op_points[i-1].frequency;
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else
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return 0;
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}
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/* Return the current CPU frequency in kHz */
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static unsigned int get_cur_freq(unsigned int cpu)
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{
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unsigned l, h;
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unsigned clock_freq;
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rdmsr_on_cpu(cpu, MSR_IA32_PERF_STATUS, &l, &h);
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clock_freq = extract_clock(l, cpu, 0);
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if (unlikely(clock_freq == 0)) {
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/*
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* On some CPUs, we can see transient MSR values (which are
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* not present in _PSS), while CPU is doing some automatic
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* P-state transition (like TM2). Get the last freq set
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* in PERF_CTL.
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*/
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rdmsr_on_cpu(cpu, MSR_IA32_PERF_CTL, &l, &h);
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clock_freq = extract_clock(l, cpu, 1);
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}
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return clock_freq;
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}
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static int centrino_cpu_init(struct cpufreq_policy *policy)
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{
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struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
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unsigned l, h;
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int i;
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/* Only Intel makes Enhanced Speedstep-capable CPUs */
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if (cpu->x86_vendor != X86_VENDOR_INTEL ||
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!cpu_has(cpu, X86_FEATURE_EST))
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return -ENODEV;
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if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
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centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
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if (policy->cpu != 0)
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return -ENODEV;
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for (i = 0; i < N_IDS; i++)
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if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
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break;
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if (i != N_IDS)
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per_cpu(centrino_cpu, policy->cpu) = &cpu_ids[i];
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if (!per_cpu(centrino_cpu, policy->cpu)) {
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pr_debug("found unsupported CPU with "
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"Enhanced SpeedStep: send /proc/cpuinfo to "
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MAINTAINER "\n");
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return -ENODEV;
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}
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if (centrino_cpu_init_table(policy))
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return -ENODEV;
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/* Check to see if Enhanced SpeedStep is enabled, and try to
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enable it if not. */
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rdmsr(MSR_IA32_MISC_ENABLE, l, h);
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if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
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l |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
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pr_debug("trying to enable Enhanced SpeedStep (%x)\n", l);
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wrmsr(MSR_IA32_MISC_ENABLE, l, h);
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/* check to see if it stuck */
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rdmsr(MSR_IA32_MISC_ENABLE, l, h);
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if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
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pr_info("couldn't enable Enhanced SpeedStep\n");
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return -ENODEV;
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}
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}
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policy->cpuinfo.transition_latency = 10000;
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/* 10uS transition latency */
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policy->freq_table = per_cpu(centrino_model, policy->cpu)->op_points;
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return 0;
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}
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static int centrino_cpu_exit(struct cpufreq_policy *policy)
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{
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unsigned int cpu = policy->cpu;
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if (!per_cpu(centrino_model, cpu))
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return -ENODEV;
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per_cpu(centrino_model, cpu) = NULL;
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return 0;
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}
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/**
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* centrino_target - set a new CPUFreq policy
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* @policy: new policy
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* @index: index of target frequency
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*
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* Sets a new CPUFreq policy.
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*/
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static int centrino_target(struct cpufreq_policy *policy, unsigned int index)
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{
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unsigned int msr, oldmsr = 0, h = 0, cpu = policy->cpu;
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int retval = 0;
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unsigned int j, first_cpu;
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struct cpufreq_frequency_table *op_points;
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cpumask_var_t covered_cpus;
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if (unlikely(!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL)))
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return -ENOMEM;
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if (unlikely(per_cpu(centrino_model, cpu) == NULL)) {
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retval = -ENODEV;
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goto out;
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}
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first_cpu = 1;
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op_points = &per_cpu(centrino_model, cpu)->op_points[index];
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for_each_cpu(j, policy->cpus) {
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int good_cpu;
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/*
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* Support for SMP systems.
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* Make sure we are running on CPU that wants to change freq
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*/
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if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
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good_cpu = cpumask_any_and(policy->cpus,
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cpu_online_mask);
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else
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good_cpu = j;
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if (good_cpu >= nr_cpu_ids) {
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pr_debug("couldn't limit to CPUs in this domain\n");
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retval = -EAGAIN;
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if (first_cpu) {
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/* We haven't started the transition yet. */
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goto out;
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}
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break;
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}
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msr = op_points->driver_data;
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if (first_cpu) {
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rdmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, &oldmsr, &h);
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if (msr == (oldmsr & 0xffff)) {
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pr_debug("no change needed - msr was and needs "
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"to be %x\n", oldmsr);
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retval = 0;
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goto out;
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}
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first_cpu = 0;
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/* all but 16 LSB are reserved, treat them with care */
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oldmsr &= ~0xffff;
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msr &= 0xffff;
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oldmsr |= msr;
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}
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wrmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr, h);
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if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
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break;
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cpumask_set_cpu(j, covered_cpus);
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}
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if (unlikely(retval)) {
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/*
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* We have failed halfway through the frequency change.
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* We have sent callbacks to policy->cpus and
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* MSRs have already been written on coverd_cpus.
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* Best effort undo..
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*/
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for_each_cpu(j, covered_cpus)
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wrmsr_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr, h);
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}
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retval = 0;
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out:
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free_cpumask_var(covered_cpus);
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return retval;
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}
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static struct cpufreq_driver centrino_driver = {
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.name = "centrino", /* should be speedstep-centrino,
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but there's a 16 char limit */
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.init = centrino_cpu_init,
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.exit = centrino_cpu_exit,
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = centrino_target,
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.get = get_cur_freq,
|
|
.attr = cpufreq_generic_attr,
|
|
};
|
|
|
|
/*
|
|
* This doesn't replace the detailed checks above because
|
|
* the generic CPU IDs don't have a way to match for steppings
|
|
* or ASCII model IDs.
|
|
*/
|
|
static const struct x86_cpu_id centrino_ids[] = {
|
|
X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, 9, X86_FEATURE_EST, NULL),
|
|
X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, 13, X86_FEATURE_EST, NULL),
|
|
X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 15, 3, X86_FEATURE_EST, NULL),
|
|
X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 15, 4, X86_FEATURE_EST, NULL),
|
|
{}
|
|
};
|
|
|
|
/**
|
|
* centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
|
|
*
|
|
* Initializes the Enhanced SpeedStep support. Returns -ENODEV on
|
|
* unsupported devices, -ENOENT if there's no voltage table for this
|
|
* particular CPU model, -EINVAL on problems during initiatization,
|
|
* and zero on success.
|
|
*
|
|
* This is quite picky. Not only does the CPU have to advertise the
|
|
* "est" flag in the cpuid capability flags, we look for a specific
|
|
* CPU model and stepping, and we need to have the exact model name in
|
|
* our voltage tables. That is, be paranoid about not releasing
|
|
* someone's valuable magic smoke.
|
|
*/
|
|
static int __init centrino_init(void)
|
|
{
|
|
if (!x86_match_cpu(centrino_ids))
|
|
return -ENODEV;
|
|
return cpufreq_register_driver(¢rino_driver);
|
|
}
|
|
|
|
static void __exit centrino_exit(void)
|
|
{
|
|
cpufreq_unregister_driver(¢rino_driver);
|
|
}
|
|
|
|
MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
|
|
MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
|
|
MODULE_LICENSE ("GPL");
|
|
|
|
late_initcall(centrino_init);
|
|
module_exit(centrino_exit);
|