318 lines
9.6 KiB
C
318 lines
9.6 KiB
C
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
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/* Copyright(c) 2014 - 2020 Intel Corporation */
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#ifndef ADF_ACCEL_DEVICES_H_
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#define ADF_ACCEL_DEVICES_H_
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/list.h>
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#include <linux/io.h>
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#include <linux/ratelimit.h>
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#include "adf_cfg_common.h"
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#include "adf_pfvf_msg.h"
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#define ADF_DH895XCC_DEVICE_NAME "dh895xcc"
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#define ADF_DH895XCCVF_DEVICE_NAME "dh895xccvf"
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#define ADF_C62X_DEVICE_NAME "c6xx"
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#define ADF_C62XVF_DEVICE_NAME "c6xxvf"
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#define ADF_C3XXX_DEVICE_NAME "c3xxx"
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#define ADF_C3XXXVF_DEVICE_NAME "c3xxxvf"
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#define ADF_4XXX_DEVICE_NAME "4xxx"
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#define ADF_4XXX_PCI_DEVICE_ID 0x4940
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#define ADF_4XXXIOV_PCI_DEVICE_ID 0x4941
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#define ADF_401XX_PCI_DEVICE_ID 0x4942
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#define ADF_401XXIOV_PCI_DEVICE_ID 0x4943
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#define ADF_DEVICE_FUSECTL_OFFSET 0x40
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#define ADF_DEVICE_LEGFUSE_OFFSET 0x4C
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#define ADF_DEVICE_FUSECTL_MASK 0x80000000
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#define ADF_PCI_MAX_BARS 3
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#define ADF_DEVICE_NAME_LENGTH 32
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#define ADF_ETR_MAX_RINGS_PER_BANK 16
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#define ADF_MAX_MSIX_VECTOR_NAME 16
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#define ADF_DEVICE_NAME_PREFIX "qat_"
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enum adf_accel_capabilities {
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ADF_ACCEL_CAPABILITIES_NULL = 0,
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ADF_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = 1,
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ADF_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = 2,
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ADF_ACCEL_CAPABILITIES_CIPHER = 4,
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ADF_ACCEL_CAPABILITIES_AUTHENTICATION = 8,
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ADF_ACCEL_CAPABILITIES_COMPRESSION = 32,
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ADF_ACCEL_CAPABILITIES_LZS_COMPRESSION = 64,
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ADF_ACCEL_CAPABILITIES_RANDOM_NUMBER = 128
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};
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struct adf_bar {
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resource_size_t base_addr;
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void __iomem *virt_addr;
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resource_size_t size;
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};
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struct adf_irq {
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bool enabled;
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char name[ADF_MAX_MSIX_VECTOR_NAME];
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};
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struct adf_accel_msix {
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struct adf_irq *irqs;
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u32 num_entries;
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};
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struct adf_accel_pci {
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struct pci_dev *pci_dev;
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struct adf_accel_msix msix_entries;
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struct adf_bar pci_bars[ADF_PCI_MAX_BARS];
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u8 revid;
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u8 sku;
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};
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enum dev_state {
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DEV_DOWN = 0,
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DEV_UP
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};
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enum dev_sku_info {
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DEV_SKU_1 = 0,
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DEV_SKU_2,
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DEV_SKU_3,
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DEV_SKU_4,
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DEV_SKU_VF,
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DEV_SKU_UNKNOWN,
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};
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static inline const char *get_sku_info(enum dev_sku_info info)
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{
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switch (info) {
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case DEV_SKU_1:
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return "SKU1";
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case DEV_SKU_2:
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return "SKU2";
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case DEV_SKU_3:
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return "SKU3";
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case DEV_SKU_4:
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return "SKU4";
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case DEV_SKU_VF:
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return "SKUVF";
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case DEV_SKU_UNKNOWN:
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default:
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break;
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}
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return "Unknown SKU";
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}
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struct adf_hw_device_class {
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const char *name;
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const enum adf_device_type type;
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u32 instances;
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};
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struct arb_info {
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u32 arb_cfg;
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u32 arb_offset;
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u32 wt2sam_offset;
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};
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struct admin_info {
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u32 admin_msg_ur;
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u32 admin_msg_lr;
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u32 mailbox_offset;
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};
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struct adf_hw_csr_ops {
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u64 (*build_csr_ring_base_addr)(dma_addr_t addr, u32 size);
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u32 (*read_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
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u32 ring);
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void (*write_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
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u32 ring, u32 value);
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u32 (*read_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
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u32 ring);
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void (*write_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
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u32 ring, u32 value);
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u32 (*read_csr_e_stat)(void __iomem *csr_base_addr, u32 bank);
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void (*write_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,
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u32 ring, u32 value);
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void (*write_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,
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u32 ring, dma_addr_t addr);
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void (*write_csr_int_flag)(void __iomem *csr_base_addr, u32 bank,
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u32 value);
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void (*write_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);
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void (*write_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank,
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u32 value);
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void (*write_csr_int_col_ctl)(void __iomem *csr_base_addr, u32 bank,
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u32 value);
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void (*write_csr_int_flag_and_col)(void __iomem *csr_base_addr,
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u32 bank, u32 value);
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void (*write_csr_ring_srv_arb_en)(void __iomem *csr_base_addr, u32 bank,
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u32 value);
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};
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struct adf_cfg_device_data;
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struct adf_accel_dev;
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struct adf_etr_data;
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struct adf_etr_ring_data;
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struct adf_pfvf_ops {
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int (*enable_comms)(struct adf_accel_dev *accel_dev);
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u32 (*get_pf2vf_offset)(u32 i);
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u32 (*get_vf2pf_offset)(u32 i);
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void (*enable_vf2pf_interrupts)(void __iomem *pmisc_addr, u32 vf_mask);
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void (*disable_all_vf2pf_interrupts)(void __iomem *pmisc_addr);
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u32 (*disable_pending_vf2pf_interrupts)(void __iomem *pmisc_addr);
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int (*send_msg)(struct adf_accel_dev *accel_dev, struct pfvf_message msg,
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u32 pfvf_offset, struct mutex *csr_lock);
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struct pfvf_message (*recv_msg)(struct adf_accel_dev *accel_dev,
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u32 pfvf_offset, u8 compat_ver);
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};
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struct adf_dc_ops {
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void (*build_deflate_ctx)(void *ctx);
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};
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struct adf_hw_device_data {
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struct adf_hw_device_class *dev_class;
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u32 (*get_accel_mask)(struct adf_hw_device_data *self);
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u32 (*get_ae_mask)(struct adf_hw_device_data *self);
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u32 (*get_accel_cap)(struct adf_accel_dev *accel_dev);
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u32 (*get_sram_bar_id)(struct adf_hw_device_data *self);
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u32 (*get_misc_bar_id)(struct adf_hw_device_data *self);
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u32 (*get_etr_bar_id)(struct adf_hw_device_data *self);
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u32 (*get_num_aes)(struct adf_hw_device_data *self);
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u32 (*get_num_accels)(struct adf_hw_device_data *self);
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void (*get_arb_info)(struct arb_info *arb_csrs_info);
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void (*get_admin_info)(struct admin_info *admin_csrs_info);
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enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self);
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int (*alloc_irq)(struct adf_accel_dev *accel_dev);
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void (*free_irq)(struct adf_accel_dev *accel_dev);
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void (*enable_error_correction)(struct adf_accel_dev *accel_dev);
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int (*init_admin_comms)(struct adf_accel_dev *accel_dev);
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void (*exit_admin_comms)(struct adf_accel_dev *accel_dev);
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int (*send_admin_init)(struct adf_accel_dev *accel_dev);
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int (*init_arb)(struct adf_accel_dev *accel_dev);
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void (*exit_arb)(struct adf_accel_dev *accel_dev);
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const u32 *(*get_arb_mapping)(void);
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int (*init_device)(struct adf_accel_dev *accel_dev);
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int (*enable_pm)(struct adf_accel_dev *accel_dev);
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bool (*handle_pm_interrupt)(struct adf_accel_dev *accel_dev);
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void (*disable_iov)(struct adf_accel_dev *accel_dev);
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void (*configure_iov_threads)(struct adf_accel_dev *accel_dev,
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bool enable);
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void (*enable_ints)(struct adf_accel_dev *accel_dev);
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void (*set_ssm_wdtimer)(struct adf_accel_dev *accel_dev);
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int (*ring_pair_reset)(struct adf_accel_dev *accel_dev, u32 bank_nr);
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void (*reset_device)(struct adf_accel_dev *accel_dev);
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void (*set_msix_rttable)(struct adf_accel_dev *accel_dev);
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char *(*uof_get_name)(struct adf_accel_dev *accel_dev, u32 obj_num);
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u32 (*uof_get_num_objs)(void);
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u32 (*uof_get_ae_mask)(struct adf_accel_dev *accel_dev, u32 obj_num);
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int (*dev_config)(struct adf_accel_dev *accel_dev);
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struct adf_pfvf_ops pfvf_ops;
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struct adf_hw_csr_ops csr_ops;
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struct adf_dc_ops dc_ops;
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const char *fw_name;
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const char *fw_mmp_name;
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u32 fuses;
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u32 straps;
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u32 accel_capabilities_mask;
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u32 extended_dc_capabilities;
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u32 clock_frequency;
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u32 instance_id;
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u16 accel_mask;
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u32 ae_mask;
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u32 admin_ae_mask;
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u16 tx_rings_mask;
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u16 ring_to_svc_map;
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u8 tx_rx_gap;
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u8 num_banks;
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u16 num_banks_per_vf;
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u8 num_rings_per_bank;
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u8 num_accel;
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u8 num_logical_accel;
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u8 num_engines;
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};
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/* CSR write macro */
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#define ADF_CSR_WR(csr_base, csr_offset, val) \
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__raw_writel(val, csr_base + csr_offset)
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/* CSR read macro */
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#define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset)
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#define ADF_CFG_NUM_SERVICES 4
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#define ADF_SRV_TYPE_BIT_LEN 3
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#define ADF_SRV_TYPE_MASK 0x7
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#define GET_DEV(accel_dev) ((accel_dev)->accel_pci_dev.pci_dev->dev)
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#define GET_BARS(accel_dev) ((accel_dev)->accel_pci_dev.pci_bars)
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#define GET_HW_DATA(accel_dev) (accel_dev->hw_device)
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#define GET_MAX_BANKS(accel_dev) (GET_HW_DATA(accel_dev)->num_banks)
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#define GET_NUM_RINGS_PER_BANK(accel_dev) \
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GET_HW_DATA(accel_dev)->num_rings_per_bank
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#define GET_SRV_TYPE(accel_dev, idx) \
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(((GET_HW_DATA(accel_dev)->ring_to_svc_map) >> (ADF_SRV_TYPE_BIT_LEN * (idx))) \
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& ADF_SRV_TYPE_MASK)
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#define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines)
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#define GET_CSR_OPS(accel_dev) (&(accel_dev)->hw_device->csr_ops)
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#define GET_PFVF_OPS(accel_dev) (&(accel_dev)->hw_device->pfvf_ops)
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#define GET_DC_OPS(accel_dev) (&(accel_dev)->hw_device->dc_ops)
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#define accel_to_pci_dev(accel_ptr) accel_ptr->accel_pci_dev.pci_dev
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struct adf_admin_comms;
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struct icp_qat_fw_loader_handle;
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struct adf_fw_loader_data {
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struct icp_qat_fw_loader_handle *fw_loader;
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const struct firmware *uof_fw;
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const struct firmware *mmp_fw;
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};
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struct adf_accel_vf_info {
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struct adf_accel_dev *accel_dev;
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struct mutex pf2vf_lock; /* protect CSR access for PF2VF messages */
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struct ratelimit_state vf2pf_ratelimit;
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u32 vf_nr;
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bool init;
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u8 vf_compat_ver;
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};
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struct adf_dc_data {
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u8 *ovf_buff;
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size_t ovf_buff_sz;
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dma_addr_t ovf_buff_p;
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};
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struct adf_accel_dev {
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struct adf_etr_data *transport;
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struct adf_hw_device_data *hw_device;
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struct adf_cfg_device_data *cfg;
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struct adf_fw_loader_data *fw_loader;
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struct adf_admin_comms *admin;
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struct adf_dc_data *dc_data;
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struct list_head crypto_list;
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struct list_head compression_list;
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unsigned long status;
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atomic_t ref_count;
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struct dentry *debugfs_dir;
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struct list_head list;
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struct module *owner;
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struct adf_accel_pci accel_pci_dev;
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union {
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struct {
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/* protects VF2PF interrupts access */
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spinlock_t vf2pf_ints_lock;
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/* vf_info is non-zero when SR-IOV is init'ed */
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struct adf_accel_vf_info *vf_info;
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} pf;
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struct {
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bool irq_enabled;
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char irq_name[ADF_MAX_MSIX_VECTOR_NAME];
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struct tasklet_struct pf2vf_bh_tasklet;
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struct mutex vf2pf_lock; /* protect CSR access */
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struct completion msg_received;
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struct pfvf_message response; /* temp field holding pf2vf response */
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u8 pf_compat_ver;
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} vf;
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};
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struct mutex state_lock; /* protect state of the device */
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bool is_vf;
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u32 accel_id;
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};
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#endif
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