389 lines
13 KiB
C
389 lines
13 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _SMU7_HWMGR_H
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#define _SMU7_HWMGR_H
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#include "hwmgr.h"
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#include "ppatomctrl.h"
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#define SMU7_MAX_HARDWARE_POWERLEVELS 2
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#define SMU7_VOLTAGE_CONTROL_NONE 0x0
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#define SMU7_VOLTAGE_CONTROL_BY_GPIO 0x1
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#define SMU7_VOLTAGE_CONTROL_BY_SVID2 0x2
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#define SMU7_VOLTAGE_CONTROL_MERGED 0x3
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enum gpu_pt_config_reg_type {
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GPU_CONFIGREG_MMR = 0,
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GPU_CONFIGREG_SMC_IND,
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GPU_CONFIGREG_DIDT_IND,
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GPU_CONFIGREG_GC_CAC_IND,
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GPU_CONFIGREG_CACHE,
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GPU_CONFIGREG_MAX
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};
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struct gpu_pt_config_reg {
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uint32_t offset;
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uint32_t mask;
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uint32_t shift;
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uint32_t value;
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enum gpu_pt_config_reg_type type;
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};
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struct smu7_performance_level {
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uint32_t memory_clock;
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uint32_t engine_clock;
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uint16_t pcie_gen;
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uint16_t pcie_lane;
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};
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struct smu7_thermal_temperature_setting {
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long temperature_low;
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long temperature_high;
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long temperature_shutdown;
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};
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struct smu7_uvd_clocks {
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uint32_t vclk;
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uint32_t dclk;
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};
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struct smu7_vce_clocks {
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uint32_t evclk;
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uint32_t ecclk;
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};
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struct smu7_power_state {
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uint32_t magic;
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struct smu7_uvd_clocks uvd_clks;
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struct smu7_vce_clocks vce_clks;
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uint32_t sam_clk;
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uint16_t performance_level_count;
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bool dc_compatible;
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uint32_t sclk_threshold;
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struct smu7_performance_level performance_levels[SMU7_MAX_HARDWARE_POWERLEVELS];
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};
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struct smu7_dpm_level {
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bool enabled;
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uint32_t value;
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uint32_t param1;
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};
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#define SMU7_MAX_DEEPSLEEP_DIVIDER_ID 5
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#define MAX_REGULAR_DPM_NUMBER 8
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#define SMU7_MINIMUM_ENGINE_CLOCK 2500
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struct smu7_single_dpm_table {
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uint32_t count;
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struct smu7_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
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};
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struct smu7_dpm_table {
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struct smu7_single_dpm_table sclk_table;
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struct smu7_single_dpm_table mclk_table;
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struct smu7_single_dpm_table pcie_speed_table;
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struct smu7_single_dpm_table vddc_table;
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struct smu7_single_dpm_table vddci_table;
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struct smu7_single_dpm_table mvdd_table;
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};
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struct smu7_clock_registers {
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uint32_t vCG_SPLL_FUNC_CNTL;
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uint32_t vCG_SPLL_FUNC_CNTL_2;
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uint32_t vCG_SPLL_FUNC_CNTL_3;
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uint32_t vCG_SPLL_FUNC_CNTL_4;
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uint32_t vCG_SPLL_SPREAD_SPECTRUM;
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uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;
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uint32_t vDLL_CNTL;
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uint32_t vMCLK_PWRMGT_CNTL;
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uint32_t vMPLL_AD_FUNC_CNTL;
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uint32_t vMPLL_DQ_FUNC_CNTL;
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uint32_t vMPLL_FUNC_CNTL;
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uint32_t vMPLL_FUNC_CNTL_1;
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uint32_t vMPLL_FUNC_CNTL_2;
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uint32_t vMPLL_SS1;
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uint32_t vMPLL_SS2;
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};
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#define DISABLE_MC_LOADMICROCODE 1
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#define DISABLE_MC_CFGPROGRAMMING 2
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struct smu7_voltage_smio_registers {
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uint32_t vS0_VID_LOWER_SMIO_CNTL;
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};
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#define SMU7_MAX_LEAKAGE_COUNT 8
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struct smu7_leakage_voltage {
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uint16_t count;
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uint16_t leakage_id[SMU7_MAX_LEAKAGE_COUNT];
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uint16_t actual_voltage[SMU7_MAX_LEAKAGE_COUNT];
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};
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struct smu7_vbios_boot_state {
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uint16_t mvdd_bootup_value;
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uint16_t vddc_bootup_value;
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uint16_t vddci_bootup_value;
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uint16_t vddgfx_bootup_value;
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uint32_t sclk_bootup_value;
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uint32_t mclk_bootup_value;
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uint16_t pcie_gen_bootup_value;
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uint16_t pcie_lane_bootup_value;
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};
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struct smu7_display_timing {
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uint32_t min_clock_in_sr;
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uint32_t num_existing_displays;
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uint32_t vrefresh;
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};
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struct smu7_dpmlevel_enable_mask {
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uint32_t uvd_dpm_enable_mask;
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uint32_t vce_dpm_enable_mask;
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uint32_t acp_dpm_enable_mask;
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uint32_t samu_dpm_enable_mask;
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uint32_t sclk_dpm_enable_mask;
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uint32_t mclk_dpm_enable_mask;
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uint32_t pcie_dpm_enable_mask;
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};
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struct smu7_pcie_perf_range {
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uint16_t max;
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uint16_t min;
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};
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struct smu7_odn_clock_voltage_dependency_table {
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uint32_t count;
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phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER];
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};
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struct smu7_odn_dpm_table {
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struct phm_odn_clock_levels odn_core_clock_dpm_levels;
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struct phm_odn_clock_levels odn_memory_clock_dpm_levels;
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struct smu7_odn_clock_voltage_dependency_table vdd_dependency_on_sclk;
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struct smu7_odn_clock_voltage_dependency_table vdd_dependency_on_mclk;
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uint32_t odn_mclk_min_limit;
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uint32_t min_vddc;
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uint32_t max_vddc;
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};
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struct profile_mode_setting {
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uint8_t bupdate_sclk;
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uint8_t sclk_up_hyst;
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uint8_t sclk_down_hyst;
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uint16_t sclk_activity;
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uint8_t bupdate_mclk;
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uint8_t mclk_up_hyst;
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uint8_t mclk_down_hyst;
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uint16_t mclk_activity;
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};
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struct smu7_mclk_latency_entries {
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uint32_t frequency;
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uint32_t latency;
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};
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struct smu7_mclk_latency_table {
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uint32_t count;
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struct smu7_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];
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};
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struct smu7_hwmgr {
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struct smu7_dpm_table dpm_table;
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struct smu7_dpm_table golden_dpm_table;
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struct smu7_odn_dpm_table odn_dpm_table;
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struct smu7_mclk_latency_table mclk_latency_table;
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uint32_t voting_rights_clients[8];
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uint32_t static_screen_threshold_unit;
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uint32_t static_screen_threshold;
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uint32_t voltage_control;
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uint32_t vdd_gfx_control;
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uint32_t vddc_vddgfx_delta;
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uint32_t active_auto_throttle_sources;
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struct smu7_clock_registers clock_registers;
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bool is_memory_gddr5;
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uint16_t acpi_vddc;
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bool pspp_notify_required;
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uint16_t force_pcie_gen;
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uint16_t acpi_pcie_gen;
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uint32_t pcie_gen_cap;
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uint32_t pcie_lane_cap;
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uint32_t pcie_spc_cap;
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struct smu7_leakage_voltage vddc_leakage;
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struct smu7_leakage_voltage vddci_leakage;
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struct smu7_leakage_voltage vddcgfx_leakage;
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uint32_t mvdd_control;
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uint32_t vddc_mask_low;
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uint32_t mvdd_mask_low;
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uint16_t max_vddc_in_pptable;
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uint16_t min_vddc_in_pptable;
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uint16_t max_vddci_in_pptable;
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uint16_t min_vddci_in_pptable;
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bool is_uvd_enabled;
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struct smu7_vbios_boot_state vbios_boot_state;
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bool pcie_performance_request;
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bool battery_state;
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bool mclk_ignore_signal;
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bool is_tlu_enabled;
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bool disable_handshake;
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bool smc_voltage_control_enabled;
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bool vbi_time_out_support;
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uint32_t soft_regs_start;
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/* ---- Stuff originally coming from Evergreen ---- */
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uint32_t vddci_control;
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struct pp_atomctrl_voltage_table vddc_voltage_table;
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struct pp_atomctrl_voltage_table vddci_voltage_table;
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struct pp_atomctrl_voltage_table mvdd_voltage_table;
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struct pp_atomctrl_voltage_table vddgfx_voltage_table;
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uint32_t mgcg_cgtt_local2;
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uint32_t mgcg_cgtt_local3;
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uint32_t gpio_debug;
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uint32_t mc_micro_code_feature;
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uint32_t highest_mclk;
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uint16_t acpi_vddci;
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uint8_t mvdd_high_index;
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uint8_t mvdd_low_index;
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bool dll_default_on;
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bool performance_request_registered;
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/* ---- Low Power Features ---- */
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bool ulv_supported;
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/* ---- CAC Stuff ---- */
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uint32_t cac_table_start;
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bool cac_configuration_required;
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bool driver_calculate_cac_leakage;
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bool cac_enabled;
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/* ---- DPM2 Parameters ---- */
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uint32_t power_containment_features;
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bool enable_dte_feature;
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bool enable_tdc_limit_feature;
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bool enable_pkg_pwr_tracking_feature;
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bool disable_uvd_power_tune_feature;
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uint32_t dte_tj_offset;
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uint32_t fast_watermark_threshold;
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/* ---- Phase Shedding ---- */
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uint8_t vddc_phase_shed_control;
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/* ---- DI/DT ---- */
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struct smu7_display_timing display_timing;
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/* ---- Thermal Temperature Setting ---- */
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struct smu7_thermal_temperature_setting thermal_temp_setting;
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struct smu7_dpmlevel_enable_mask dpm_level_enable_mask;
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uint32_t need_update_smu7_dpm_table;
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uint32_t sclk_dpm_key_disabled;
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uint32_t mclk_dpm_key_disabled;
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uint32_t pcie_dpm_key_disabled;
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uint32_t min_engine_clocks;
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struct smu7_pcie_perf_range pcie_gen_performance;
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struct smu7_pcie_perf_range pcie_lane_performance;
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struct smu7_pcie_perf_range pcie_gen_power_saving;
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struct smu7_pcie_perf_range pcie_lane_power_saving;
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bool use_pcie_performance_levels;
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bool use_pcie_power_saving_levels;
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uint32_t mclk_dpm0_activity_target;
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uint32_t low_sclk_interrupt_threshold;
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uint32_t last_mclk_dpm_enable_mask;
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bool uvd_enabled;
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/* ---- Power Gating States ---- */
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bool uvd_power_gated;
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bool vce_power_gated;
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bool need_long_memory_training;
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/* Application power optimization parameters */
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bool update_up_hyst;
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bool update_down_hyst;
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uint32_t down_hyst;
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uint32_t up_hyst;
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uint32_t disable_dpm_mask;
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bool apply_optimized_settings;
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uint32_t avfs_vdroop_override_setting;
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bool apply_avfs_cks_off_voltage;
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uint32_t frame_time_x2;
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uint32_t last_sent_vbi_timeout;
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uint16_t mem_latency_high;
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uint16_t mem_latency_low;
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uint32_t vr_config;
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struct profile_mode_setting current_profile_setting;
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uint32_t ro_range_minimum;
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uint32_t ro_range_maximum;
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bool disable_edc_leakage_controller;
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AtomCtrl_HiLoLeakageOffsetTable edc_hilo_leakage_offset_from_vbios;
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AtomCtrl_EDCLeakgeTable edc_leakage_table;
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};
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/* To convert to Q8.8 format for firmware */
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#define SMU7_Q88_FORMAT_CONVERSION_UNIT 256
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enum SMU7_I2CLineID {
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SMU7_I2CLineID_DDC1 = 0x90,
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SMU7_I2CLineID_DDC2 = 0x91,
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SMU7_I2CLineID_DDC3 = 0x92,
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SMU7_I2CLineID_DDC4 = 0x93,
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SMU7_I2CLineID_DDC5 = 0x94,
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SMU7_I2CLineID_DDC6 = 0x95,
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SMU7_I2CLineID_SCLSDA = 0x96,
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SMU7_I2CLineID_DDCVGA = 0x97
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};
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#define SMU7_I2C_DDC1DATA 0
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#define SMU7_I2C_DDC1CLK 1
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#define SMU7_I2C_DDC2DATA 2
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#define SMU7_I2C_DDC2CLK 3
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#define SMU7_I2C_DDC3DATA 4
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#define SMU7_I2C_DDC3CLK 5
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#define SMU7_I2C_SDA 40
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#define SMU7_I2C_SCL 41
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#define SMU7_I2C_DDC4DATA 65
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#define SMU7_I2C_DDC4CLK 66
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#define SMU7_I2C_DDC5DATA 0x48
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#define SMU7_I2C_DDC5CLK 0x49
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#define SMU7_I2C_DDC6DATA 0x4a
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#define SMU7_I2C_DDC6CLK 0x4b
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#define SMU7_I2C_DDCVGADATA 0x4c
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#define SMU7_I2C_DDCVGACLK 0x4d
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#define SMU7_UNUSED_GPIO_PIN 0x7F
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uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
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uint32_t clock_insr);
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#endif
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