745 lines
19 KiB
C
745 lines
19 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/**************************************************************************
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* Copyright (c) 2007-2011, Intel Corporation.
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* All Rights Reserved.
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*
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**************************************************************************/
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#ifndef _PSB_DRV_H_
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#define _PSB_DRV_H_
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#include <linux/kref.h>
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#include <linux/mm_types.h>
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#include <drm/drm_device.h>
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#include "gtt.h"
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#include "intel_bios.h"
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#include "mmu.h"
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#include "oaktrail.h"
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#include "opregion.h"
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#include "power.h"
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#include "psb_intel_drv.h"
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#include "psb_reg.h"
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#define DRIVER_AUTHOR "Alan Cox <alan@linux.intel.com> and others"
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#define DRIVER_NAME "gma500"
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#define DRIVER_DESC "DRM driver for the Intel GMA500, GMA600, GMA3600, GMA3650"
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#define DRIVER_DATE "20140314"
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#define DRIVER_MAJOR 1
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#define DRIVER_MINOR 0
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#define DRIVER_PATCHLEVEL 0
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/* Append new drm mode definition here, align with libdrm definition */
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#define DRM_MODE_SCALE_NO_SCALE 2
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#define IS_PSB(drm) ((to_pci_dev((drm)->dev)->device & 0xfffe) == 0x8108)
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#define IS_MRST(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x4100)
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#define IS_CDV(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x0be0)
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/* Hardware offsets */
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#define PSB_VDC_OFFSET 0x00000000
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#define PSB_VDC_SIZE 0x000080000
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#define MRST_MMIO_SIZE 0x0000C0000
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#define PSB_SGX_SIZE 0x8000
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#define PSB_SGX_OFFSET 0x00040000
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#define MRST_SGX_OFFSET 0x00080000
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/* PCI resource identifiers */
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#define PSB_MMIO_RESOURCE 0
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#define PSB_AUX_RESOURCE 0
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#define PSB_GATT_RESOURCE 2
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#define PSB_GTT_RESOURCE 3
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/* PCI configuration */
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#define PSB_GMCH_CTRL 0x52
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#define PSB_BSM 0x5C
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#define _PSB_GMCH_ENABLED 0x4
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#define PSB_PGETBL_CTL 0x2020
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#define _PSB_PGETBL_ENABLED 0x00000001
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#define PSB_SGX_2D_SLAVE_PORT 0x4000
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#define PSB_LPC_GBA 0x44
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/* TODO: To get rid of */
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#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
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#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
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/* SGX side MMU definitions (these can probably go) */
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/* Flags for external memory type field */
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#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
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#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
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#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
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/* PTE's and PDE's */
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#define PSB_PDE_MASK 0x003FFFFF
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#define PSB_PDE_SHIFT 22
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#define PSB_PTE_SHIFT 12
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/* Cache control */
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#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
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#define PSB_PTE_WO 0x0002 /* Write only */
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#define PSB_PTE_RO 0x0004 /* Read only */
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#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
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/* VDC registers and bits */
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#define PSB_MSVDX_CLOCKGATING 0x2064
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#define PSB_TOPAZ_CLOCKGATING 0x2068
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#define PSB_HWSTAM 0x2098
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#define PSB_INSTPM 0x20C0
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#define PSB_INT_IDENTITY_R 0x20A4
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#define _PSB_IRQ_ASLE (1<<0)
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#define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
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#define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
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#define _PSB_DPST_PIPEB_FLAG (1<<4)
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#define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
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#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
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#define _PSB_DPST_PIPEA_FLAG (1<<6)
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#define _PSB_PIPEA_EVENT_FLAG (1<<6)
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#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
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#define _PSB_IRQ_DISP_HOTSYNC (1<<17)
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#define _PSB_IRQ_SGX_FLAG (1<<18)
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#define _PSB_IRQ_MSVDX_FLAG (1<<19)
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#define _LNC_IRQ_TOPAZ_FLAG (1<<20)
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#define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \
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_PSB_VSYNC_PIPEB_FLAG)
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#define PSB_INT_IDENTITY_R 0x20A4
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#define PSB_INT_MASK_R 0x20A8
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#define PSB_INT_ENABLE_R 0x20A0
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#define _PSB_MMU_ER_MASK 0x0001FF00
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#define _PSB_MMU_ER_HOST (1 << 16)
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#define GPIOA 0x5010
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#define GPIOB 0x5014
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#define GPIOC 0x5018
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#define GPIOD 0x501c
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#define GPIOE 0x5020
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#define GPIOF 0x5024
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#define GPIOG 0x5028
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#define GPIOH 0x502c
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#define GPIO_CLOCK_DIR_MASK (1 << 0)
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#define GPIO_CLOCK_DIR_IN (0 << 1)
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#define GPIO_CLOCK_DIR_OUT (1 << 1)
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#define GPIO_CLOCK_VAL_MASK (1 << 2)
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#define GPIO_CLOCK_VAL_OUT (1 << 3)
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#define GPIO_CLOCK_VAL_IN (1 << 4)
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#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
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#define GPIO_DATA_DIR_MASK (1 << 8)
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#define GPIO_DATA_DIR_IN (0 << 9)
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#define GPIO_DATA_DIR_OUT (1 << 9)
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#define GPIO_DATA_VAL_MASK (1 << 10)
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#define GPIO_DATA_VAL_OUT (1 << 11)
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#define GPIO_DATA_VAL_IN (1 << 12)
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#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
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#define VCLK_DIVISOR_VGA0 0x6000
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#define VCLK_DIVISOR_VGA1 0x6004
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#define VCLK_POST_DIV 0x6010
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#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
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#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
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#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
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#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
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#define PSB_COMM_USER_IRQ (1024 >> 2)
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#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
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#define PSB_COMM_FW (2048 >> 2)
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#define PSB_UIRQ_VISTEST 1
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#define PSB_UIRQ_OOM_REPLY 2
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#define PSB_UIRQ_FIRE_TA_REPLY 3
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#define PSB_UIRQ_FIRE_RASTER_REPLY 4
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#define PSB_2D_SIZE (256*1024*1024)
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#define PSB_MAX_RELOC_PAGES 1024
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#define PSB_LOW_REG_OFFS 0x0204
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#define PSB_HIGH_REG_OFFS 0x0600
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#define PSB_NUM_VBLANKS 2
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#define PSB_2D_SIZE (256*1024*1024)
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#define PSB_MAX_RELOC_PAGES 1024
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#define PSB_LOW_REG_OFFS 0x0204
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#define PSB_HIGH_REG_OFFS 0x0600
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#define PSB_NUM_VBLANKS 2
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#define PSB_WATCHDOG_DELAY (HZ * 2)
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#define PSB_LID_DELAY (HZ / 10)
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#define PSB_MAX_BRIGHTNESS 100
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#define PSB_PWR_STATE_ON 1
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#define PSB_PWR_STATE_OFF 2
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#define PSB_PMPOLICY_NOPM 0
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#define PSB_PMPOLICY_CLOCKGATING 1
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#define PSB_PMPOLICY_POWERDOWN 2
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#define PSB_PMSTATE_POWERUP 0
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#define PSB_PMSTATE_CLOCKGATED 1
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#define PSB_PMSTATE_POWERDOWN 2
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#define PSB_PCIx_MSI_ADDR_LOC 0x94
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#define PSB_PCIx_MSI_DATA_LOC 0x98
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/* Medfield crystal settings */
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#define KSEL_CRYSTAL_19 1
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#define KSEL_BYPASS_19 5
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#define KSEL_BYPASS_25 6
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#define KSEL_BYPASS_83_100 7
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struct opregion_header;
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struct opregion_acpi;
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struct opregion_swsci;
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struct opregion_asle;
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struct psb_intel_opregion {
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struct opregion_header *header;
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struct opregion_acpi *acpi;
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struct opregion_swsci *swsci;
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struct opregion_asle *asle;
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void *vbt;
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u32 __iomem *lid_state;
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struct work_struct asle_work;
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};
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struct sdvo_device_mapping {
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u8 initialized;
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u8 dvo_port;
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u8 slave_addr;
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u8 dvo_wiring;
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u8 i2c_pin;
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u8 i2c_speed;
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u8 ddc_pin;
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};
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struct intel_gmbus {
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struct i2c_adapter adapter;
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struct i2c_adapter *force_bit;
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u32 reg0;
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};
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/* Register offset maps */
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struct psb_offset {
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u32 fp0;
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u32 fp1;
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u32 cntr;
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u32 conf;
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u32 src;
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u32 dpll;
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u32 dpll_md;
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u32 htotal;
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u32 hblank;
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u32 hsync;
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u32 vtotal;
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u32 vblank;
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u32 vsync;
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u32 stride;
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u32 size;
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u32 pos;
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u32 surf;
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u32 addr;
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u32 base;
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u32 status;
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u32 linoff;
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u32 tileoff;
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u32 palette;
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};
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/*
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* Register save state. This is used to hold the context when the
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* device is powered off. In the case of Oaktrail this can (but does not
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* yet) include screen blank. Operations occuring during the save
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* update the register cache instead.
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*/
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/* Common status for pipes */
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struct psb_pipe {
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u32 fp0;
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u32 fp1;
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u32 cntr;
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u32 conf;
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u32 src;
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u32 dpll;
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u32 dpll_md;
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u32 htotal;
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u32 hblank;
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u32 hsync;
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u32 vtotal;
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u32 vblank;
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u32 vsync;
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u32 stride;
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u32 size;
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u32 pos;
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u32 base;
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u32 surf;
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u32 addr;
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u32 status;
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u32 linoff;
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u32 tileoff;
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u32 palette[256];
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};
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struct psb_state {
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uint32_t saveVCLK_DIVISOR_VGA0;
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uint32_t saveVCLK_DIVISOR_VGA1;
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uint32_t saveVCLK_POST_DIV;
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uint32_t saveVGACNTRL;
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uint32_t saveADPA;
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uint32_t saveLVDS;
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uint32_t saveDVOA;
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uint32_t saveDVOB;
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uint32_t saveDVOC;
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uint32_t savePP_ON;
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uint32_t savePP_OFF;
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uint32_t savePP_CONTROL;
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uint32_t savePP_CYCLE;
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uint32_t savePFIT_CONTROL;
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uint32_t saveCLOCKGATING;
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uint32_t saveDSPARB;
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uint32_t savePFIT_AUTO_RATIOS;
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uint32_t savePFIT_PGM_RATIOS;
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uint32_t savePP_ON_DELAYS;
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uint32_t savePP_OFF_DELAYS;
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uint32_t savePP_DIVISOR;
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uint32_t saveBCLRPAT_A;
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uint32_t saveBCLRPAT_B;
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uint32_t savePERF_MODE;
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uint32_t saveDSPFW1;
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uint32_t saveDSPFW2;
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uint32_t saveDSPFW3;
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uint32_t saveDSPFW4;
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uint32_t saveDSPFW5;
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uint32_t saveDSPFW6;
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uint32_t saveCHICKENBIT;
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uint32_t saveDSPACURSOR_CTRL;
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uint32_t saveDSPBCURSOR_CTRL;
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uint32_t saveDSPACURSOR_BASE;
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uint32_t saveDSPBCURSOR_BASE;
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uint32_t saveDSPACURSOR_POS;
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uint32_t saveDSPBCURSOR_POS;
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uint32_t saveOV_OVADD;
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uint32_t saveOV_OGAMC0;
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uint32_t saveOV_OGAMC1;
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uint32_t saveOV_OGAMC2;
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uint32_t saveOV_OGAMC3;
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uint32_t saveOV_OGAMC4;
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uint32_t saveOV_OGAMC5;
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uint32_t saveOVC_OVADD;
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uint32_t saveOVC_OGAMC0;
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uint32_t saveOVC_OGAMC1;
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uint32_t saveOVC_OGAMC2;
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uint32_t saveOVC_OGAMC3;
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uint32_t saveOVC_OGAMC4;
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uint32_t saveOVC_OGAMC5;
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/* DPST register save */
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uint32_t saveHISTOGRAM_INT_CONTROL_REG;
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uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
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uint32_t savePWM_CONTROL_LOGIC;
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};
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struct cdv_state {
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uint32_t saveDSPCLK_GATE_D;
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uint32_t saveRAMCLK_GATE_D;
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uint32_t saveDSPARB;
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uint32_t saveDSPFW[6];
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uint32_t saveADPA;
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uint32_t savePP_CONTROL;
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uint32_t savePFIT_PGM_RATIOS;
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uint32_t saveLVDS;
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uint32_t savePFIT_CONTROL;
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uint32_t savePP_ON_DELAYS;
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uint32_t savePP_OFF_DELAYS;
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uint32_t savePP_CYCLE;
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uint32_t saveVGACNTRL;
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uint32_t saveIER;
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uint32_t saveIMR;
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u8 saveLBB;
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};
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struct psb_save_area {
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struct psb_pipe pipe[3];
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uint32_t saveBSM;
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uint32_t saveVBT;
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union {
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struct psb_state psb;
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struct cdv_state cdv;
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};
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uint32_t saveBLC_PWM_CTL2;
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uint32_t saveBLC_PWM_CTL;
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};
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struct psb_ops;
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#define PSB_NUM_PIPE 3
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struct intel_scu_ipc_dev;
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struct drm_psb_private {
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struct drm_device dev;
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struct pci_dev *aux_pdev; /* Currently only used by mrst */
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struct pci_dev *lpc_pdev; /* Currently only used by mrst */
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const struct psb_ops *ops;
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const struct psb_offset *regmap;
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struct child_device_config *child_dev;
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int child_dev_num;
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struct psb_gtt gtt;
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/* GTT Memory manager */
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struct psb_gtt_mm *gtt_mm;
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struct page *scratch_page;
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u32 __iomem *gtt_map;
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uint32_t stolen_base;
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u8 __iomem *vram_addr;
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unsigned long vram_stolen_size;
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u16 gmch_ctrl; /* Saved GTT setup */
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u32 pge_ctl;
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struct mutex gtt_mutex;
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struct resource *gtt_mem; /* Our PCI resource */
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struct mutex mmap_mutex;
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struct psb_mmu_driver *mmu;
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struct psb_mmu_pd *pf_pd;
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/* Register base */
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uint8_t __iomem *sgx_reg;
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uint8_t __iomem *vdc_reg;
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uint8_t __iomem *aux_reg; /* Auxillary vdc pipe regs */
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uint16_t lpc_gpio_base;
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uint32_t gatt_free_offset;
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/* Fencing / irq */
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uint32_t vdc_irq_mask;
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uint32_t pipestat[PSB_NUM_PIPE];
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spinlock_t irqmask_lock;
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/* Power */
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bool pm_initialized;
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/* Modesetting */
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struct psb_intel_mode_device mode_dev;
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bool modeset; /* true if we have done the mode_device setup */
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struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
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struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
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uint32_t num_pipe;
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/* OSPM info (Power management base) (TODO: can go ?) */
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uint32_t ospm_base;
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/* Sizes info */
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u32 fuse_reg_value;
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u32 video_device_fuse;
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/* PCI revision ID for B0:D2:F0 */
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uint8_t platform_rev_id;
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/* gmbus */
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struct intel_gmbus *gmbus;
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uint8_t __iomem *gmbus_reg;
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/* Used by SDVO */
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int crt_ddc_pin;
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/* FIXME: The mappings should be parsed from bios but for now we can
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pretend there are no mappings available */
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struct sdvo_device_mapping sdvo_mappings[2];
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u32 hotplug_supported_mask;
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struct drm_property *broadcast_rgb_property;
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struct drm_property *force_audio_property;
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/* LVDS info */
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int backlight_duty_cycle; /* restore backlight to this value */
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bool panel_wants_dither;
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struct drm_display_mode *panel_fixed_mode;
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struct drm_display_mode *lfp_lvds_vbt_mode;
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struct drm_display_mode *sdvo_lvds_vbt_mode;
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struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
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struct gma_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
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/* Feature bits from the VBIOS */
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unsigned int int_tv_support:1;
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unsigned int lvds_dither:1;
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unsigned int lvds_vbt:1;
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unsigned int int_crt_support:1;
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unsigned int lvds_use_ssc:1;
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int lvds_ssc_freq;
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|
bool is_lvds_on;
|
|
bool is_mipi_on;
|
|
bool lvds_enabled_in_vbt;
|
|
u32 mipi_ctrl_display;
|
|
|
|
unsigned int core_freq;
|
|
uint32_t iLVDS_enable;
|
|
|
|
/* MID specific */
|
|
bool use_msi;
|
|
bool has_gct;
|
|
struct oaktrail_gct_data gct_data;
|
|
|
|
/* Oaktrail HDMI state */
|
|
struct oaktrail_hdmi_dev *hdmi_priv;
|
|
|
|
/* Register state */
|
|
struct psb_save_area regs;
|
|
|
|
/* Hotplug handling */
|
|
struct work_struct hotplug_work;
|
|
|
|
/* LID-Switch */
|
|
spinlock_t lid_lock;
|
|
struct timer_list lid_timer;
|
|
struct psb_intel_opregion opregion;
|
|
u32 lid_last_state;
|
|
|
|
/* Watchdog */
|
|
uint32_t apm_reg;
|
|
uint16_t apm_base;
|
|
|
|
/*
|
|
* Used for modifying backlight from
|
|
* xrandr -- consider removing and using HAL instead
|
|
*/
|
|
struct intel_scu_ipc_dev *scu;
|
|
struct backlight_device *backlight_device;
|
|
struct drm_property *backlight_property;
|
|
bool backlight_enabled;
|
|
int backlight_level;
|
|
uint32_t blc_adj1;
|
|
uint32_t blc_adj2;
|
|
|
|
bool dsr_enable;
|
|
u32 dsr_fb_update;
|
|
bool dpi_panel_on[3];
|
|
void *dsi_configs[2];
|
|
u32 bpp;
|
|
u32 bpp2;
|
|
|
|
u32 pipeconf[3];
|
|
u32 dspcntr[3];
|
|
|
|
bool dplla_96mhz; /* DPLL data from the VBT */
|
|
|
|
struct {
|
|
int rate;
|
|
int lanes;
|
|
int preemphasis;
|
|
int vswing;
|
|
|
|
bool initialized;
|
|
bool support;
|
|
int bpp;
|
|
struct edp_power_seq pps;
|
|
} edp;
|
|
uint8_t panel_type;
|
|
};
|
|
|
|
static inline struct drm_psb_private *to_drm_psb_private(struct drm_device *dev)
|
|
{
|
|
return container_of(dev, struct drm_psb_private, dev);
|
|
}
|
|
|
|
/* Operations for each board type */
|
|
struct psb_ops {
|
|
const char *name;
|
|
int pipes; /* Number of output pipes */
|
|
int crtcs; /* Number of CRTCs */
|
|
int sgx_offset; /* Base offset of SGX device */
|
|
int hdmi_mask; /* Mask of HDMI CRTCs */
|
|
int lvds_mask; /* Mask of LVDS CRTCs */
|
|
int sdvo_mask; /* Mask of SDVO CRTCs */
|
|
int cursor_needs_phys; /* If cursor base reg need physical address */
|
|
|
|
/* Sub functions */
|
|
struct drm_crtc_helper_funcs const *crtc_helper;
|
|
const struct gma_clock_funcs *clock_funcs;
|
|
|
|
/* Setup hooks */
|
|
int (*chip_setup)(struct drm_device *dev);
|
|
void (*chip_teardown)(struct drm_device *dev);
|
|
/* Optional helper caller after modeset */
|
|
void (*errata)(struct drm_device *dev);
|
|
|
|
/* Display management hooks */
|
|
int (*output_init)(struct drm_device *dev);
|
|
int (*hotplug)(struct drm_device *dev);
|
|
void (*hotplug_enable)(struct drm_device *dev, bool on);
|
|
/* Power management hooks */
|
|
void (*init_pm)(struct drm_device *dev);
|
|
int (*save_regs)(struct drm_device *dev);
|
|
int (*restore_regs)(struct drm_device *dev);
|
|
void (*save_crtc)(struct drm_crtc *crtc);
|
|
void (*restore_crtc)(struct drm_crtc *crtc);
|
|
int (*power_up)(struct drm_device *dev);
|
|
int (*power_down)(struct drm_device *dev);
|
|
void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc);
|
|
void (*disable_sr)(struct drm_device *dev);
|
|
|
|
void (*lvds_bl_power)(struct drm_device *dev, bool on);
|
|
|
|
/* Backlight */
|
|
int (*backlight_init)(struct drm_device *dev);
|
|
void (*backlight_set)(struct drm_device *dev, int level);
|
|
int (*backlight_get)(struct drm_device *dev);
|
|
const char *backlight_name;
|
|
|
|
int i2c_bus; /* I2C bus identifier for Moorestown */
|
|
};
|
|
|
|
/* psb_lid.c */
|
|
extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
|
|
extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
|
|
|
|
/* modesetting */
|
|
extern void psb_modeset_init(struct drm_device *dev);
|
|
extern void psb_modeset_cleanup(struct drm_device *dev);
|
|
|
|
/* framebuffer */
|
|
struct drm_framebuffer *psb_framebuffer_create(struct drm_device *dev,
|
|
const struct drm_mode_fb_cmd2 *mode_cmd,
|
|
struct drm_gem_object *obj);
|
|
|
|
/* fbdev */
|
|
#if defined(CONFIG_DRM_FBDEV_EMULATION)
|
|
void psb_fbdev_setup(struct drm_psb_private *dev_priv);
|
|
#else
|
|
static inline void psb_fbdev_setup(struct drm_psb_private *dev_priv)
|
|
{ }
|
|
#endif
|
|
|
|
/* backlight.c */
|
|
int gma_backlight_init(struct drm_device *dev);
|
|
void gma_backlight_exit(struct drm_device *dev);
|
|
void gma_backlight_disable(struct drm_device *dev);
|
|
void gma_backlight_enable(struct drm_device *dev);
|
|
void gma_backlight_set(struct drm_device *dev, int v);
|
|
|
|
/* oaktrail_crtc.c */
|
|
extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
|
|
|
|
/* oaktrail_lvds.c */
|
|
extern void oaktrail_lvds_init(struct drm_device *dev,
|
|
struct psb_intel_mode_device *mode_dev);
|
|
|
|
/* psb_intel_display.c */
|
|
extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
|
|
|
|
/* psb_intel_lvds.c */
|
|
extern const struct drm_connector_helper_funcs
|
|
psb_intel_lvds_connector_helper_funcs;
|
|
extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
|
|
|
|
/* gem.c */
|
|
extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
|
|
struct drm_mode_create_dumb *args);
|
|
|
|
/* psb_device.c */
|
|
extern const struct psb_ops psb_chip_ops;
|
|
|
|
/* oaktrail_device.c */
|
|
extern const struct psb_ops oaktrail_chip_ops;
|
|
|
|
/* cdv_device.c */
|
|
extern const struct psb_ops cdv_chip_ops;
|
|
|
|
/* Utilities */
|
|
static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
|
|
{
|
|
struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
|
|
return ioread32(dev_priv->vdc_reg + reg);
|
|
}
|
|
|
|
static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg)
|
|
{
|
|
struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
|
|
return ioread32(dev_priv->aux_reg + reg);
|
|
}
|
|
|
|
#define REG_READ(reg) REGISTER_READ(dev, (reg))
|
|
#define REG_READ_AUX(reg) REGISTER_READ_AUX(dev, (reg))
|
|
|
|
/* Useful for post reads */
|
|
static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev,
|
|
uint32_t reg, int aux)
|
|
{
|
|
uint32_t val;
|
|
|
|
if (aux)
|
|
val = REG_READ_AUX(reg);
|
|
else
|
|
val = REG_READ(reg);
|
|
|
|
return val;
|
|
}
|
|
|
|
#define REG_READ_WITH_AUX(reg, aux) REGISTER_READ_WITH_AUX(dev, (reg), (aux))
|
|
|
|
static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
|
|
uint32_t val)
|
|
{
|
|
struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
|
|
iowrite32((val), dev_priv->vdc_reg + (reg));
|
|
}
|
|
|
|
static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg,
|
|
uint32_t val)
|
|
{
|
|
struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
|
|
iowrite32((val), dev_priv->aux_reg + (reg));
|
|
}
|
|
|
|
#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
|
|
#define REG_WRITE_AUX(reg, val) REGISTER_WRITE_AUX(dev, (reg), (val))
|
|
|
|
static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg,
|
|
uint32_t val, int aux)
|
|
{
|
|
if (aux)
|
|
REG_WRITE_AUX(reg, val);
|
|
else
|
|
REG_WRITE(reg, val);
|
|
}
|
|
|
|
#define REG_WRITE_WITH_AUX(reg, val, aux) REGISTER_WRITE_WITH_AUX(dev, (reg), (val), (aux))
|
|
|
|
static inline void REGISTER_WRITE16(struct drm_device *dev,
|
|
uint32_t reg, uint32_t val)
|
|
{
|
|
struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
|
|
iowrite16((val), dev_priv->vdc_reg + (reg));
|
|
}
|
|
|
|
#define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
|
|
|
|
static inline void REGISTER_WRITE8(struct drm_device *dev,
|
|
uint32_t reg, uint32_t val)
|
|
{
|
|
struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
|
|
iowrite8((val), dev_priv->vdc_reg + (reg));
|
|
}
|
|
|
|
#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
|
|
|
|
#define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
|
|
#define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
|
|
|
|
#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
|
|
#define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
|
|
|
|
#define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
|
|
#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
|
|
|
|
#endif
|