539 lines
18 KiB
C
539 lines
18 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022-2023 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "intel_de.h"
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#include "intel_display_types.h"
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#include "intel_vblank.h"
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#include "intel_vrr.h"
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/*
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* This timing diagram depicts the video signal in and
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* around the vertical blanking period.
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*
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* Assumptions about the fictitious mode used in this example:
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* vblank_start >= 3
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* vsync_start = vblank_start + 1
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* vsync_end = vblank_start + 2
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* vtotal = vblank_start + 3
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*
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* start of vblank:
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* latch double buffered registers
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* increment frame counter (ctg+)
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* generate start of vblank interrupt (gen4+)
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* |
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* | frame start:
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* | generate frame start interrupt (aka. vblank interrupt) (gmch)
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* | may be shifted forward 1-3 extra lines via TRANSCONF
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* | |
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* | | start of vsync:
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* | | generate vsync interrupt
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* | | |
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* ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
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* . \hs/ . \hs/ \hs/ \hs/ . \hs/
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* ----va---> <-----------------vb--------------------> <--------va-------------
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* | | <----vs-----> |
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* -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
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* -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
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* -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
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* | | |
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* last visible pixel first visible pixel
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* | increment frame counter (gen3/4)
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* pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
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*
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* x = horizontal active
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* _ = horizontal blanking
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* hs = horizontal sync
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* va = vertical active
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* vb = vertical blanking
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* vs = vertical sync
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* vbs = vblank_start (number)
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*
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* Summary:
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* - most events happen at the start of horizontal sync
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* - frame start happens at the start of horizontal blank, 1-4 lines
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* (depending on TRANSCONF settings) after the start of vblank
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* - gen3/4 pixel and frame counter are synchronized with the start
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* of horizontal active on the first line of vertical active
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*/
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/*
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* Called from drm generic code, passed a 'crtc', which we use as a pipe index.
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*/
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u32 i915_get_vblank_counter(struct drm_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->dev);
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struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
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const struct drm_display_mode *mode = &vblank->hwmode;
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enum pipe pipe = to_intel_crtc(crtc)->pipe;
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u32 pixel, vbl_start, hsync_start, htotal;
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u64 frame;
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/*
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* On i965gm TV output the frame counter only works up to
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* the point when we enable the TV encoder. After that the
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* frame counter ceases to work and reads zero. We need a
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* vblank wait before enabling the TV encoder and so we
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* have to enable vblank interrupts while the frame counter
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* is still in a working state. However the core vblank code
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* does not like us returning non-zero frame counter values
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* when we've told it that we don't have a working frame
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* counter. Thus we must stop non-zero values leaking out.
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*/
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if (!vblank->max_vblank_count)
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return 0;
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htotal = mode->crtc_htotal;
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hsync_start = mode->crtc_hsync_start;
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vbl_start = mode->crtc_vblank_start;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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vbl_start = DIV_ROUND_UP(vbl_start, 2);
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/* Convert to pixel count */
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vbl_start *= htotal;
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/* Start of vblank event occurs at start of hsync */
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vbl_start -= htotal - hsync_start;
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/*
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* High & low register fields aren't synchronized, so make sure
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* we get a low value that's stable across two reads of the high
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* register.
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*/
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frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(pipe), PIPEFRAME(pipe));
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pixel = frame & PIPE_PIXEL_MASK;
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frame = (frame >> PIPE_FRAME_LOW_SHIFT) & 0xffffff;
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/*
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* The frame counter increments at beginning of active.
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* Cook up a vblank counter by also checking the pixel
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* counter against vblank start.
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*/
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return (frame + (pixel >= vbl_start)) & 0xffffff;
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}
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u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->dev);
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struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
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enum pipe pipe = to_intel_crtc(crtc)->pipe;
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if (!vblank->max_vblank_count)
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return 0;
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return intel_de_read(dev_priv, PIPE_FRMCOUNT_G4X(pipe));
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}
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static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct drm_vblank_crtc *vblank =
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&crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
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const struct drm_display_mode *mode = &vblank->hwmode;
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u32 htotal = mode->crtc_htotal;
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u32 clock = mode->crtc_clock;
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u32 scan_prev_time, scan_curr_time, scan_post_time;
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/*
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* To avoid the race condition where we might cross into the
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* next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
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* reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
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* during the same frame.
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*/
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do {
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/*
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* This field provides read back of the display
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* pipe frame time stamp. The time stamp value
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* is sampled at every start of vertical blank.
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*/
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scan_prev_time = intel_de_read_fw(dev_priv,
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PIPE_FRMTMSTMP(crtc->pipe));
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/*
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* The TIMESTAMP_CTR register has the current
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* time stamp value.
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*/
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scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR);
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scan_post_time = intel_de_read_fw(dev_priv,
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PIPE_FRMTMSTMP(crtc->pipe));
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} while (scan_post_time != scan_prev_time);
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return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
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clock), 1000 * htotal);
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}
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/*
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* On certain encoders on certain platforms, pipe
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* scanline register will not work to get the scanline,
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* since the timings are driven from the PORT or issues
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* with scanline register updates.
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* This function will use Framestamp and current
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* timestamp registers to calculate the scanline.
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*/
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static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
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{
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struct drm_vblank_crtc *vblank =
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&crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
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const struct drm_display_mode *mode = &vblank->hwmode;
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u32 vblank_start = mode->crtc_vblank_start;
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u32 vtotal = mode->crtc_vtotal;
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u32 scanline;
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scanline = intel_crtc_scanlines_since_frame_timestamp(crtc);
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scanline = min(scanline, vtotal - 1);
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scanline = (scanline + vblank_start) % vtotal;
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return scanline;
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}
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/*
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* intel_de_read_fw(), only for fast reads of display block, no need for
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* forcewake etc.
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*/
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static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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const struct drm_display_mode *mode;
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struct drm_vblank_crtc *vblank;
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enum pipe pipe = crtc->pipe;
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int position, vtotal;
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if (!crtc->active)
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return 0;
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vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
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mode = &vblank->hwmode;
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if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
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return __intel_get_crtc_scanline_from_timestamp(crtc);
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vtotal = mode->crtc_vtotal;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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vtotal /= 2;
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position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;
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/*
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* On HSW, the DSL reg (0x70000) appears to return 0 if we
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* read it just before the start of vblank. So try it again
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* so we don't accidentally end up spanning a vblank frame
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* increment, causing the pipe_update_end() code to squak at us.
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*
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* The nature of this problem means we can't simply check the ISR
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* bit and return the vblank start value; nor can we use the scanline
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* debug register in the transcoder as it appears to have the same
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* problem. We may need to extend this to include other platforms,
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* but so far testing only shows the problem on HSW.
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*/
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if (HAS_DDI(dev_priv) && !position) {
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int i, temp;
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for (i = 0; i < 100; i++) {
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udelay(1);
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temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;
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if (temp != position) {
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position = temp;
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break;
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}
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}
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}
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/*
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* See update_scanline_offset() for the details on the
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* scanline_offset adjustment.
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*/
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return (position + crtc->scanline_offset) % vtotal;
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}
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static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
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bool in_vblank_irq,
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int *vpos, int *hpos,
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ktime_t *stime, ktime_t *etime,
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const struct drm_display_mode *mode)
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{
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struct drm_device *dev = _crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *crtc = to_intel_crtc(_crtc);
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enum pipe pipe = crtc->pipe;
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int position;
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int vbl_start, vbl_end, hsync_start, htotal, vtotal;
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unsigned long irqflags;
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bool use_scanline_counter = DISPLAY_VER(dev_priv) >= 5 ||
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IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) == 2 ||
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crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
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if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
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drm_dbg(&dev_priv->drm,
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"trying to get scanoutpos for disabled pipe %c\n",
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pipe_name(pipe));
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return false;
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}
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htotal = mode->crtc_htotal;
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hsync_start = mode->crtc_hsync_start;
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vtotal = mode->crtc_vtotal;
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vbl_start = mode->crtc_vblank_start;
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vbl_end = mode->crtc_vblank_end;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
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vbl_start = DIV_ROUND_UP(vbl_start, 2);
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vbl_end /= 2;
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vtotal /= 2;
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}
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/*
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* Lock uncore.lock, as we will do multiple timing critical raw
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* register reads, potentially with preemption disabled, so the
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* following code must not block on uncore.lock.
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*/
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spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
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/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
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/* Get optional system timestamp before query. */
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if (stime)
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*stime = ktime_get();
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if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
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int scanlines = intel_crtc_scanlines_since_frame_timestamp(crtc);
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position = __intel_get_crtc_scanline(crtc);
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/*
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* Already exiting vblank? If so, shift our position
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* so it looks like we're already apporaching the full
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* vblank end. This should make the generated timestamp
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* more or less match when the active portion will start.
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*/
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if (position >= vbl_start && scanlines < position)
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position = min(crtc->vmax_vblank_start + scanlines, vtotal - 1);
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} else if (use_scanline_counter) {
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/* No obvious pixelcount register. Only query vertical
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* scanout position from Display scan line register.
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*/
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position = __intel_get_crtc_scanline(crtc);
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} else {
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/*
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* Have access to pixelcount since start of frame.
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* We can split this into vertical and horizontal
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* scanout position.
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*/
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position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
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/* convert to pixel counts */
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vbl_start *= htotal;
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vbl_end *= htotal;
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vtotal *= htotal;
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/*
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* In interlaced modes, the pixel counter counts all pixels,
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* so one field will have htotal more pixels. In order to avoid
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* the reported position from jumping backwards when the pixel
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* counter is beyond the length of the shorter field, just
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* clamp the position the length of the shorter field. This
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* matches how the scanline counter based position works since
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* the scanline counter doesn't count the two half lines.
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*/
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position = min(position, vtotal - 1);
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/*
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* Start of vblank interrupt is triggered at start of hsync,
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* just prior to the first active line of vblank. However we
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* consider lines to start at the leading edge of horizontal
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* active. So, should we get here before we've crossed into
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* the horizontal active of the first line in vblank, we would
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* not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
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* always add htotal-hsync_start to the current pixel position.
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*/
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position = (position + htotal - hsync_start) % vtotal;
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}
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/* Get optional system timestamp after query. */
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if (etime)
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*etime = ktime_get();
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/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
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spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
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/*
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* While in vblank, position will be negative
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* counting up towards 0 at vbl_end. And outside
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* vblank, position will be positive counting
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* up since vbl_end.
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*/
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if (position >= vbl_start)
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position -= vbl_end;
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else
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position += vtotal - vbl_end;
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if (use_scanline_counter) {
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*vpos = position;
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*hpos = 0;
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} else {
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*vpos = position / htotal;
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*hpos = position - (*vpos * htotal);
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}
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return true;
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}
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bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
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ktime_t *vblank_time, bool in_vblank_irq)
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{
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return drm_crtc_vblank_helper_get_vblank_timestamp_internal(
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crtc, max_error, vblank_time, in_vblank_irq,
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i915_get_crtc_scanoutpos);
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}
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int intel_get_crtc_scanline(struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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unsigned long irqflags;
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int position;
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spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
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position = __intel_get_crtc_scanline(crtc);
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spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
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return position;
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}
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static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
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enum pipe pipe)
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{
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i915_reg_t reg = PIPEDSL(pipe);
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u32 line1, line2;
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line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
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msleep(5);
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line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
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return line1 != line2;
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}
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static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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enum pipe pipe = crtc->pipe;
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/* Wait for the display line to settle/start moving */
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if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
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drm_err(&dev_priv->drm,
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"pipe %c scanline %s wait timed out\n",
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pipe_name(pipe), str_on_off(state));
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}
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void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
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{
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wait_for_pipe_scanline_moving(crtc, false);
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}
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void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
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{
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wait_for_pipe_scanline_moving(crtc, true);
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}
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static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
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const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
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/*
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* The scanline counter increments at the leading edge of hsync.
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*
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* On most platforms it starts counting from vtotal-1 on the
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* first active line. That means the scanline counter value is
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* always one less than what we would expect. Ie. just after
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* start of vblank, which also occurs at start of hsync (on the
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* last active line), the scanline counter will read vblank_start-1.
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*
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* On gen2 the scanline counter starts counting from 1 instead
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* of vtotal-1, so we have to subtract one (or rather add vtotal-1
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* to keep the value positive), instead of adding one.
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*
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* On HSW+ the behaviour of the scanline counter depends on the output
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* type. For DP ports it behaves like most other platforms, but on HDMI
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* there's an extra 1 line difference. So we need to add two instead of
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* one to the value.
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*
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* On VLV/CHV DSI the scanline counter would appear to increment
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* approx. 1/3 of a scanline before start of vblank. Unfortunately
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* that means we can't tell whether we're in vblank or not while
|
|
* we're on that particular line. We must still set scanline_offset
|
|
* to 1 so that the vblank timestamps come out correct when we query
|
|
* the scanline counter from within the vblank interrupt handler.
|
|
* However if queried just before the start of vblank we'll get an
|
|
* answer that's slightly in the future.
|
|
*/
|
|
if (DISPLAY_VER(i915) == 2) {
|
|
int vtotal;
|
|
|
|
vtotal = adjusted_mode->crtc_vtotal;
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
|
|
vtotal /= 2;
|
|
|
|
return vtotal - 1;
|
|
} else if (HAS_DDI(i915) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
|
|
return 2;
|
|
} else {
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
|
|
bool vrr_enable)
|
|
{
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
|
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
|
|
u8 mode_flags = crtc_state->mode_flags;
|
|
struct drm_display_mode adjusted_mode;
|
|
int vmax_vblank_start = 0;
|
|
unsigned long irqflags;
|
|
|
|
drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode);
|
|
|
|
if (vrr_enable) {
|
|
drm_WARN_ON(&i915->drm, (mode_flags & I915_MODE_FLAG_VRR) == 0);
|
|
|
|
adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
|
|
adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
|
|
adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
|
|
vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
|
|
} else {
|
|
mode_flags &= ~I915_MODE_FLAG_VRR;
|
|
}
|
|
|
|
/*
|
|
* Belts and suspenders locking to guarantee everyone sees 100%
|
|
* consistent state during fastset seamless refresh rate changes.
|
|
*
|
|
* vblank_time_lock takes care of all drm_vblank.c stuff, and
|
|
* uncore.lock takes care of __intel_get_crtc_scanline() which
|
|
* may get called elsewhere as well.
|
|
*
|
|
* TODO maybe just protect everything (including
|
|
* __intel_get_crtc_scanline()) with vblank_time_lock?
|
|
* Need to audit everything to make sure it's safe.
|
|
*/
|
|
spin_lock_irqsave(&i915->drm.vblank_time_lock, irqflags);
|
|
spin_lock(&i915->uncore.lock);
|
|
|
|
drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);
|
|
|
|
crtc->vmax_vblank_start = vmax_vblank_start;
|
|
|
|
crtc->mode_flags = mode_flags;
|
|
|
|
crtc->scanline_offset = intel_crtc_scanline_offset(crtc_state);
|
|
|
|
spin_unlock(&i915->uncore.lock);
|
|
spin_unlock_irqrestore(&i915->drm.vblank_time_lock, irqflags);
|
|
}
|