485 lines
15 KiB
C
485 lines
15 KiB
C
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <linux/string_helpers.h>
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#include <drm/drm_print.h>
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#include <drm/i915_pciids.h>
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#include "display/intel_display_device.h"
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#include "gt/intel_gt_regs.h"
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "i915_utils.h"
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#include "intel_device_info.h"
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#define PLATFORM_NAME(x) [INTEL_##x] = #x
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static const char * const platform_names[] = {
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PLATFORM_NAME(I830),
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PLATFORM_NAME(I845G),
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PLATFORM_NAME(I85X),
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PLATFORM_NAME(I865G),
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PLATFORM_NAME(I915G),
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PLATFORM_NAME(I915GM),
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PLATFORM_NAME(I945G),
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PLATFORM_NAME(I945GM),
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PLATFORM_NAME(G33),
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PLATFORM_NAME(PINEVIEW),
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PLATFORM_NAME(I965G),
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PLATFORM_NAME(I965GM),
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PLATFORM_NAME(G45),
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PLATFORM_NAME(GM45),
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PLATFORM_NAME(IRONLAKE),
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PLATFORM_NAME(SANDYBRIDGE),
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PLATFORM_NAME(IVYBRIDGE),
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PLATFORM_NAME(VALLEYVIEW),
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PLATFORM_NAME(HASWELL),
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PLATFORM_NAME(BROADWELL),
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PLATFORM_NAME(CHERRYVIEW),
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PLATFORM_NAME(SKYLAKE),
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PLATFORM_NAME(BROXTON),
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PLATFORM_NAME(KABYLAKE),
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PLATFORM_NAME(GEMINILAKE),
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PLATFORM_NAME(COFFEELAKE),
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PLATFORM_NAME(COMETLAKE),
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PLATFORM_NAME(ICELAKE),
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PLATFORM_NAME(ELKHARTLAKE),
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PLATFORM_NAME(JASPERLAKE),
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PLATFORM_NAME(TIGERLAKE),
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PLATFORM_NAME(ROCKETLAKE),
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PLATFORM_NAME(DG1),
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PLATFORM_NAME(ALDERLAKE_S),
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PLATFORM_NAME(ALDERLAKE_P),
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PLATFORM_NAME(XEHPSDV),
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PLATFORM_NAME(DG2),
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PLATFORM_NAME(PONTEVECCHIO),
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PLATFORM_NAME(METEORLAKE),
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};
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#undef PLATFORM_NAME
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const char *intel_platform_name(enum intel_platform platform)
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{
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BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
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if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
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platform_names[platform] == NULL))
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return "<unknown>";
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return platform_names[platform];
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}
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void intel_device_info_print(const struct intel_device_info *info,
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const struct intel_runtime_info *runtime,
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struct drm_printer *p)
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{
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const struct intel_display_runtime_info *display_runtime =
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&info->display->__runtime_defaults;
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if (runtime->graphics.ip.rel)
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drm_printf(p, "graphics version: %u.%02u\n",
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runtime->graphics.ip.ver,
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runtime->graphics.ip.rel);
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else
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drm_printf(p, "graphics version: %u\n",
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runtime->graphics.ip.ver);
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if (runtime->media.ip.rel)
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drm_printf(p, "media version: %u.%02u\n",
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runtime->media.ip.ver,
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runtime->media.ip.rel);
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else
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drm_printf(p, "media version: %u\n",
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runtime->media.ip.ver);
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if (display_runtime->ip.rel)
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drm_printf(p, "display version: %u.%02u\n",
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display_runtime->ip.ver,
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display_runtime->ip.rel);
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else
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drm_printf(p, "display version: %u\n",
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display_runtime->ip.ver);
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drm_printf(p, "graphics stepping: %s\n", intel_step_name(runtime->step.graphics_step));
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drm_printf(p, "media stepping: %s\n", intel_step_name(runtime->step.media_step));
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drm_printf(p, "display stepping: %s\n", intel_step_name(runtime->step.display_step));
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drm_printf(p, "base die stepping: %s\n", intel_step_name(runtime->step.basedie_step));
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drm_printf(p, "gt: %d\n", info->gt);
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drm_printf(p, "memory-regions: 0x%x\n", runtime->memory_regions);
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drm_printf(p, "page-sizes: 0x%x\n", runtime->page_sizes);
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drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
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drm_printf(p, "ppgtt-size: %d\n", runtime->ppgtt_size);
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drm_printf(p, "ppgtt-type: %d\n", runtime->ppgtt_type);
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drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);
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#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name))
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DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
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#undef PRINT_FLAG
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drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu));
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#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display->name))
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DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
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#undef PRINT_FLAG
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drm_printf(p, "has_hdcp: %s\n", str_yes_no(display_runtime->has_hdcp));
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drm_printf(p, "has_dmc: %s\n", str_yes_no(display_runtime->has_dmc));
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drm_printf(p, "has_dsc: %s\n", str_yes_no(display_runtime->has_dsc));
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drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
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}
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#undef INTEL_VGA_DEVICE
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#define INTEL_VGA_DEVICE(id, info) (id)
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static const u16 subplatform_ult_ids[] = {
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INTEL_HSW_ULT_GT1_IDS(0),
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INTEL_HSW_ULT_GT2_IDS(0),
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INTEL_HSW_ULT_GT3_IDS(0),
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INTEL_BDW_ULT_GT1_IDS(0),
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INTEL_BDW_ULT_GT2_IDS(0),
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INTEL_BDW_ULT_GT3_IDS(0),
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INTEL_BDW_ULT_RSVD_IDS(0),
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INTEL_SKL_ULT_GT1_IDS(0),
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INTEL_SKL_ULT_GT2_IDS(0),
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INTEL_SKL_ULT_GT3_IDS(0),
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INTEL_KBL_ULT_GT1_IDS(0),
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INTEL_KBL_ULT_GT2_IDS(0),
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INTEL_KBL_ULT_GT3_IDS(0),
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INTEL_CFL_U_GT2_IDS(0),
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INTEL_CFL_U_GT3_IDS(0),
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INTEL_WHL_U_GT1_IDS(0),
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INTEL_WHL_U_GT2_IDS(0),
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INTEL_WHL_U_GT3_IDS(0),
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INTEL_CML_U_GT1_IDS(0),
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INTEL_CML_U_GT2_IDS(0),
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};
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static const u16 subplatform_ulx_ids[] = {
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INTEL_HSW_ULX_GT1_IDS(0),
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INTEL_HSW_ULX_GT2_IDS(0),
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INTEL_BDW_ULX_GT1_IDS(0),
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INTEL_BDW_ULX_GT2_IDS(0),
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INTEL_BDW_ULX_GT3_IDS(0),
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INTEL_BDW_ULX_RSVD_IDS(0),
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INTEL_SKL_ULX_GT1_IDS(0),
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INTEL_SKL_ULX_GT2_IDS(0),
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INTEL_KBL_ULX_GT1_IDS(0),
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INTEL_KBL_ULX_GT2_IDS(0),
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INTEL_AML_KBL_GT2_IDS(0),
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INTEL_AML_CFL_GT2_IDS(0),
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};
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static const u16 subplatform_portf_ids[] = {
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INTEL_ICL_PORT_F_IDS(0),
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};
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static const u16 subplatform_uy_ids[] = {
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INTEL_TGL_12_GT2_IDS(0),
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};
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static const u16 subplatform_n_ids[] = {
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INTEL_ADLN_IDS(0),
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};
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static const u16 subplatform_rpl_ids[] = {
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INTEL_RPLS_IDS(0),
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INTEL_RPLP_IDS(0),
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};
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static const u16 subplatform_rplu_ids[] = {
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INTEL_RPLU_IDS(0),
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};
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static const u16 subplatform_g10_ids[] = {
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INTEL_DG2_G10_IDS(0),
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INTEL_ATS_M150_IDS(0),
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};
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static const u16 subplatform_g11_ids[] = {
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INTEL_DG2_G11_IDS(0),
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INTEL_ATS_M75_IDS(0),
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};
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static const u16 subplatform_g12_ids[] = {
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INTEL_DG2_G12_IDS(0),
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};
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static const u16 subplatform_m_ids[] = {
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INTEL_MTL_M_IDS(0),
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};
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static const u16 subplatform_p_ids[] = {
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INTEL_MTL_P_IDS(0),
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};
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static bool find_devid(u16 id, const u16 *p, unsigned int num)
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{
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for (; num; num--, p++) {
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if (*p == id)
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return true;
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}
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return false;
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}
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static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
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{
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const struct intel_device_info *info = INTEL_INFO(i915);
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const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
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const unsigned int pi = __platform_mask_index(rinfo, info->platform);
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const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
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u16 devid = INTEL_DEVID(i915);
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u32 mask = 0;
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/* Make sure IS_<platform> checks are working. */
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RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
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/* Find and mark subplatform bits based on the PCI device id. */
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if (find_devid(devid, subplatform_ult_ids,
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ARRAY_SIZE(subplatform_ult_ids))) {
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mask = BIT(INTEL_SUBPLATFORM_ULT);
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} else if (find_devid(devid, subplatform_ulx_ids,
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ARRAY_SIZE(subplatform_ulx_ids))) {
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mask = BIT(INTEL_SUBPLATFORM_ULX);
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if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
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/* ULX machines are also considered ULT. */
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mask |= BIT(INTEL_SUBPLATFORM_ULT);
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}
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} else if (find_devid(devid, subplatform_portf_ids,
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ARRAY_SIZE(subplatform_portf_ids))) {
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mask = BIT(INTEL_SUBPLATFORM_PORTF);
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} else if (find_devid(devid, subplatform_uy_ids,
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ARRAY_SIZE(subplatform_uy_ids))) {
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mask = BIT(INTEL_SUBPLATFORM_UY);
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} else if (find_devid(devid, subplatform_n_ids,
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ARRAY_SIZE(subplatform_n_ids))) {
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mask = BIT(INTEL_SUBPLATFORM_N);
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} else if (find_devid(devid, subplatform_rpl_ids,
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ARRAY_SIZE(subplatform_rpl_ids))) {
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mask = BIT(INTEL_SUBPLATFORM_RPL);
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if (find_devid(devid, subplatform_rplu_ids,
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ARRAY_SIZE(subplatform_rplu_ids)))
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mask |= BIT(INTEL_SUBPLATFORM_RPLU);
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} else if (find_devid(devid, subplatform_g10_ids,
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ARRAY_SIZE(subplatform_g10_ids))) {
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mask = BIT(INTEL_SUBPLATFORM_G10);
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} else if (find_devid(devid, subplatform_g11_ids,
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ARRAY_SIZE(subplatform_g11_ids))) {
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mask = BIT(INTEL_SUBPLATFORM_G11);
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} else if (find_devid(devid, subplatform_g12_ids,
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ARRAY_SIZE(subplatform_g12_ids))) {
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mask = BIT(INTEL_SUBPLATFORM_G12);
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} else if (find_devid(devid, subplatform_m_ids,
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ARRAY_SIZE(subplatform_m_ids))) {
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mask = BIT(INTEL_SUBPLATFORM_M);
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} else if (find_devid(devid, subplatform_p_ids,
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ARRAY_SIZE(subplatform_p_ids))) {
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mask = BIT(INTEL_SUBPLATFORM_P);
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}
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GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
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RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
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}
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static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_ip_version *ip)
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{
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struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
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void __iomem *addr;
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u32 val;
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u8 expected_ver = ip->ver;
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u8 expected_rel = ip->rel;
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addr = pci_iomap_range(pdev, 0, offset, sizeof(u32));
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if (drm_WARN_ON(&i915->drm, !addr))
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return;
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val = ioread32(addr);
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pci_iounmap(pdev, addr);
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ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
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ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
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ip->step = REG_FIELD_GET(GMD_ID_STEP, val);
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/* Sanity check against expected versions from device info */
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if (IP_VER(ip->ver, ip->rel) < IP_VER(expected_ver, expected_rel))
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drm_dbg(&i915->drm,
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"Hardware reports GMD IP version %u.%u (REG[0x%x] = 0x%08x) but minimum expected is %u.%u\n",
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ip->ver, ip->rel, offset, val, expected_ver, expected_rel);
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}
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/*
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* Setup the graphics version for the current device. This must be done before
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* any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this
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* function should be called very early in the driver initialization sequence.
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*
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* Regular MMIO access is not yet setup at the point this function is called so
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* we peek at the appropriate MMIO offset directly. The GMD_ID register is
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* part of an 'always on' power well by design, so we don't need to worry about
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* forcewake while reading it.
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*/
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static void intel_ipver_early_init(struct drm_i915_private *i915)
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{
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struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
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if (!HAS_GMD_ID(i915)) {
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drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12);
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/*
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* On older platforms, graphics and media share the same ip
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* version and release.
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*/
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RUNTIME_INFO(i915)->media.ip =
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RUNTIME_INFO(i915)->graphics.ip;
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return;
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}
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ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS),
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&runtime->graphics.ip);
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/* Wa_22012778468 */
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if (runtime->graphics.ip.ver == 0x0 &&
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INTEL_INFO(i915)->platform == INTEL_METEORLAKE) {
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RUNTIME_INFO(i915)->graphics.ip.ver = 12;
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RUNTIME_INFO(i915)->graphics.ip.rel = 70;
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}
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ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
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&runtime->media.ip);
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}
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/**
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* intel_device_info_runtime_init_early - initialize early runtime info
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* @i915: the i915 device
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*
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* Determine early intel_device_info fields at runtime. This function needs
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* to be called before the MMIO has been setup.
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*/
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void intel_device_info_runtime_init_early(struct drm_i915_private *i915)
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{
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intel_ipver_early_init(i915);
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intel_device_info_subplatform_init(i915);
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}
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/* FIXME: Remove this, and make device info a const pointer to rodata. */
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static struct intel_device_info *
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mkwrite_device_info(struct drm_i915_private *i915)
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{
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return (struct intel_device_info *)INTEL_INFO(i915);
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}
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static const struct intel_display_device_info no_display = {};
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/**
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* intel_device_info_runtime_init - initialize runtime info
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* @dev_priv: the i915 device
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*
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* Determine various intel_device_info fields at runtime.
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*
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* Use it when either:
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* - it's judged too laborious to fill n static structures with the limit
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* when a simple if statement does the job,
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* - run-time checks (eg read fuse/strap registers) are needed.
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*
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* This function needs to be called:
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* - after the MMIO has been setup as we are reading registers,
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* - after the PCH has been detected,
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* - before the first usage of the fields it can tweak.
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*/
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void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
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{
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struct intel_device_info *info = mkwrite_device_info(dev_priv);
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struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
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if (HAS_DISPLAY(dev_priv))
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intel_display_device_info_runtime_init(dev_priv);
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/* Display may have been disabled by runtime init */
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if (!HAS_DISPLAY(dev_priv)) {
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dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
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DRIVER_ATOMIC);
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info->display = &no_display;
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}
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/* Disable nuclear pageflip by default on pre-g4x */
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if (!dev_priv->params.nuclear_pageflip &&
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DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
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dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
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BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
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if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) {
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drm_info(&dev_priv->drm,
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"Disabling ppGTT for VT-d support\n");
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runtime->ppgtt_type = INTEL_PPGTT_NONE;
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}
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runtime->rawclk_freq = intel_read_rawclk(dev_priv);
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drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
|
|
|
|
}
|
|
|
|
/*
|
|
* Set up device info and initial runtime info at driver create.
|
|
*
|
|
* Note: i915 is only an allocated blob of memory at this point.
|
|
*/
|
|
void intel_device_info_driver_create(struct drm_i915_private *i915,
|
|
u16 device_id,
|
|
const struct intel_device_info *match_info)
|
|
{
|
|
struct intel_device_info *info;
|
|
struct intel_runtime_info *runtime;
|
|
u16 ver, rel, step;
|
|
|
|
/* Setup the write-once "constant" device info */
|
|
info = mkwrite_device_info(i915);
|
|
memcpy(info, match_info, sizeof(*info));
|
|
|
|
/* Initialize initial runtime info from static const data and pdev. */
|
|
runtime = RUNTIME_INFO(i915);
|
|
memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
|
|
|
|
/* Probe display support */
|
|
info->display = intel_display_device_probe(i915, info->has_gmd_id,
|
|
&ver, &rel, &step);
|
|
memcpy(DISPLAY_RUNTIME_INFO(i915),
|
|
&DISPLAY_INFO(i915)->__runtime_defaults,
|
|
sizeof(*DISPLAY_RUNTIME_INFO(i915)));
|
|
|
|
if (info->has_gmd_id) {
|
|
DISPLAY_RUNTIME_INFO(i915)->ip.ver = ver;
|
|
DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel;
|
|
DISPLAY_RUNTIME_INFO(i915)->ip.step = step;
|
|
}
|
|
|
|
runtime->device_id = device_id;
|
|
}
|
|
|
|
void intel_driver_caps_print(const struct intel_driver_caps *caps,
|
|
struct drm_printer *p)
|
|
{
|
|
drm_printf(p, "Has logical contexts? %s\n",
|
|
str_yes_no(caps->has_logical_contexts));
|
|
drm_printf(p, "scheduler: 0x%x\n", caps->scheduler);
|
|
}
|