578 lines
14 KiB
C
578 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (C) 2014 Endless Mobile
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*
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* Written by:
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* Jasper St. Pierre <jstpierre@mecheye.net>
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*/
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#include <linux/component.h>
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#include <linux/module.h>
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#include <linux/of_graph.h>
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#include <linux/sys_soc.h>
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#include <linux/platform_device.h>
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#include <linux/soc/amlogic/meson-canvas.h>
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#include <drm/drm_aperture.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_drv.h>
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#include <drm/drm_fbdev_dma.h>
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#include <drm/drm_gem_dma_helper.h>
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#include <drm/drm_gem_framebuffer_helper.h>
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#include <drm/drm_modeset_helper_vtables.h>
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#include <drm/drm_module.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drm_vblank.h>
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#include "meson_crtc.h"
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#include "meson_drv.h"
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#include "meson_overlay.h"
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#include "meson_plane.h"
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#include "meson_osd_afbcd.h"
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#include "meson_registers.h"
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#include "meson_encoder_cvbs.h"
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#include "meson_encoder_hdmi.h"
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#include "meson_encoder_dsi.h"
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#include "meson_viu.h"
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#include "meson_vpp.h"
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#include "meson_rdma.h"
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#define DRIVER_NAME "meson"
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#define DRIVER_DESC "Amlogic Meson DRM driver"
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/**
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* DOC: Video Processing Unit
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*
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* VPU Handles the Global Video Processing, it includes management of the
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* clocks gates, blocks reset lines and power domains.
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*
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* What is missing :
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*
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* - Full reset of entire video processing HW blocks
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* - Scaling and setup of the VPU clock
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* - Bus clock gates
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* - Powering up video processing HW blocks
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* - Powering Up HDMI controller and PHY
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*/
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static const struct drm_mode_config_funcs meson_mode_config_funcs = {
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.atomic_check = drm_atomic_helper_check,
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.atomic_commit = drm_atomic_helper_commit,
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.fb_create = drm_gem_fb_create,
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};
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static const struct drm_mode_config_helper_funcs meson_mode_config_helpers = {
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.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
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};
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static irqreturn_t meson_irq(int irq, void *arg)
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{
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struct drm_device *dev = arg;
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struct meson_drm *priv = dev->dev_private;
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(void)readl_relaxed(priv->io_base + _REG(VENC_INTFLAG));
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meson_crtc_irq(priv);
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return IRQ_HANDLED;
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}
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static int meson_dumb_create(struct drm_file *file, struct drm_device *dev,
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struct drm_mode_create_dumb *args)
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{
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/*
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* We need 64bytes aligned stride, and PAGE aligned size
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*/
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args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), SZ_64);
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args->size = PAGE_ALIGN(args->pitch * args->height);
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return drm_gem_dma_dumb_create_internal(file, dev, args);
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}
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DEFINE_DRM_GEM_DMA_FOPS(fops);
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static const struct drm_driver meson_driver = {
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.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
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/* DMA Ops */
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DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(meson_dumb_create),
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/* Misc */
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.fops = &fops,
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.name = DRIVER_NAME,
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.desc = DRIVER_DESC,
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.date = "20161109",
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.major = 1,
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.minor = 0,
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};
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static bool meson_vpu_has_available_connectors(struct device *dev)
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{
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struct device_node *ep, *remote;
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/* Parses each endpoint and check if remote exists */
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for_each_endpoint_of_node(dev->of_node, ep) {
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/* If the endpoint node exists, consider it enabled */
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remote = of_graph_get_remote_port(ep);
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if (remote) {
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of_node_put(remote);
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of_node_put(ep);
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return true;
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}
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}
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return false;
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}
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static struct regmap_config meson_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = 0x1000,
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};
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static void meson_vpu_init(struct meson_drm *priv)
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{
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u32 value;
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/*
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* Slave dc0 and dc5 connected to master port 1.
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* By default other slaves are connected to master port 0.
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*/
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value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) |
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VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1);
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writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1));
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/* Slave dc0 connected to master port 1 */
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value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1);
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writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2));
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/* Slave dc4 and dc7 connected to master port 1 */
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value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) |
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VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1);
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writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1));
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/* Slave dc1 connected to master port 1 */
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value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1);
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writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
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}
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struct meson_drm_soc_attr {
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struct meson_drm_soc_limits limits;
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const struct soc_device_attribute *attrs;
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};
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static const struct meson_drm_soc_attr meson_drm_soc_attrs[] = {
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/* S805X/S805Y HDMI PLL won't lock for HDMI PHY freq > 1,65GHz */
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{
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.limits = {
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.max_hdmi_phy_freq = 1650000,
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},
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.attrs = (const struct soc_device_attribute []) {
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{ .soc_id = "GXL (S805*)", },
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{ /* sentinel */ }
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}
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},
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};
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static int meson_drv_bind_master(struct device *dev, bool has_components)
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{
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struct platform_device *pdev = to_platform_device(dev);
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const struct meson_drm_match_data *match;
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struct meson_drm *priv;
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struct drm_device *drm;
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struct resource *res;
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void __iomem *regs;
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int ret, i;
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/* Checks if an output connector is available */
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if (!meson_vpu_has_available_connectors(dev)) {
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dev_err(dev, "No output connector available\n");
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return -ENODEV;
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}
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match = of_device_get_match_data(dev);
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if (!match)
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return -ENODEV;
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drm = drm_dev_alloc(&meson_driver, dev);
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if (IS_ERR(drm))
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return PTR_ERR(drm);
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv) {
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ret = -ENOMEM;
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goto free_drm;
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}
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drm->dev_private = priv;
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priv->drm = drm;
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priv->dev = dev;
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priv->compat = match->compat;
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priv->afbcd.ops = match->afbcd_ops;
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regs = devm_platform_ioremap_resource_byname(pdev, "vpu");
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if (IS_ERR(regs)) {
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ret = PTR_ERR(regs);
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goto free_drm;
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}
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priv->io_base = regs;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi");
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if (!res) {
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ret = -EINVAL;
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goto free_drm;
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}
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/* Simply ioremap since it may be a shared register zone */
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regs = devm_ioremap(dev, res->start, resource_size(res));
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if (!regs) {
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ret = -EADDRNOTAVAIL;
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goto free_drm;
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}
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priv->hhi = devm_regmap_init_mmio(dev, regs,
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&meson_regmap_config);
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if (IS_ERR(priv->hhi)) {
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dev_err(&pdev->dev, "Couldn't create the HHI regmap\n");
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ret = PTR_ERR(priv->hhi);
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goto free_drm;
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}
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priv->canvas = meson_canvas_get(dev);
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if (IS_ERR(priv->canvas)) {
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ret = PTR_ERR(priv->canvas);
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goto free_drm;
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}
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ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1);
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if (ret)
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goto free_drm;
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ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0);
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if (ret) {
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meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
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goto free_drm;
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}
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ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1);
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if (ret) {
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meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
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meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
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goto free_drm;
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}
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ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2);
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if (ret) {
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meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
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meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
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meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
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goto free_drm;
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}
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priv->vsync_irq = platform_get_irq(pdev, 0);
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ret = drm_vblank_init(drm, 1);
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if (ret)
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goto free_drm;
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/* Assign limits per soc revision/package */
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for (i = 0 ; i < ARRAY_SIZE(meson_drm_soc_attrs) ; ++i) {
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if (soc_device_match(meson_drm_soc_attrs[i].attrs)) {
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priv->limits = &meson_drm_soc_attrs[i].limits;
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break;
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}
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}
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/*
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* Remove early framebuffers (ie. simplefb). The framebuffer can be
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* located anywhere in RAM
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*/
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ret = drm_aperture_remove_framebuffers(&meson_driver);
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if (ret)
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goto free_drm;
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ret = drmm_mode_config_init(drm);
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if (ret)
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goto free_drm;
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drm->mode_config.max_width = 3840;
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drm->mode_config.max_height = 2160;
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drm->mode_config.funcs = &meson_mode_config_funcs;
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drm->mode_config.helper_private = &meson_mode_config_helpers;
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/* Hardware Initialization */
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meson_vpu_init(priv);
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meson_venc_init(priv);
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meson_vpp_init(priv);
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meson_viu_init(priv);
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if (priv->afbcd.ops) {
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ret = priv->afbcd.ops->init(priv);
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if (ret)
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goto free_drm;
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}
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/* Encoder Initialization */
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ret = meson_encoder_cvbs_init(priv);
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if (ret)
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goto exit_afbcd;
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if (has_components) {
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ret = component_bind_all(dev, drm);
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if (ret) {
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dev_err(drm->dev, "Couldn't bind all components\n");
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/* Do not try to unbind */
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has_components = false;
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goto exit_afbcd;
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}
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}
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ret = meson_encoder_hdmi_init(priv);
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if (ret)
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goto exit_afbcd;
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if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
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ret = meson_encoder_dsi_init(priv);
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if (ret)
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goto exit_afbcd;
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}
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ret = meson_plane_create(priv);
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if (ret)
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goto exit_afbcd;
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ret = meson_overlay_create(priv);
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if (ret)
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goto exit_afbcd;
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ret = meson_crtc_create(priv);
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if (ret)
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goto exit_afbcd;
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ret = request_irq(priv->vsync_irq, meson_irq, 0, drm->driver->name, drm);
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if (ret)
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goto exit_afbcd;
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drm_mode_config_reset(drm);
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drm_kms_helper_poll_init(drm);
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platform_set_drvdata(pdev, priv);
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ret = drm_dev_register(drm, 0);
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if (ret)
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goto uninstall_irq;
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drm_fbdev_dma_setup(drm, 32);
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return 0;
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uninstall_irq:
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free_irq(priv->vsync_irq, drm);
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exit_afbcd:
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if (priv->afbcd.ops)
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priv->afbcd.ops->exit(priv);
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free_drm:
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drm_dev_put(drm);
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meson_encoder_dsi_remove(priv);
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meson_encoder_hdmi_remove(priv);
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meson_encoder_cvbs_remove(priv);
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if (has_components)
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component_unbind_all(dev, drm);
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return ret;
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}
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static int meson_drv_bind(struct device *dev)
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{
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return meson_drv_bind_master(dev, true);
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}
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static void meson_drv_unbind(struct device *dev)
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{
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struct meson_drm *priv = dev_get_drvdata(dev);
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struct drm_device *drm = priv->drm;
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if (priv->canvas) {
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meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
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meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
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meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
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meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2);
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}
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drm_dev_unregister(drm);
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drm_kms_helper_poll_fini(drm);
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drm_atomic_helper_shutdown(drm);
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free_irq(priv->vsync_irq, drm);
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drm_dev_put(drm);
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meson_encoder_dsi_remove(priv);
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meson_encoder_hdmi_remove(priv);
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meson_encoder_cvbs_remove(priv);
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component_unbind_all(dev, drm);
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if (priv->afbcd.ops)
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priv->afbcd.ops->exit(priv);
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}
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static const struct component_master_ops meson_drv_master_ops = {
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.bind = meson_drv_bind,
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.unbind = meson_drv_unbind,
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};
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static int __maybe_unused meson_drv_pm_suspend(struct device *dev)
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{
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struct meson_drm *priv = dev_get_drvdata(dev);
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if (!priv)
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return 0;
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return drm_mode_config_helper_suspend(priv->drm);
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}
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static int __maybe_unused meson_drv_pm_resume(struct device *dev)
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{
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struct meson_drm *priv = dev_get_drvdata(dev);
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if (!priv)
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return 0;
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meson_vpu_init(priv);
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meson_venc_init(priv);
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meson_vpp_init(priv);
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meson_viu_init(priv);
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if (priv->afbcd.ops)
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priv->afbcd.ops->init(priv);
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return drm_mode_config_helper_resume(priv->drm);
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}
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static void meson_drv_shutdown(struct platform_device *pdev)
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{
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struct meson_drm *priv = dev_get_drvdata(&pdev->dev);
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if (!priv)
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return;
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drm_kms_helper_poll_fini(priv->drm);
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drm_atomic_helper_shutdown(priv->drm);
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}
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/*
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* Only devices to use as components
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* TOFIX: get rid of components when we can finally
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* get meson_dx_hdmi to stop using the meson_drm
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* private structure for HHI registers.
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*/
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static const struct of_device_id components_dev_match[] = {
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{ .compatible = "amlogic,meson-gxbb-dw-hdmi" },
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{ .compatible = "amlogic,meson-gxl-dw-hdmi" },
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{ .compatible = "amlogic,meson-gxm-dw-hdmi" },
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{ .compatible = "amlogic,meson-g12a-dw-hdmi" },
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{}
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};
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static int meson_drv_probe(struct platform_device *pdev)
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{
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struct component_match *match = NULL;
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struct device_node *np = pdev->dev.of_node;
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struct device_node *ep, *remote;
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int count = 0;
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for_each_endpoint_of_node(np, ep) {
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remote = of_graph_get_remote_port_parent(ep);
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if (!remote || !of_device_is_available(remote)) {
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of_node_put(remote);
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continue;
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}
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if (of_match_node(components_dev_match, remote)) {
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component_match_add(&pdev->dev, &match, component_compare_of, remote);
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dev_dbg(&pdev->dev, "parent %pOF remote match add %pOF parent %s\n",
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np, remote, dev_name(&pdev->dev));
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}
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of_node_put(remote);
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++count;
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}
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if (count && !match)
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return meson_drv_bind_master(&pdev->dev, false);
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/* If some endpoints were found, initialize the nodes */
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if (count) {
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dev_info(&pdev->dev, "Queued %d outputs on vpu\n", count);
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return component_master_add_with_match(&pdev->dev,
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&meson_drv_master_ops,
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match);
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}
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/* If no output endpoints were available, simply bail out */
|
|
return 0;
|
|
};
|
|
|
|
static int meson_drv_remove(struct platform_device *pdev)
|
|
{
|
|
component_master_del(&pdev->dev, &meson_drv_master_ops);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct meson_drm_match_data meson_drm_gxbb_data = {
|
|
.compat = VPU_COMPATIBLE_GXBB,
|
|
};
|
|
|
|
static struct meson_drm_match_data meson_drm_gxl_data = {
|
|
.compat = VPU_COMPATIBLE_GXL,
|
|
};
|
|
|
|
static struct meson_drm_match_data meson_drm_gxm_data = {
|
|
.compat = VPU_COMPATIBLE_GXM,
|
|
.afbcd_ops = &meson_afbcd_gxm_ops,
|
|
};
|
|
|
|
static struct meson_drm_match_data meson_drm_g12a_data = {
|
|
.compat = VPU_COMPATIBLE_G12A,
|
|
.afbcd_ops = &meson_afbcd_g12a_ops,
|
|
};
|
|
|
|
static const struct of_device_id dt_match[] = {
|
|
{ .compatible = "amlogic,meson-gxbb-vpu",
|
|
.data = (void *)&meson_drm_gxbb_data },
|
|
{ .compatible = "amlogic,meson-gxl-vpu",
|
|
.data = (void *)&meson_drm_gxl_data },
|
|
{ .compatible = "amlogic,meson-gxm-vpu",
|
|
.data = (void *)&meson_drm_gxm_data },
|
|
{ .compatible = "amlogic,meson-g12a-vpu",
|
|
.data = (void *)&meson_drm_g12a_data },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, dt_match);
|
|
|
|
static const struct dev_pm_ops meson_drv_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(meson_drv_pm_suspend, meson_drv_pm_resume)
|
|
};
|
|
|
|
static struct platform_driver meson_drm_platform_driver = {
|
|
.probe = meson_drv_probe,
|
|
.remove = meson_drv_remove,
|
|
.shutdown = meson_drv_shutdown,
|
|
.driver = {
|
|
.name = "meson-drm",
|
|
.of_match_table = dt_match,
|
|
.pm = &meson_drv_pm_ops,
|
|
},
|
|
};
|
|
|
|
drm_module_platform_driver(meson_drm_platform_driver);
|
|
|
|
MODULE_AUTHOR("Jasper St. Pierre <jstpierre@mecheye.net>");
|
|
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
|
MODULE_LICENSE("GPL");
|