567 lines
17 KiB
C
567 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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* Copyright (C) 2014 Endless Mobile
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*
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* Written by:
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* Jasper St. Pierre <jstpierre@mecheye.net>
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*/
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#include <linux/bitfield.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_blend.h>
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#include <drm/drm_device.h>
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#include <drm/drm_fb_dma_helper.h>
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#include <drm/drm_fourcc.h>
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#include <drm/drm_framebuffer.h>
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#include <drm/drm_gem_atomic_helper.h>
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#include <drm/drm_gem_dma_helper.h>
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#include "meson_plane.h"
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#include "meson_registers.h"
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#include "meson_viu.h"
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#include "meson_osd_afbcd.h"
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/* OSD_SCI_WH_M1 */
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#define SCI_WH_M1_W(w) FIELD_PREP(GENMASK(28, 16), w)
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#define SCI_WH_M1_H(h) FIELD_PREP(GENMASK(12, 0), h)
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/* OSD_SCO_H_START_END */
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/* OSD_SCO_V_START_END */
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#define SCO_HV_START(start) FIELD_PREP(GENMASK(27, 16), start)
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#define SCO_HV_END(end) FIELD_PREP(GENMASK(11, 0), end)
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/* OSD_SC_CTRL0 */
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#define SC_CTRL0_PATH_EN BIT(3)
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#define SC_CTRL0_SEL_OSD1 BIT(2)
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/* OSD_VSC_CTRL0 */
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#define VSC_BANK_LEN(value) FIELD_PREP(GENMASK(2, 0), value)
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#define VSC_TOP_INI_RCV_NUM(value) FIELD_PREP(GENMASK(6, 3), value)
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#define VSC_TOP_RPT_L0_NUM(value) FIELD_PREP(GENMASK(9, 8), value)
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#define VSC_BOT_INI_RCV_NUM(value) FIELD_PREP(GENMASK(14, 11), value)
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#define VSC_BOT_RPT_L0_NUM(value) FIELD_PREP(GENMASK(17, 16), value)
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#define VSC_PROG_INTERLACE BIT(23)
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#define VSC_VERTICAL_SCALER_EN BIT(24)
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/* OSD_VSC_INI_PHASE */
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#define VSC_INI_PHASE_BOT(bottom) FIELD_PREP(GENMASK(31, 16), bottom)
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#define VSC_INI_PHASE_TOP(top) FIELD_PREP(GENMASK(15, 0), top)
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/* OSD_HSC_CTRL0 */
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#define HSC_BANK_LENGTH(value) FIELD_PREP(GENMASK(2, 0), value)
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#define HSC_INI_RCV_NUM0(value) FIELD_PREP(GENMASK(6, 3), value)
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#define HSC_RPT_P0_NUM0(value) FIELD_PREP(GENMASK(9, 8), value)
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#define HSC_HORIZ_SCALER_EN BIT(22)
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/* VPP_OSD_VSC_PHASE_STEP */
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/* VPP_OSD_HSC_PHASE_STEP */
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#define SC_PHASE_STEP(value) FIELD_PREP(GENMASK(27, 0), value)
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struct meson_plane {
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struct drm_plane base;
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struct meson_drm *priv;
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bool enabled;
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};
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#define to_meson_plane(x) container_of(x, struct meson_plane, base)
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#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
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static int meson_plane_atomic_check(struct drm_plane *plane,
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struct drm_atomic_state *state)
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{
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struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
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plane);
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struct drm_crtc_state *crtc_state;
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if (!new_plane_state->crtc)
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return 0;
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crtc_state = drm_atomic_get_crtc_state(state,
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new_plane_state->crtc);
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if (IS_ERR(crtc_state))
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return PTR_ERR(crtc_state);
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/*
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* Only allow :
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* - Upscaling up to 5x, vertical and horizontal
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* - Final coordinates must match crtc size
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*/
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return drm_atomic_helper_check_plane_state(new_plane_state,
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crtc_state,
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FRAC_16_16(1, 5),
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DRM_PLANE_NO_SCALING,
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false, true);
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}
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#define MESON_MOD_AFBC_VALID_BITS (AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | \
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AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | \
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AFBC_FORMAT_MOD_YTR | \
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AFBC_FORMAT_MOD_SPARSE | \
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AFBC_FORMAT_MOD_SPLIT)
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/* Takes a fixed 16.16 number and converts it to integer. */
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static inline int64_t fixed16_to_int(int64_t value)
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{
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return value >> 16;
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}
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static u32 meson_g12a_afbcd_line_stride(struct meson_drm *priv)
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{
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u32 line_stride = 0;
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switch (priv->afbcd.format) {
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case DRM_FORMAT_RGB565:
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line_stride = ((priv->viu.osd1_width << 4) + 127) >> 7;
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break;
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case DRM_FORMAT_RGB888:
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_ARGB8888:
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case DRM_FORMAT_XBGR8888:
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case DRM_FORMAT_ABGR8888:
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line_stride = ((priv->viu.osd1_width << 5) + 127) >> 7;
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break;
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}
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return ((line_stride + 1) >> 1) << 1;
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}
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static void meson_plane_atomic_update(struct drm_plane *plane,
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struct drm_atomic_state *state)
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{
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struct meson_plane *meson_plane = to_meson_plane(plane);
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struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
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plane);
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struct drm_rect dest = drm_plane_state_dest(new_state);
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struct meson_drm *priv = meson_plane->priv;
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struct drm_framebuffer *fb = new_state->fb;
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struct drm_gem_dma_object *gem;
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unsigned long flags;
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int vsc_ini_rcv_num, vsc_ini_rpt_p0_num;
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int vsc_bot_rcv_num, vsc_bot_rpt_p0_num;
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int hsc_ini_rcv_num, hsc_ini_rpt_p0_num;
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int hf_phase_step, vf_phase_step;
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int src_w, src_h, dst_w, dst_h;
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int bot_ini_phase;
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int hf_bank_len;
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int vf_bank_len;
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u8 canvas_id_osd1;
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/*
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* Update Coordinates
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* Update Formats
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* Update Buffer
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* Enable Plane
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*/
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spin_lock_irqsave(&priv->drm->event_lock, flags);
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/* Check if AFBC decoder is required for this buffer */
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if ((meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
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meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) &&
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fb->modifier & DRM_FORMAT_MOD_ARM_AFBC(MESON_MOD_AFBC_VALID_BITS))
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priv->viu.osd1_afbcd = true;
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else
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priv->viu.osd1_afbcd = false;
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/* Enable OSD and BLK0, set max global alpha */
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priv->viu.osd1_ctrl_stat = OSD_ENABLE |
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(0x100 << OSD_GLOBAL_ALPHA_SHIFT) |
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OSD_BLK0_ENABLE;
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priv->viu.osd1_ctrl_stat2 = readl(priv->io_base +
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_REG(VIU_OSD1_CTRL_STAT2));
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canvas_id_osd1 = priv->canvas_id_osd1;
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/* Set up BLK0 to point to the right canvas */
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priv->viu.osd1_blk0_cfg[0] = canvas_id_osd1 << OSD_CANVAS_SEL;
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if (priv->viu.osd1_afbcd) {
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if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
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/* This is the internal decoding memory address */
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priv->viu.osd1_blk1_cfg4 = MESON_G12A_AFBCD_OUT_ADDR;
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priv->viu.osd1_blk0_cfg[0] |= OSD_ENDIANNESS_BE;
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priv->viu.osd1_ctrl_stat2 |= OSD_PENDING_STAT_CLEAN;
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priv->viu.osd1_ctrl_stat |= VIU_OSD1_CFG_SYN_EN;
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}
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if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) {
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priv->viu.osd1_blk0_cfg[0] |= OSD_ENDIANNESS_LE;
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priv->viu.osd1_ctrl_stat2 |= OSD_DPATH_MALI_AFBCD;
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}
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} else {
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priv->viu.osd1_blk0_cfg[0] |= OSD_ENDIANNESS_LE;
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if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM))
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priv->viu.osd1_ctrl_stat2 &= ~OSD_DPATH_MALI_AFBCD;
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}
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/* On GXBB, Use the old non-HDR RGB2YUV converter */
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if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
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priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB;
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if (priv->viu.osd1_afbcd &&
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meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
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priv->viu.osd1_blk0_cfg[0] |= OSD_MALI_SRC_EN |
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priv->afbcd.ops->fmt_to_blk_mode(fb->modifier,
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fb->format->format);
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} else {
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switch (fb->format->format) {
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_ARGB8888:
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priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
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OSD_COLOR_MATRIX_32_ARGB;
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break;
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case DRM_FORMAT_XBGR8888:
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case DRM_FORMAT_ABGR8888:
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priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
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OSD_COLOR_MATRIX_32_ABGR;
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break;
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case DRM_FORMAT_RGB888:
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priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_24 |
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OSD_COLOR_MATRIX_24_RGB;
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break;
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case DRM_FORMAT_RGB565:
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priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_16 |
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OSD_COLOR_MATRIX_16_RGB565;
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break;
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}
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}
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switch (fb->format->format) {
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_XBGR8888:
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/* For XRGB, replace the pixel's alpha by 0xFF */
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priv->viu.osd1_ctrl_stat2 |= OSD_REPLACE_EN;
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break;
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case DRM_FORMAT_ARGB8888:
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case DRM_FORMAT_ABGR8888:
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/* For ARGB, use the pixel's alpha */
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priv->viu.osd1_ctrl_stat2 &= ~OSD_REPLACE_EN;
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break;
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}
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/* Default scaler parameters */
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vsc_bot_rcv_num = 0;
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vsc_bot_rpt_p0_num = 0;
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hf_bank_len = 4;
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vf_bank_len = 4;
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if (new_state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
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vsc_bot_rcv_num = 6;
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vsc_bot_rpt_p0_num = 2;
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}
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hsc_ini_rcv_num = hf_bank_len;
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vsc_ini_rcv_num = vf_bank_len;
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hsc_ini_rpt_p0_num = (hf_bank_len / 2) - 1;
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vsc_ini_rpt_p0_num = (vf_bank_len / 2) - 1;
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src_w = fixed16_to_int(new_state->src_w);
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src_h = fixed16_to_int(new_state->src_h);
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dst_w = new_state->crtc_w;
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dst_h = new_state->crtc_h;
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/*
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* When the output is interlaced, the OSD must switch between
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* each field using the INTERLACE_SEL_ODD (0) of VIU_OSD1_BLK0_CFG_W0
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* at each vsync.
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* But the vertical scaler can provide such funtionnality if
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* is configured for 2:1 scaling with interlace options enabled.
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*/
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if (new_state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
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dest.y1 /= 2;
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dest.y2 /= 2;
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dst_h /= 2;
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}
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hf_phase_step = ((src_w << 18) / dst_w) << 6;
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vf_phase_step = (src_h << 20) / dst_h;
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if (new_state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
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bot_ini_phase = ((vf_phase_step / 2) >> 4);
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else
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bot_ini_phase = 0;
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vf_phase_step = (vf_phase_step << 4);
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/* In interlaced mode, scaler is always active */
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if (src_h != dst_h || src_w != dst_w) {
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priv->viu.osd_sc_i_wh_m1 = SCI_WH_M1_W(src_w - 1) |
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SCI_WH_M1_H(src_h - 1);
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priv->viu.osd_sc_o_h_start_end = SCO_HV_START(dest.x1) |
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SCO_HV_END(dest.x2 - 1);
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priv->viu.osd_sc_o_v_start_end = SCO_HV_START(dest.y1) |
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SCO_HV_END(dest.y2 - 1);
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/* Enable OSD Scaler */
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priv->viu.osd_sc_ctrl0 = SC_CTRL0_PATH_EN | SC_CTRL0_SEL_OSD1;
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} else {
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priv->viu.osd_sc_i_wh_m1 = 0;
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priv->viu.osd_sc_o_h_start_end = 0;
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priv->viu.osd_sc_o_v_start_end = 0;
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priv->viu.osd_sc_ctrl0 = 0;
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}
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/* In interlaced mode, vertical scaler is always active */
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if (src_h != dst_h) {
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priv->viu.osd_sc_v_ctrl0 =
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VSC_BANK_LEN(vf_bank_len) |
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VSC_TOP_INI_RCV_NUM(vsc_ini_rcv_num) |
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VSC_TOP_RPT_L0_NUM(vsc_ini_rpt_p0_num) |
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VSC_VERTICAL_SCALER_EN;
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if (new_state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
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priv->viu.osd_sc_v_ctrl0 |=
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VSC_BOT_INI_RCV_NUM(vsc_bot_rcv_num) |
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VSC_BOT_RPT_L0_NUM(vsc_bot_rpt_p0_num) |
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VSC_PROG_INTERLACE;
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priv->viu.osd_sc_v_phase_step = SC_PHASE_STEP(vf_phase_step);
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priv->viu.osd_sc_v_ini_phase = VSC_INI_PHASE_BOT(bot_ini_phase);
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} else {
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priv->viu.osd_sc_v_ctrl0 = 0;
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priv->viu.osd_sc_v_phase_step = 0;
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priv->viu.osd_sc_v_ini_phase = 0;
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}
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/* Horizontal scaler is only used if width does not match */
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if (src_w != dst_w) {
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priv->viu.osd_sc_h_ctrl0 =
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HSC_BANK_LENGTH(hf_bank_len) |
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HSC_INI_RCV_NUM0(hsc_ini_rcv_num) |
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HSC_RPT_P0_NUM0(hsc_ini_rpt_p0_num) |
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HSC_HORIZ_SCALER_EN;
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priv->viu.osd_sc_h_phase_step = SC_PHASE_STEP(hf_phase_step);
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priv->viu.osd_sc_h_ini_phase = 0;
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} else {
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priv->viu.osd_sc_h_ctrl0 = 0;
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priv->viu.osd_sc_h_phase_step = 0;
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priv->viu.osd_sc_h_ini_phase = 0;
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}
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/*
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* The format of these registers is (x2 << 16 | x1),
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* where x2 is exclusive.
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* e.g. +30x1920 would be (1919 << 16) | 30
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*/
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priv->viu.osd1_blk0_cfg[1] =
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((fixed16_to_int(new_state->src.x2) - 1) << 16) |
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fixed16_to_int(new_state->src.x1);
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priv->viu.osd1_blk0_cfg[2] =
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((fixed16_to_int(new_state->src.y2) - 1) << 16) |
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fixed16_to_int(new_state->src.y1);
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priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1;
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priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1;
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if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
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priv->viu.osd_blend_din0_scope_h = ((dest.x2 - 1) << 16) | dest.x1;
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priv->viu.osd_blend_din0_scope_v = ((dest.y2 - 1) << 16) | dest.y1;
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priv->viu.osb_blend0_size = dst_h << 16 | dst_w;
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priv->viu.osb_blend1_size = dst_h << 16 | dst_w;
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}
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/* Update Canvas with buffer address */
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gem = drm_fb_dma_get_gem_obj(fb, 0);
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priv->viu.osd1_addr = gem->dma_addr;
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priv->viu.osd1_stride = fb->pitches[0];
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priv->viu.osd1_height = fb->height;
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priv->viu.osd1_width = fb->width;
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if (priv->viu.osd1_afbcd) {
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priv->afbcd.modifier = fb->modifier;
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priv->afbcd.format = fb->format->format;
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/* Calculate decoder write stride */
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if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
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priv->viu.osd1_blk2_cfg4 =
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meson_g12a_afbcd_line_stride(priv);
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}
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if (!meson_plane->enabled) {
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/* Reset OSD1 before enabling it on GXL+ SoCs */
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if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
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meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
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meson_viu_osd1_reset(priv);
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meson_plane->enabled = true;
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}
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priv->viu.osd1_enabled = true;
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spin_unlock_irqrestore(&priv->drm->event_lock, flags);
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}
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static void meson_plane_atomic_disable(struct drm_plane *plane,
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struct drm_atomic_state *state)
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{
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struct meson_plane *meson_plane = to_meson_plane(plane);
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struct meson_drm *priv = meson_plane->priv;
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if (priv->afbcd.ops) {
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priv->afbcd.ops->reset(priv);
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priv->afbcd.ops->disable(priv);
|
|
}
|
|
|
|
/* Disable OSD1 */
|
|
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
|
|
writel_bits_relaxed(VIU_OSD1_POSTBLD_SRC_OSD1, 0,
|
|
priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
|
|
else
|
|
writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0,
|
|
priv->io_base + _REG(VPP_MISC));
|
|
|
|
meson_plane->enabled = false;
|
|
priv->viu.osd1_enabled = false;
|
|
}
|
|
|
|
static const struct drm_plane_helper_funcs meson_plane_helper_funcs = {
|
|
.atomic_check = meson_plane_atomic_check,
|
|
.atomic_disable = meson_plane_atomic_disable,
|
|
.atomic_update = meson_plane_atomic_update,
|
|
};
|
|
|
|
static bool meson_plane_format_mod_supported(struct drm_plane *plane,
|
|
u32 format, u64 modifier)
|
|
{
|
|
struct meson_plane *meson_plane = to_meson_plane(plane);
|
|
struct meson_drm *priv = meson_plane->priv;
|
|
int i;
|
|
|
|
if (modifier == DRM_FORMAT_MOD_INVALID)
|
|
return false;
|
|
|
|
if (modifier == DRM_FORMAT_MOD_LINEAR)
|
|
return true;
|
|
|
|
if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) &&
|
|
!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
|
|
return false;
|
|
|
|
if (modifier & ~DRM_FORMAT_MOD_ARM_AFBC(MESON_MOD_AFBC_VALID_BITS))
|
|
return false;
|
|
|
|
for (i = 0 ; i < plane->modifier_count ; ++i)
|
|
if (plane->modifiers[i] == modifier)
|
|
break;
|
|
|
|
if (i == plane->modifier_count) {
|
|
DRM_DEBUG_KMS("Unsupported modifier\n");
|
|
return false;
|
|
}
|
|
|
|
if (priv->afbcd.ops && priv->afbcd.ops->supported_fmt)
|
|
return priv->afbcd.ops->supported_fmt(modifier, format);
|
|
|
|
DRM_DEBUG_KMS("AFBC Unsupported\n");
|
|
return false;
|
|
}
|
|
|
|
static const struct drm_plane_funcs meson_plane_funcs = {
|
|
.update_plane = drm_atomic_helper_update_plane,
|
|
.disable_plane = drm_atomic_helper_disable_plane,
|
|
.destroy = drm_plane_cleanup,
|
|
.reset = drm_atomic_helper_plane_reset,
|
|
.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
|
|
.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
|
|
.format_mod_supported = meson_plane_format_mod_supported,
|
|
};
|
|
|
|
static const uint32_t supported_drm_formats[] = {
|
|
DRM_FORMAT_ARGB8888,
|
|
DRM_FORMAT_ABGR8888,
|
|
DRM_FORMAT_XRGB8888,
|
|
DRM_FORMAT_XBGR8888,
|
|
DRM_FORMAT_RGB888,
|
|
DRM_FORMAT_RGB565,
|
|
};
|
|
|
|
static const uint64_t format_modifiers_afbc_gxm[] = {
|
|
DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
|
|
AFBC_FORMAT_MOD_SPARSE |
|
|
AFBC_FORMAT_MOD_YTR),
|
|
/* SPLIT mandates SPARSE, RGB modes mandates YTR */
|
|
DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
|
|
AFBC_FORMAT_MOD_YTR |
|
|
AFBC_FORMAT_MOD_SPARSE |
|
|
AFBC_FORMAT_MOD_SPLIT),
|
|
DRM_FORMAT_MOD_LINEAR,
|
|
DRM_FORMAT_MOD_INVALID,
|
|
};
|
|
|
|
static const uint64_t format_modifiers_afbc_g12a[] = {
|
|
/*
|
|
* - TOFIX Support AFBC modifiers for YUV formats (16x16 + TILED)
|
|
* - SPLIT is mandatory for performances reasons when in 16x16
|
|
* block size
|
|
* - 32x8 block size + SPLIT is mandatory with 4K frame size
|
|
* for performances reasons
|
|
*/
|
|
DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
|
|
AFBC_FORMAT_MOD_SPARSE |
|
|
AFBC_FORMAT_MOD_SPLIT),
|
|
DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
|
|
AFBC_FORMAT_MOD_YTR |
|
|
AFBC_FORMAT_MOD_SPARSE |
|
|
AFBC_FORMAT_MOD_SPLIT),
|
|
DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 |
|
|
AFBC_FORMAT_MOD_SPARSE),
|
|
DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 |
|
|
AFBC_FORMAT_MOD_YTR |
|
|
AFBC_FORMAT_MOD_SPARSE),
|
|
DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 |
|
|
AFBC_FORMAT_MOD_SPARSE |
|
|
AFBC_FORMAT_MOD_SPLIT),
|
|
DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 |
|
|
AFBC_FORMAT_MOD_YTR |
|
|
AFBC_FORMAT_MOD_SPARSE |
|
|
AFBC_FORMAT_MOD_SPLIT),
|
|
DRM_FORMAT_MOD_LINEAR,
|
|
DRM_FORMAT_MOD_INVALID,
|
|
};
|
|
|
|
static const uint64_t format_modifiers_default[] = {
|
|
DRM_FORMAT_MOD_LINEAR,
|
|
DRM_FORMAT_MOD_INVALID,
|
|
};
|
|
|
|
int meson_plane_create(struct meson_drm *priv)
|
|
{
|
|
struct meson_plane *meson_plane;
|
|
struct drm_plane *plane;
|
|
const uint64_t *format_modifiers = format_modifiers_default;
|
|
|
|
meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane),
|
|
GFP_KERNEL);
|
|
if (!meson_plane)
|
|
return -ENOMEM;
|
|
|
|
meson_plane->priv = priv;
|
|
plane = &meson_plane->base;
|
|
|
|
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM))
|
|
format_modifiers = format_modifiers_afbc_gxm;
|
|
else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
|
|
format_modifiers = format_modifiers_afbc_g12a;
|
|
|
|
drm_universal_plane_init(priv->drm, plane, 0xFF,
|
|
&meson_plane_funcs,
|
|
supported_drm_formats,
|
|
ARRAY_SIZE(supported_drm_formats),
|
|
format_modifiers,
|
|
DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane");
|
|
|
|
drm_plane_helper_add(plane, &meson_plane_helper_funcs);
|
|
|
|
/* For now, OSD Primary plane is always on the front */
|
|
drm_plane_create_zpos_immutable_property(plane, 1);
|
|
|
|
priv->primary_plane = plane;
|
|
|
|
return 0;
|
|
}
|