609 lines
15 KiB
C
609 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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*/
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#include <linux/bitops.h>
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#include <linux/debugfs.h>
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#include <linux/slab.h>
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#include "dpu_core_irq.h"
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#include "dpu_kms.h"
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#include "dpu_hw_interrupts.h"
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#include "dpu_hw_util.h"
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#include "dpu_hw_mdss.h"
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#include "dpu_trace.h"
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/*
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* Register offsets in MDSS register file for the interrupt registers
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* w.r.t. the MDP base
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*/
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#define MDP_INTF_OFF(intf) (0x6A000 + 0x800 * (intf))
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#define MDP_INTF_INTR_EN(intf) (MDP_INTF_OFF(intf) + 0x1c0)
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#define MDP_INTF_INTR_STATUS(intf) (MDP_INTF_OFF(intf) + 0x1c4)
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#define MDP_INTF_INTR_CLEAR(intf) (MDP_INTF_OFF(intf) + 0x1c8)
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#define MDP_INTF_TEAR_OFF(intf) (0x6D700 + 0x100 * (intf))
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#define MDP_INTF_INTR_TEAR_EN(intf) (MDP_INTF_TEAR_OFF(intf) + 0x000)
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#define MDP_INTF_INTR_TEAR_STATUS(intf) (MDP_INTF_TEAR_OFF(intf) + 0x004)
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#define MDP_INTF_INTR_TEAR_CLEAR(intf) (MDP_INTF_TEAR_OFF(intf) + 0x008)
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#define MDP_AD4_OFF(ad4) (0x7C000 + 0x1000 * (ad4))
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#define MDP_AD4_INTR_EN_OFF(ad4) (MDP_AD4_OFF(ad4) + 0x41c)
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#define MDP_AD4_INTR_CLEAR_OFF(ad4) (MDP_AD4_OFF(ad4) + 0x424)
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#define MDP_AD4_INTR_STATUS_OFF(ad4) (MDP_AD4_OFF(ad4) + 0x420)
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#define MDP_INTF_REV_7xxx_OFF(intf) (0x34000 + 0x1000 * (intf))
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#define MDP_INTF_REV_7xxx_INTR_EN(intf) (MDP_INTF_REV_7xxx_OFF(intf) + 0x1c0)
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#define MDP_INTF_REV_7xxx_INTR_STATUS(intf) (MDP_INTF_REV_7xxx_OFF(intf) + 0x1c4)
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#define MDP_INTF_REV_7xxx_INTR_CLEAR(intf) (MDP_INTF_REV_7xxx_OFF(intf) + 0x1c8)
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#define MDP_INTF_REV_7xxx_TEAR_OFF(intf) (0x34800 + 0x1000 * (intf))
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#define MDP_INTF_REV_7xxx_INTR_TEAR_EN(intf) (MDP_INTF_REV_7xxx_TEAR_OFF(intf) + 0x000)
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#define MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(intf) (MDP_INTF_REV_7xxx_TEAR_OFF(intf) + 0x004)
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#define MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(intf) (MDP_INTF_REV_7xxx_TEAR_OFF(intf) + 0x008)
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/**
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* struct dpu_intr_reg - array of DPU register sets
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* @clr_off: offset to CLEAR reg
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* @en_off: offset to ENABLE reg
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* @status_off: offset to STATUS reg
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*/
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struct dpu_intr_reg {
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u32 clr_off;
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u32 en_off;
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u32 status_off;
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};
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/*
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* struct dpu_intr_reg - List of DPU interrupt registers
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*
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* When making changes be sure to sync with dpu_hw_intr_reg
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*/
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static const struct dpu_intr_reg dpu_intr_set[] = {
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[MDP_SSPP_TOP0_INTR] = {
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INTR_CLEAR,
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INTR_EN,
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INTR_STATUS
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},
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[MDP_SSPP_TOP0_INTR2] = {
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INTR2_CLEAR,
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INTR2_EN,
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INTR2_STATUS
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},
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[MDP_SSPP_TOP0_HIST_INTR] = {
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HIST_INTR_CLEAR,
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HIST_INTR_EN,
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HIST_INTR_STATUS
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},
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[MDP_INTF0_INTR] = {
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MDP_INTF_INTR_CLEAR(0),
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MDP_INTF_INTR_EN(0),
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MDP_INTF_INTR_STATUS(0)
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},
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[MDP_INTF1_INTR] = {
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MDP_INTF_INTR_CLEAR(1),
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MDP_INTF_INTR_EN(1),
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MDP_INTF_INTR_STATUS(1)
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},
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[MDP_INTF2_INTR] = {
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MDP_INTF_INTR_CLEAR(2),
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MDP_INTF_INTR_EN(2),
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MDP_INTF_INTR_STATUS(2)
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},
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[MDP_INTF3_INTR] = {
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MDP_INTF_INTR_CLEAR(3),
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MDP_INTF_INTR_EN(3),
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MDP_INTF_INTR_STATUS(3)
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},
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[MDP_INTF4_INTR] = {
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MDP_INTF_INTR_CLEAR(4),
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MDP_INTF_INTR_EN(4),
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MDP_INTF_INTR_STATUS(4)
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},
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[MDP_INTF5_INTR] = {
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MDP_INTF_INTR_CLEAR(5),
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MDP_INTF_INTR_EN(5),
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MDP_INTF_INTR_STATUS(5)
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},
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[MDP_INTF1_TEAR_INTR] = {
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MDP_INTF_INTR_TEAR_CLEAR(1),
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MDP_INTF_INTR_TEAR_EN(1),
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MDP_INTF_INTR_TEAR_STATUS(1)
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},
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[MDP_INTF2_TEAR_INTR] = {
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MDP_INTF_INTR_TEAR_CLEAR(2),
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MDP_INTF_INTR_TEAR_EN(2),
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MDP_INTF_INTR_TEAR_STATUS(2)
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},
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[MDP_AD4_0_INTR] = {
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MDP_AD4_INTR_CLEAR_OFF(0),
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MDP_AD4_INTR_EN_OFF(0),
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MDP_AD4_INTR_STATUS_OFF(0),
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},
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[MDP_AD4_1_INTR] = {
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MDP_AD4_INTR_CLEAR_OFF(1),
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MDP_AD4_INTR_EN_OFF(1),
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MDP_AD4_INTR_STATUS_OFF(1),
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},
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[MDP_INTF0_7xxx_INTR] = {
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MDP_INTF_REV_7xxx_INTR_CLEAR(0),
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MDP_INTF_REV_7xxx_INTR_EN(0),
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MDP_INTF_REV_7xxx_INTR_STATUS(0)
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},
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[MDP_INTF1_7xxx_INTR] = {
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MDP_INTF_REV_7xxx_INTR_CLEAR(1),
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MDP_INTF_REV_7xxx_INTR_EN(1),
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MDP_INTF_REV_7xxx_INTR_STATUS(1)
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},
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[MDP_INTF1_7xxx_TEAR_INTR] = {
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MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(1),
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MDP_INTF_REV_7xxx_INTR_TEAR_EN(1),
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MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(1)
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},
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[MDP_INTF2_7xxx_INTR] = {
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MDP_INTF_REV_7xxx_INTR_CLEAR(2),
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MDP_INTF_REV_7xxx_INTR_EN(2),
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MDP_INTF_REV_7xxx_INTR_STATUS(2)
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},
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[MDP_INTF2_7xxx_TEAR_INTR] = {
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MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(2),
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MDP_INTF_REV_7xxx_INTR_TEAR_EN(2),
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MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(2)
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},
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[MDP_INTF3_7xxx_INTR] = {
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MDP_INTF_REV_7xxx_INTR_CLEAR(3),
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MDP_INTF_REV_7xxx_INTR_EN(3),
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MDP_INTF_REV_7xxx_INTR_STATUS(3)
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},
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[MDP_INTF4_7xxx_INTR] = {
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MDP_INTF_REV_7xxx_INTR_CLEAR(4),
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MDP_INTF_REV_7xxx_INTR_EN(4),
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MDP_INTF_REV_7xxx_INTR_STATUS(4)
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},
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[MDP_INTF5_7xxx_INTR] = {
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MDP_INTF_REV_7xxx_INTR_CLEAR(5),
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MDP_INTF_REV_7xxx_INTR_EN(5),
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MDP_INTF_REV_7xxx_INTR_STATUS(5)
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},
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[MDP_INTF6_7xxx_INTR] = {
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MDP_INTF_REV_7xxx_INTR_CLEAR(6),
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MDP_INTF_REV_7xxx_INTR_EN(6),
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MDP_INTF_REV_7xxx_INTR_STATUS(6)
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},
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[MDP_INTF7_7xxx_INTR] = {
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MDP_INTF_REV_7xxx_INTR_CLEAR(7),
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MDP_INTF_REV_7xxx_INTR_EN(7),
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MDP_INTF_REV_7xxx_INTR_STATUS(7)
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},
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[MDP_INTF8_7xxx_INTR] = {
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MDP_INTF_REV_7xxx_INTR_CLEAR(8),
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MDP_INTF_REV_7xxx_INTR_EN(8),
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MDP_INTF_REV_7xxx_INTR_STATUS(8)
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},
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};
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#define DPU_IRQ_REG(irq_idx) (irq_idx / 32)
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#define DPU_IRQ_MASK(irq_idx) (BIT(irq_idx % 32))
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/**
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* dpu_core_irq_callback_handler - dispatch core interrupts
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* @dpu_kms: Pointer to DPU's KMS structure
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* @irq_idx: interrupt index
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*/
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static void dpu_core_irq_callback_handler(struct dpu_kms *dpu_kms, int irq_idx)
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{
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VERB("irq_idx=%d\n", irq_idx);
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if (!dpu_kms->hw_intr->irq_tbl[irq_idx].cb)
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DRM_ERROR("no registered cb, idx:%d\n", irq_idx);
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atomic_inc(&dpu_kms->hw_intr->irq_tbl[irq_idx].count);
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/*
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* Perform registered function callback
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*/
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dpu_kms->hw_intr->irq_tbl[irq_idx].cb(dpu_kms->hw_intr->irq_tbl[irq_idx].arg, irq_idx);
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}
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irqreturn_t dpu_core_irq(struct msm_kms *kms)
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{
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struct dpu_kms *dpu_kms = to_dpu_kms(kms);
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struct dpu_hw_intr *intr = dpu_kms->hw_intr;
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int reg_idx;
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int irq_idx;
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u32 irq_status;
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u32 enable_mask;
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int bit;
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unsigned long irq_flags;
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if (!intr)
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return IRQ_NONE;
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spin_lock_irqsave(&intr->irq_lock, irq_flags);
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for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
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if (!test_bit(reg_idx, &intr->irq_mask))
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continue;
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/* Read interrupt status */
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irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off);
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/* Read enable mask */
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enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off);
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/* and clear the interrupt */
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if (irq_status)
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DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
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irq_status);
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/* Finally update IRQ status based on enable mask */
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irq_status &= enable_mask;
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if (!irq_status)
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continue;
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/*
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* Search through matching intr status.
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*/
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while ((bit = ffs(irq_status)) != 0) {
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irq_idx = DPU_IRQ_IDX(reg_idx, bit - 1);
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dpu_core_irq_callback_handler(dpu_kms, irq_idx);
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/*
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* When callback finish, clear the irq_status
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* with the matching mask. Once irq_status
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* is all cleared, the search can be stopped.
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*/
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irq_status &= ~BIT(bit - 1);
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}
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}
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/* ensure register writes go through */
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wmb();
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spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
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return IRQ_HANDLED;
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}
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static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
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{
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int reg_idx;
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const struct dpu_intr_reg *reg;
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const char *dbgstr = NULL;
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uint32_t cache_irq_mask;
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if (!intr)
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return -EINVAL;
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if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
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pr_err("invalid IRQ index: [%d]\n", irq_idx);
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return -EINVAL;
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}
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/*
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* The cache_irq_mask and hardware RMW operations needs to be done
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* under irq_lock and it's the caller's responsibility to ensure that's
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* held.
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*/
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assert_spin_locked(&intr->irq_lock);
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reg_idx = DPU_IRQ_REG(irq_idx);
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reg = &dpu_intr_set[reg_idx];
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cache_irq_mask = intr->cache_irq_mask[reg_idx];
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if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
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dbgstr = "already ";
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} else {
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dbgstr = "";
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cache_irq_mask |= DPU_IRQ_MASK(irq_idx);
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/* Cleaning any pending interrupt */
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DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));
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/* Enabling interrupts with the new mask */
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DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
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/* ensure register write goes through */
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wmb();
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intr->cache_irq_mask[reg_idx] = cache_irq_mask;
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}
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pr_debug("DPU IRQ %d %senabled: MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", irq_idx, dbgstr,
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DPU_IRQ_MASK(irq_idx), cache_irq_mask);
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return 0;
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}
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static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
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{
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int reg_idx;
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const struct dpu_intr_reg *reg;
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const char *dbgstr = NULL;
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uint32_t cache_irq_mask;
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if (!intr)
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return -EINVAL;
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if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
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pr_err("invalid IRQ index: [%d]\n", irq_idx);
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return -EINVAL;
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}
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/*
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* The cache_irq_mask and hardware RMW operations needs to be done
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* under irq_lock and it's the caller's responsibility to ensure that's
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* held.
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*/
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assert_spin_locked(&intr->irq_lock);
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reg_idx = DPU_IRQ_REG(irq_idx);
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reg = &dpu_intr_set[reg_idx];
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cache_irq_mask = intr->cache_irq_mask[reg_idx];
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if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
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dbgstr = "already ";
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} else {
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dbgstr = "";
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cache_irq_mask &= ~DPU_IRQ_MASK(irq_idx);
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/* Disable interrupts based on the new mask */
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DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
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/* Cleaning any pending interrupt */
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DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));
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/* ensure register write goes through */
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wmb();
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intr->cache_irq_mask[reg_idx] = cache_irq_mask;
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}
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pr_debug("DPU IRQ %d %sdisabled: MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", irq_idx, dbgstr,
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DPU_IRQ_MASK(irq_idx), cache_irq_mask);
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return 0;
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}
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static void dpu_clear_irqs(struct dpu_kms *dpu_kms)
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{
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struct dpu_hw_intr *intr = dpu_kms->hw_intr;
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int i;
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if (!intr)
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return;
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for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
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if (test_bit(i, &intr->irq_mask))
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DPU_REG_WRITE(&intr->hw,
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dpu_intr_set[i].clr_off, 0xffffffff);
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}
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/* ensure register writes go through */
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wmb();
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}
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static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms)
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{
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struct dpu_hw_intr *intr = dpu_kms->hw_intr;
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int i;
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if (!intr)
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return;
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for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
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if (test_bit(i, &intr->irq_mask))
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DPU_REG_WRITE(&intr->hw,
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dpu_intr_set[i].en_off, 0x00000000);
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}
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/* ensure register writes go through */
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wmb();
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}
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u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
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{
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struct dpu_hw_intr *intr = dpu_kms->hw_intr;
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int reg_idx;
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unsigned long irq_flags;
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u32 intr_status;
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if (!intr)
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return 0;
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if (irq_idx < 0) {
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DPU_ERROR("[%pS] invalid irq_idx=%d\n",
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__builtin_return_address(0), irq_idx);
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return 0;
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}
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if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
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pr_err("invalid IRQ index: [%d]\n", irq_idx);
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return 0;
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}
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spin_lock_irqsave(&intr->irq_lock, irq_flags);
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reg_idx = DPU_IRQ_REG(irq_idx);
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intr_status = DPU_REG_READ(&intr->hw,
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dpu_intr_set[reg_idx].status_off) &
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DPU_IRQ_MASK(irq_idx);
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if (intr_status)
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DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
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intr_status);
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/* ensure register writes go through */
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wmb();
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spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
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return intr_status;
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}
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static void __intr_offset(const struct dpu_mdss_cfg *m,
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void __iomem *addr, struct dpu_hw_blk_reg_map *hw)
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{
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hw->blk_addr = addr + m->mdp[0].base;
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}
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struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
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const struct dpu_mdss_cfg *m)
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{
|
|
struct dpu_hw_intr *intr;
|
|
int nirq = MDP_INTR_MAX * 32;
|
|
|
|
if (!addr || !m)
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
intr = kzalloc(struct_size(intr, irq_tbl, nirq), GFP_KERNEL);
|
|
if (!intr)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
__intr_offset(m, addr, &intr->hw);
|
|
|
|
intr->total_irqs = nirq;
|
|
|
|
intr->irq_mask = m->mdss_irqs;
|
|
|
|
spin_lock_init(&intr->irq_lock);
|
|
|
|
return intr;
|
|
}
|
|
|
|
void dpu_hw_intr_destroy(struct dpu_hw_intr *intr)
|
|
{
|
|
kfree(intr);
|
|
}
|
|
|
|
int dpu_core_irq_register_callback(struct dpu_kms *dpu_kms, int irq_idx,
|
|
void (*irq_cb)(void *arg, int irq_idx),
|
|
void *irq_arg)
|
|
{
|
|
unsigned long irq_flags;
|
|
int ret;
|
|
|
|
if (!irq_cb) {
|
|
DPU_ERROR("invalid ird_idx:%d irq_cb:%ps\n", irq_idx, irq_cb);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
|
|
DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
|
|
return -EINVAL;
|
|
}
|
|
|
|
VERB("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx);
|
|
|
|
spin_lock_irqsave(&dpu_kms->hw_intr->irq_lock, irq_flags);
|
|
|
|
if (unlikely(WARN_ON(dpu_kms->hw_intr->irq_tbl[irq_idx].cb))) {
|
|
spin_unlock_irqrestore(&dpu_kms->hw_intr->irq_lock, irq_flags);
|
|
|
|
return -EBUSY;
|
|
}
|
|
|
|
trace_dpu_core_irq_register_callback(irq_idx, irq_cb);
|
|
dpu_kms->hw_intr->irq_tbl[irq_idx].arg = irq_arg;
|
|
dpu_kms->hw_intr->irq_tbl[irq_idx].cb = irq_cb;
|
|
|
|
ret = dpu_hw_intr_enable_irq_locked(
|
|
dpu_kms->hw_intr,
|
|
irq_idx);
|
|
if (ret)
|
|
DPU_ERROR("Fail to enable IRQ for irq_idx:%d\n",
|
|
irq_idx);
|
|
spin_unlock_irqrestore(&dpu_kms->hw_intr->irq_lock, irq_flags);
|
|
|
|
trace_dpu_irq_register_success(irq_idx);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int dpu_core_irq_unregister_callback(struct dpu_kms *dpu_kms, int irq_idx)
|
|
{
|
|
unsigned long irq_flags;
|
|
int ret;
|
|
|
|
if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
|
|
DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
|
|
return -EINVAL;
|
|
}
|
|
|
|
VERB("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx);
|
|
|
|
spin_lock_irqsave(&dpu_kms->hw_intr->irq_lock, irq_flags);
|
|
trace_dpu_core_irq_unregister_callback(irq_idx);
|
|
|
|
ret = dpu_hw_intr_disable_irq_locked(dpu_kms->hw_intr, irq_idx);
|
|
if (ret)
|
|
DPU_ERROR("Fail to disable IRQ for irq_idx:%d: %d\n",
|
|
irq_idx, ret);
|
|
|
|
dpu_kms->hw_intr->irq_tbl[irq_idx].cb = NULL;
|
|
dpu_kms->hw_intr->irq_tbl[irq_idx].arg = NULL;
|
|
|
|
spin_unlock_irqrestore(&dpu_kms->hw_intr->irq_lock, irq_flags);
|
|
|
|
trace_dpu_irq_unregister_success(irq_idx);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
static int dpu_debugfs_core_irq_show(struct seq_file *s, void *v)
|
|
{
|
|
struct dpu_kms *dpu_kms = s->private;
|
|
unsigned long irq_flags;
|
|
int i, irq_count;
|
|
void *cb;
|
|
|
|
for (i = 0; i < dpu_kms->hw_intr->total_irqs; i++) {
|
|
spin_lock_irqsave(&dpu_kms->hw_intr->irq_lock, irq_flags);
|
|
irq_count = atomic_read(&dpu_kms->hw_intr->irq_tbl[i].count);
|
|
cb = dpu_kms->hw_intr->irq_tbl[i].cb;
|
|
spin_unlock_irqrestore(&dpu_kms->hw_intr->irq_lock, irq_flags);
|
|
|
|
if (irq_count || cb)
|
|
seq_printf(s, "idx:%d irq:%d cb:%ps\n", i, irq_count, cb);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_core_irq);
|
|
|
|
void dpu_debugfs_core_irq_init(struct dpu_kms *dpu_kms,
|
|
struct dentry *parent)
|
|
{
|
|
debugfs_create_file("core_irq", 0600, parent, dpu_kms,
|
|
&dpu_debugfs_core_irq_fops);
|
|
}
|
|
#endif
|
|
|
|
void dpu_core_irq_preinstall(struct msm_kms *kms)
|
|
{
|
|
struct dpu_kms *dpu_kms = to_dpu_kms(kms);
|
|
int i;
|
|
|
|
pm_runtime_get_sync(&dpu_kms->pdev->dev);
|
|
dpu_clear_irqs(dpu_kms);
|
|
dpu_disable_all_irqs(dpu_kms);
|
|
pm_runtime_put_sync(&dpu_kms->pdev->dev);
|
|
|
|
for (i = 0; i < dpu_kms->hw_intr->total_irqs; i++)
|
|
atomic_set(&dpu_kms->hw_intr->irq_tbl[i].count, 0);
|
|
}
|
|
|
|
void dpu_core_irq_uninstall(struct msm_kms *kms)
|
|
{
|
|
struct dpu_kms *dpu_kms = to_dpu_kms(kms);
|
|
int i;
|
|
|
|
if (!dpu_kms->hw_intr)
|
|
return;
|
|
|
|
pm_runtime_get_sync(&dpu_kms->pdev->dev);
|
|
for (i = 0; i < dpu_kms->hw_intr->total_irqs; i++)
|
|
if (dpu_kms->hw_intr->irq_tbl[i].cb)
|
|
DPU_ERROR("irq_idx=%d still enabled/registered\n", i);
|
|
|
|
dpu_clear_irqs(dpu_kms);
|
|
dpu_disable_all_irqs(dpu_kms);
|
|
pm_runtime_put_sync(&dpu_kms->pdev->dev);
|
|
}
|