149 lines
5.0 KiB
C
149 lines
5.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*/
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#include "dsi_phy.h"
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#include "dsi.xml.h"
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#include "dsi_phy_20nm.xml.h"
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static void dsi_20nm_dphy_set_timing(struct msm_dsi_phy *phy,
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struct msm_dsi_dphy_timing *timing)
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{
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void __iomem *base = phy->base;
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0,
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DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero));
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1,
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DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail));
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2,
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DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare));
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if (timing->clk_zero & BIT(8))
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3,
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DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8);
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4,
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DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit));
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5,
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DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero));
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6,
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DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare));
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_7,
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DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail));
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_8,
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DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst));
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_9,
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DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |
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DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure));
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_10,
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DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get));
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_11,
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DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0));
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}
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static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable)
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{
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void __iomem *base = phy->reg_base;
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if (!enable) {
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dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0);
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return;
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}
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if (phy->regulator_ldo_mode) {
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dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x1d);
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return;
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}
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/* non LDO mode */
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dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_1, 0x03);
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dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_2, 0x03);
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dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_3, 0x00);
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dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_4, 0x20);
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dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0x01);
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dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x00);
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dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0, 0x03);
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}
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static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy,
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struct msm_dsi_phy_clk_request *clk_req)
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{
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struct msm_dsi_dphy_timing *timing = &phy->timing;
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int i;
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void __iomem *base = phy->base;
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u32 cfg_4[4] = {0x20, 0x40, 0x20, 0x00};
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u32 val;
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DBG("");
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if (msm_dsi_dphy_timing_calc(timing, clk_req)) {
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DRM_DEV_ERROR(&phy->pdev->dev,
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"%s: D-PHY timing calculation failed\n", __func__);
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return -EINVAL;
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}
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dsi_20nm_phy_regulator_ctrl(phy, true);
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dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff);
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val = dsi_phy_read(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL);
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if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_STANDALONE)
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val |= DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
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else
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val &= ~DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;
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dsi_phy_write(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL, val);
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for (i = 0; i < 4; i++) {
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dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i),
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(i >> 1) * 0x40);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_0(i), 0x01);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_1(i), 0x46);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_0(i), 0x02);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_1(i), 0xa0);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_4(i), cfg_4[i]);
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}
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dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_3, 0x80);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR0, 0x01);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR1, 0x46);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_0, 0x00);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_1, 0xa0);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_2, 0x00);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_4, 0x00);
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dsi_20nm_dphy_set_timing(phy, timing);
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dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_1, 0x00);
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dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_1, 0x06);
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/* make sure everything is written before enable */
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wmb();
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dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_0, 0x7f);
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return 0;
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}
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static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy)
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{
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dsi_phy_write(phy->base + REG_DSI_20nm_PHY_CTRL_0, 0);
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dsi_20nm_phy_regulator_ctrl(phy, false);
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}
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static const struct regulator_bulk_data dsi_phy_20nm_regulators[] = {
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{ .supply = "vddio", .init_load_uA = 100000 }, /* 1.8 V */
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{ .supply = "vcca", .init_load_uA = 10000 }, /* 1.0 V */
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};
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const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {
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.has_phy_regulator = true,
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.regulator_data = dsi_phy_20nm_regulators,
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.num_regulators = ARRAY_SIZE(dsi_phy_20nm_regulators),
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.ops = {
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.enable = dsi_20nm_phy_enable,
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.disable = dsi_20nm_phy_disable,
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},
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.io_start = { 0xfd998500, 0xfd9a0500 },
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.num_dsi_phy = 2,
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};
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