149 lines
4.1 KiB
C
149 lines
4.1 KiB
C
/*
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* Copyright 2022 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include <subdev/mc.h>
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#include <subdev/timer.h>
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static bool
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ga102_flcn_dma_done(struct nvkm_falcon *falcon)
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{
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return !!(nvkm_falcon_rd32(falcon, 0x118) & 0x00000002);
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}
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static void
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ga102_flcn_dma_xfer(struct nvkm_falcon *falcon, u32 mem_base, u32 dma_base, u32 cmd)
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{
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nvkm_falcon_wr32(falcon, 0x114, mem_base);
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nvkm_falcon_wr32(falcon, 0x11c, dma_base);
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nvkm_falcon_wr32(falcon, 0x118, cmd);
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}
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static int
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ga102_flcn_dma_init(struct nvkm_falcon *falcon, u64 dma_addr, int xfer_len,
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enum nvkm_falcon_mem mem_type, bool sec, u32 *cmd)
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{
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*cmd = (ilog2(xfer_len) - 2) << 8;
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if (mem_type == IMEM)
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*cmd |= 0x00000010;
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if (sec)
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*cmd |= 0x00000004;
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nvkm_falcon_wr32(falcon, 0x110, dma_addr >> 8);
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nvkm_falcon_wr32(falcon, 0x128, 0x00000000);
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return 0;
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}
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const struct nvkm_falcon_func_dma
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ga102_flcn_dma = {
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.init = ga102_flcn_dma_init,
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.xfer = ga102_flcn_dma_xfer,
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.done = ga102_flcn_dma_done,
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};
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int
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ga102_flcn_reset_wait_mem_scrubbing(struct nvkm_falcon *falcon)
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{
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nvkm_falcon_mask(falcon, 0x040, 0x00000000, 0x00000000);
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if (nvkm_msec(falcon->owner->device, 20,
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if (!(nvkm_falcon_rd32(falcon, 0x0f4) & 0x00001000))
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break;
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) < 0)
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return -ETIMEDOUT;
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return 0;
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}
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int
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ga102_flcn_reset_prep(struct nvkm_falcon *falcon)
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{
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nvkm_falcon_rd32(falcon, 0x0f4);
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nvkm_usec(falcon->owner->device, 150,
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if (nvkm_falcon_rd32(falcon, 0x0f4) & 0x80000000)
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break;
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_warn = false;
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);
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return 0;
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}
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int
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ga102_flcn_select(struct nvkm_falcon *falcon)
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{
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if ((nvkm_falcon_rd32(falcon, falcon->addr2 + 0x668) & 0x00000010) != 0x00000000) {
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nvkm_falcon_wr32(falcon, falcon->addr2 + 0x668, 0x00000000);
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if (nvkm_msec(falcon->owner->device, 10,
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if (nvkm_falcon_rd32(falcon, falcon->addr2 + 0x668) & 0x00000001)
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break;
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) < 0)
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return -ETIMEDOUT;
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}
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return 0;
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}
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int
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ga102_flcn_fw_boot(struct nvkm_falcon_fw *fw, u32 *mbox0, u32 *mbox1, u32 mbox0_ok, u32 irqsclr)
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{
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struct nvkm_falcon *falcon = fw->falcon;
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nvkm_falcon_wr32(falcon, falcon->addr2 + 0x210, fw->dmem_sign);
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nvkm_falcon_wr32(falcon, falcon->addr2 + 0x19c, fw->engine_id);
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nvkm_falcon_wr32(falcon, falcon->addr2 + 0x198, fw->ucode_id);
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nvkm_falcon_wr32(falcon, falcon->addr2 + 0x180, 0x00000001);
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return gm200_flcn_fw_boot(fw, mbox0, mbox1, mbox0_ok, irqsclr);
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}
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int
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ga102_flcn_fw_load(struct nvkm_falcon_fw *fw)
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{
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struct nvkm_falcon *falcon = fw->falcon;
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int ret = 0;
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nvkm_falcon_mask(falcon, 0x624, 0x00000080, 0x00000080);
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nvkm_falcon_wr32(falcon, 0x10c, 0x00000000);
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nvkm_falcon_mask(falcon, 0x600, 0x00010007, (0 << 16) | (1 << 2) | 1);
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ret = nvkm_falcon_dma_wr(falcon, fw->fw.img, fw->fw.phys, fw->imem_base_img,
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IMEM, fw->imem_base, fw->imem_size, true);
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if (ret)
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return ret;
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ret = nvkm_falcon_dma_wr(falcon, fw->fw.img, fw->fw.phys, fw->dmem_base_img,
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DMEM, fw->dmem_base, fw->dmem_size, false);
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if (ret)
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return ret;
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return 0;
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}
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const struct nvkm_falcon_fw_func
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ga102_flcn_fw = {
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.signature = ga100_flcn_fw_signature,
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.reset = gm200_flcn_fw_reset,
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.load = ga102_flcn_fw_load,
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.boot = ga102_flcn_fw_boot,
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};
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