1008 lines
27 KiB
C
1008 lines
27 KiB
C
/*
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* Copyright 2013 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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* Roy Spliet <rspliet@eclipso.eu>
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*/
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#define gt215_ram(p) container_of((p), struct gt215_ram, base)
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#include "ram.h"
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#include "ramfuc.h"
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#include <core/memory.h>
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#include <core/option.h>
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#include <subdev/bios.h>
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#include <subdev/bios/M0205.h>
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#include <subdev/bios/rammap.h>
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#include <subdev/bios/timing.h>
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#include <subdev/clk/gt215.h>
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#include <subdev/gpio.h>
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struct gt215_ramfuc {
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struct ramfuc base;
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struct ramfuc_reg r_0x001610;
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struct ramfuc_reg r_0x001700;
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struct ramfuc_reg r_0x002504;
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struct ramfuc_reg r_0x004000;
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struct ramfuc_reg r_0x004004;
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struct ramfuc_reg r_0x004018;
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struct ramfuc_reg r_0x004128;
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struct ramfuc_reg r_0x004168;
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struct ramfuc_reg r_0x100080;
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struct ramfuc_reg r_0x100200;
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struct ramfuc_reg r_0x100210;
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struct ramfuc_reg r_0x100220[9];
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struct ramfuc_reg r_0x100264;
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struct ramfuc_reg r_0x1002d0;
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struct ramfuc_reg r_0x1002d4;
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struct ramfuc_reg r_0x1002dc;
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struct ramfuc_reg r_0x10053c;
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struct ramfuc_reg r_0x1005a0;
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struct ramfuc_reg r_0x1005a4;
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struct ramfuc_reg r_0x100700;
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struct ramfuc_reg r_0x100714;
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struct ramfuc_reg r_0x100718;
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struct ramfuc_reg r_0x10071c;
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struct ramfuc_reg r_0x100720;
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struct ramfuc_reg r_0x100760;
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struct ramfuc_reg r_0x1007a0;
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struct ramfuc_reg r_0x1007e0;
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struct ramfuc_reg r_0x100da0;
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struct ramfuc_reg r_0x10f804;
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struct ramfuc_reg r_0x1110e0;
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struct ramfuc_reg r_0x111100;
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struct ramfuc_reg r_0x111104;
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struct ramfuc_reg r_0x1111e0;
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struct ramfuc_reg r_0x111400;
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struct ramfuc_reg r_0x611200;
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struct ramfuc_reg r_mr[4];
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struct ramfuc_reg r_gpio[4];
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};
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struct gt215_ltrain {
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enum {
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NVA3_TRAIN_UNKNOWN,
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NVA3_TRAIN_UNSUPPORTED,
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NVA3_TRAIN_ONCE,
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NVA3_TRAIN_EXEC,
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NVA3_TRAIN_DONE
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} state;
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u32 r_100720;
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u32 r_1111e0;
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u32 r_111400;
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struct nvkm_memory *memory;
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};
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struct gt215_ram {
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struct nvkm_ram base;
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struct gt215_ramfuc fuc;
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struct gt215_ltrain ltrain;
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};
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static void
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gt215_link_train_calc(u32 *vals, struct gt215_ltrain *train)
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{
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int i, lo, hi;
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u8 median[8], bins[4] = {0, 0, 0, 0}, bin = 0, qty = 0;
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for (i = 0; i < 8; i++) {
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for (lo = 0; lo < 0x40; lo++) {
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if (!(vals[lo] & 0x80000000))
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continue;
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if (vals[lo] & (0x101 << i))
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break;
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}
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if (lo == 0x40)
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return;
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for (hi = lo + 1; hi < 0x40; hi++) {
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if (!(vals[lo] & 0x80000000))
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continue;
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if (!(vals[hi] & (0x101 << i))) {
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hi--;
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break;
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}
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}
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median[i] = ((hi - lo) >> 1) + lo;
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bins[(median[i] & 0xf0) >> 4]++;
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median[i] += 0x30;
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}
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/* Find the best value for 0x1111e0 */
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for (i = 0; i < 4; i++) {
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if (bins[i] > qty) {
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bin = i + 3;
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qty = bins[i];
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}
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}
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train->r_100720 = 0;
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for (i = 0; i < 8; i++) {
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median[i] = max(median[i], (u8) (bin << 4));
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median[i] = min(median[i], (u8) ((bin << 4) | 0xf));
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train->r_100720 |= ((median[i] & 0x0f) << (i << 2));
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}
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train->r_1111e0 = 0x02000000 | (bin * 0x101);
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train->r_111400 = 0x0;
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}
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/*
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* Link training for (at least) DDR3
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*/
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static int
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gt215_link_train(struct gt215_ram *ram)
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{
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struct gt215_ltrain *train = &ram->ltrain;
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struct gt215_ramfuc *fuc = &ram->fuc;
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struct nvkm_subdev *subdev = &ram->base.fb->subdev;
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struct nvkm_device *device = subdev->device;
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struct nvkm_bios *bios = device->bios;
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struct nvkm_clk *clk = device->clk;
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u32 *result, r1700;
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int ret, i;
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struct nvbios_M0205T M0205T = { 0 };
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u8 ver, hdr, cnt, len, snr, ssz;
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unsigned int clk_current;
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unsigned long flags;
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unsigned long *f = &flags;
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if (nvkm_boolopt(device->cfgopt, "NvMemExec", true) != true)
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return -ENOSYS;
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/* XXX: Multiple partitions? */
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result = kmalloc_array(64, sizeof(u32), GFP_KERNEL);
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if (!result)
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return -ENOMEM;
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train->state = NVA3_TRAIN_EXEC;
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/* Clock speeds for training and back */
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nvbios_M0205Tp(bios, &ver, &hdr, &cnt, &len, &snr, &ssz, &M0205T);
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if (M0205T.freq == 0) {
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kfree(result);
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return -ENOENT;
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}
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clk_current = nvkm_clk_read(clk, nv_clk_src_mem);
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ret = gt215_clk_pre(clk, f);
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if (ret)
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goto out;
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/* First: clock up/down */
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ret = ram->base.func->calc(&ram->base, (u32) M0205T.freq * 1000);
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if (ret)
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goto out;
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/* Do this *after* calc, eliminates write in script */
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nvkm_wr32(device, 0x111400, 0x00000000);
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/* XXX: Magic writes that improve train reliability? */
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nvkm_mask(device, 0x100674, 0x0000ffff, 0x00000000);
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nvkm_mask(device, 0x1005e4, 0x0000ffff, 0x00000000);
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nvkm_mask(device, 0x100b0c, 0x000000ff, 0x00000000);
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nvkm_wr32(device, 0x100c04, 0x00000400);
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/* Now the training script */
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r1700 = ram_rd32(fuc, 0x001700);
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ram_mask(fuc, 0x100200, 0x00000800, 0x00000000);
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ram_wr32(fuc, 0x611200, 0x3300);
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ram_wait_vblank(fuc);
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ram_wait(fuc, 0x611200, 0x00000003, 0x00000000, 500000);
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ram_mask(fuc, 0x001610, 0x00000083, 0x00000003);
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ram_mask(fuc, 0x100080, 0x00000020, 0x00000000);
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ram_mask(fuc, 0x10f804, 0x80000000, 0x00000000);
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ram_wr32(fuc, 0x001700, 0x00000000);
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ram_train(fuc);
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/* Reset */
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ram_mask(fuc, 0x10f804, 0x80000000, 0x80000000);
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ram_wr32(fuc, 0x10053c, 0x0);
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ram_wr32(fuc, 0x100720, train->r_100720);
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ram_wr32(fuc, 0x1111e0, train->r_1111e0);
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ram_wr32(fuc, 0x111400, train->r_111400);
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ram_nuke(fuc, 0x100080);
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ram_mask(fuc, 0x100080, 0x00000020, 0x00000020);
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ram_nsec(fuc, 1000);
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ram_wr32(fuc, 0x001700, r1700);
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ram_mask(fuc, 0x001610, 0x00000083, 0x00000080);
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ram_wr32(fuc, 0x611200, 0x3330);
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ram_mask(fuc, 0x100200, 0x00000800, 0x00000800);
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ram_exec(fuc, true);
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ram->base.func->calc(&ram->base, clk_current);
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ram_exec(fuc, true);
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/* Post-processing, avoids flicker */
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nvkm_mask(device, 0x616308, 0x10, 0x10);
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nvkm_mask(device, 0x616b08, 0x10, 0x10);
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gt215_clk_post(clk, f);
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ram_train_result(ram->base.fb, result, 64);
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for (i = 0; i < 64; i++)
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nvkm_debug(subdev, "Train: %08x", result[i]);
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gt215_link_train_calc(result, train);
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nvkm_debug(subdev, "Train: %08x %08x %08x", train->r_100720,
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train->r_1111e0, train->r_111400);
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kfree(result);
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train->state = NVA3_TRAIN_DONE;
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return ret;
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out:
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if(ret == -EBUSY)
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f = NULL;
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train->state = NVA3_TRAIN_UNSUPPORTED;
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gt215_clk_post(clk, f);
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kfree(result);
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return ret;
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}
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static int
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gt215_link_train_init(struct gt215_ram *ram)
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{
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static const u32 pattern[16] = {
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0xaaaaaaaa, 0xcccccccc, 0xdddddddd, 0xeeeeeeee,
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0x00000000, 0x11111111, 0x44444444, 0xdddddddd,
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0x33333333, 0x55555555, 0x77777777, 0x66666666,
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0x99999999, 0x88888888, 0xeeeeeeee, 0xbbbbbbbb,
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};
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struct gt215_ltrain *train = &ram->ltrain;
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struct nvkm_device *device = ram->base.fb->subdev.device;
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struct nvkm_bios *bios = device->bios;
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struct nvbios_M0205E M0205E;
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u8 ver, hdr, cnt, len;
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u32 r001700;
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u64 addr;
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int ret, i = 0;
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train->state = NVA3_TRAIN_UNSUPPORTED;
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/* We support type "5"
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* XXX: training pattern table appears to be unused for this routine */
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if (!nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E))
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return -ENOENT;
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if (M0205E.type != 5)
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return 0;
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train->state = NVA3_TRAIN_ONCE;
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ret = nvkm_ram_get(device, NVKM_RAM_MM_NORMAL, 0x01, 16, 0x8000,
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true, true, &ram->ltrain.memory);
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if (ret)
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return ret;
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addr = nvkm_memory_addr(ram->ltrain.memory);
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nvkm_wr32(device, 0x100538, 0x10000000 | (addr >> 16));
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nvkm_wr32(device, 0x1005a8, 0x0000ffff);
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nvkm_mask(device, 0x10f800, 0x00000001, 0x00000001);
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for (i = 0; i < 0x30; i++) {
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nvkm_wr32(device, 0x10f8c0, (i << 8) | i);
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nvkm_wr32(device, 0x10f900, pattern[i % 16]);
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}
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for (i = 0; i < 0x30; i++) {
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nvkm_wr32(device, 0x10f8e0, (i << 8) | i);
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nvkm_wr32(device, 0x10f920, pattern[i % 16]);
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}
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/* And upload the pattern */
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r001700 = nvkm_rd32(device, 0x1700);
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nvkm_wr32(device, 0x1700, addr >> 16);
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for (i = 0; i < 16; i++)
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nvkm_wr32(device, 0x700000 + (i << 2), pattern[i]);
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for (i = 0; i < 16; i++)
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nvkm_wr32(device, 0x700100 + (i << 2), pattern[i]);
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nvkm_wr32(device, 0x1700, r001700);
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train->r_100720 = nvkm_rd32(device, 0x100720);
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train->r_1111e0 = nvkm_rd32(device, 0x1111e0);
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train->r_111400 = nvkm_rd32(device, 0x111400);
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return 0;
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}
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static void
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gt215_link_train_fini(struct gt215_ram *ram)
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{
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nvkm_memory_unref(&ram->ltrain.memory);
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}
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/*
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* RAM reclocking
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*/
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#define T(t) cfg->timing_10_##t
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static int
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gt215_ram_timing_calc(struct gt215_ram *ram, u32 *timing)
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{
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struct nvbios_ramcfg *cfg = &ram->base.target.bios;
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struct nvkm_subdev *subdev = &ram->base.fb->subdev;
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struct nvkm_device *device = subdev->device;
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int tUNK_base, tUNK_40_0, prevCL;
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u32 cur2, cur3, cur7, cur8;
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cur2 = nvkm_rd32(device, 0x100228);
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cur3 = nvkm_rd32(device, 0x10022c);
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cur7 = nvkm_rd32(device, 0x10023c);
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cur8 = nvkm_rd32(device, 0x100240);
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switch ((!T(CWL)) * ram->base.type) {
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case NVKM_RAM_TYPE_DDR2:
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T(CWL) = T(CL) - 1;
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break;
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case NVKM_RAM_TYPE_GDDR3:
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T(CWL) = ((cur2 & 0xff000000) >> 24) + 1;
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break;
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}
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prevCL = (cur3 & 0x000000ff) + 1;
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tUNK_base = ((cur7 & 0x00ff0000) >> 16) - prevCL;
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timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC));
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timing[1] = (T(WR) + 1 + T(CWL)) << 24 |
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max_t(u8,T(18), 1) << 16 |
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(T(WTR) + 1 + T(CWL)) << 8 |
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(5 + T(CL) - T(CWL));
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timing[2] = (T(CWL) - 1) << 24 |
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(T(RRD) << 16) |
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(T(RCDWR) << 8) |
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T(RCDRD);
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timing[3] = (cur3 & 0x00ff0000) |
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(0x30 + T(CL)) << 24 |
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(0xb + T(CL)) << 8 |
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(T(CL) - 1);
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timing[4] = T(20) << 24 |
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T(21) << 16 |
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T(13) << 8 |
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T(13);
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timing[5] = T(RFC) << 24 |
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max_t(u8,T(RCDRD), T(RCDWR)) << 16 |
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max_t(u8, (T(CWL) + 6), (T(CL) + 2)) << 8 |
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T(RP);
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timing[6] = (0x5a + T(CL)) << 16 |
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max_t(u8, 1, (6 - T(CL) + T(CWL))) << 8 |
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(0x50 + T(CL) - T(CWL));
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timing[7] = (cur7 & 0xff000000) |
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((tUNK_base + T(CL)) << 16) |
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0x202;
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timing[8] = cur8 & 0xffffff00;
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switch (ram->base.type) {
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case NVKM_RAM_TYPE_DDR2:
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case NVKM_RAM_TYPE_GDDR3:
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tUNK_40_0 = prevCL - (cur8 & 0xff);
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if (tUNK_40_0 > 0)
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timing[8] |= T(CL);
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break;
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default:
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break;
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}
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nvkm_debug(subdev, "Entry: 220: %08x %08x %08x %08x\n",
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timing[0], timing[1], timing[2], timing[3]);
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nvkm_debug(subdev, " 230: %08x %08x %08x %08x\n",
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timing[4], timing[5], timing[6], timing[7]);
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nvkm_debug(subdev, " 240: %08x\n", timing[8]);
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return 0;
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}
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#undef T
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static void
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nvkm_sddr2_dll_reset(struct gt215_ramfuc *fuc)
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{
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ram_mask(fuc, mr[0], 0x100, 0x100);
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ram_nsec(fuc, 1000);
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ram_mask(fuc, mr[0], 0x100, 0x000);
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ram_nsec(fuc, 1000);
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}
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static void
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nvkm_sddr3_dll_disable(struct gt215_ramfuc *fuc, u32 *mr)
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{
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u32 mr1_old = ram_rd32(fuc, mr[1]);
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if (!(mr1_old & 0x1)) {
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ram_wr32(fuc, 0x1002d4, 0x00000001);
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ram_wr32(fuc, mr[1], mr[1]);
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ram_nsec(fuc, 1000);
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}
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}
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static void
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nvkm_gddr3_dll_disable(struct gt215_ramfuc *fuc, u32 *mr)
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{
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u32 mr1_old = ram_rd32(fuc, mr[1]);
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if (!(mr1_old & 0x40)) {
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ram_wr32(fuc, mr[1], mr[1]);
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ram_nsec(fuc, 1000);
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}
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|
}
|
|
|
|
static void
|
|
gt215_ram_lock_pll(struct gt215_ramfuc *fuc, struct gt215_clk_info *mclk)
|
|
{
|
|
ram_wr32(fuc, 0x004004, mclk->pll);
|
|
ram_mask(fuc, 0x004000, 0x00000001, 0x00000001);
|
|
ram_mask(fuc, 0x004000, 0x00000010, 0x00000000);
|
|
ram_wait(fuc, 0x004000, 0x00020000, 0x00020000, 64000);
|
|
ram_mask(fuc, 0x004000, 0x00000010, 0x00000010);
|
|
}
|
|
|
|
static void
|
|
gt215_ram_gpio(struct gt215_ramfuc *fuc, u8 tag, u32 val)
|
|
{
|
|
struct nvkm_gpio *gpio = fuc->base.fb->subdev.device->gpio;
|
|
struct dcb_gpio_func func;
|
|
u32 reg, sh, gpio_val;
|
|
int ret;
|
|
|
|
if (nvkm_gpio_get(gpio, 0, tag, DCB_GPIO_UNUSED) != val) {
|
|
ret = nvkm_gpio_find(gpio, 0, tag, DCB_GPIO_UNUSED, &func);
|
|
if (ret)
|
|
return;
|
|
|
|
reg = func.line >> 3;
|
|
sh = (func.line & 0x7) << 2;
|
|
gpio_val = ram_rd32(fuc, gpio[reg]);
|
|
if (gpio_val & (8 << sh))
|
|
val = !val;
|
|
if (!(func.log[1] & 1))
|
|
val = !val;
|
|
|
|
ram_mask(fuc, gpio[reg], (0x3 << sh), ((val | 0x2) << sh));
|
|
ram_nsec(fuc, 20000);
|
|
}
|
|
}
|
|
|
|
static int
|
|
gt215_ram_calc(struct nvkm_ram *base, u32 freq)
|
|
{
|
|
struct gt215_ram *ram = gt215_ram(base);
|
|
struct gt215_ramfuc *fuc = &ram->fuc;
|
|
struct gt215_ltrain *train = &ram->ltrain;
|
|
struct nvkm_subdev *subdev = &ram->base.fb->subdev;
|
|
struct nvkm_device *device = subdev->device;
|
|
struct nvkm_bios *bios = device->bios;
|
|
struct gt215_clk_info mclk;
|
|
struct nvkm_gpio *gpio = device->gpio;
|
|
struct nvkm_ram_data *next;
|
|
u8 ver, hdr, cnt, len, strap;
|
|
u32 data;
|
|
u32 r004018, r100760, r100da0, r111100, ctrl;
|
|
u32 unk714, unk718, unk71c;
|
|
int ret, i;
|
|
u32 timing[9];
|
|
bool pll2pll;
|
|
|
|
next = &ram->base.target;
|
|
next->freq = freq;
|
|
ram->base.next = next;
|
|
|
|
if (ram->ltrain.state == NVA3_TRAIN_ONCE)
|
|
gt215_link_train(ram);
|
|
|
|
/* lookup memory config data relevant to the target frequency */
|
|
data = nvbios_rammapEm(bios, freq / 1000, &ver, &hdr, &cnt, &len,
|
|
&next->bios);
|
|
if (!data || ver != 0x10 || hdr < 0x05) {
|
|
nvkm_error(subdev, "invalid/missing rammap entry\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* locate specific data set for the attached memory */
|
|
strap = nvbios_ramcfg_index(subdev);
|
|
if (strap >= cnt) {
|
|
nvkm_error(subdev, "invalid ramcfg strap\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, strap,
|
|
&ver, &hdr, &next->bios);
|
|
if (!data || ver != 0x10 || hdr < 0x09) {
|
|
nvkm_error(subdev, "invalid/missing ramcfg entry\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* lookup memory timings, if bios says they're present */
|
|
if (next->bios.ramcfg_timing != 0xff) {
|
|
data = nvbios_timingEp(bios, next->bios.ramcfg_timing,
|
|
&ver, &hdr, &cnt, &len,
|
|
&next->bios);
|
|
if (!data || ver != 0x10 || hdr < 0x17) {
|
|
nvkm_error(subdev, "invalid/missing timing entry\n");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
ret = gt215_pll_info(device->clk, 0x12, 0x4000, freq, &mclk);
|
|
if (ret < 0) {
|
|
nvkm_error(subdev, "failed mclk calculation\n");
|
|
return ret;
|
|
}
|
|
|
|
gt215_ram_timing_calc(ram, timing);
|
|
|
|
ret = ram_init(fuc, ram->base.fb);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Determine ram-specific MR values */
|
|
ram->base.mr[0] = ram_rd32(fuc, mr[0]);
|
|
ram->base.mr[1] = ram_rd32(fuc, mr[1]);
|
|
ram->base.mr[2] = ram_rd32(fuc, mr[2]);
|
|
|
|
switch (ram->base.type) {
|
|
case NVKM_RAM_TYPE_DDR2:
|
|
ret = nvkm_sddr2_calc(&ram->base);
|
|
break;
|
|
case NVKM_RAM_TYPE_DDR3:
|
|
ret = nvkm_sddr3_calc(&ram->base);
|
|
break;
|
|
case NVKM_RAM_TYPE_GDDR3:
|
|
ret = nvkm_gddr3_calc(&ram->base);
|
|
break;
|
|
default:
|
|
ret = -ENOSYS;
|
|
break;
|
|
}
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* XXX: 750MHz seems rather arbitrary */
|
|
if (freq <= 750000) {
|
|
r004018 = 0x10000000;
|
|
r100760 = 0x22222222;
|
|
r100da0 = 0x00000010;
|
|
} else {
|
|
r004018 = 0x00000000;
|
|
r100760 = 0x00000000;
|
|
r100da0 = 0x00000000;
|
|
}
|
|
|
|
if (!next->bios.ramcfg_DLLoff)
|
|
r004018 |= 0x00004000;
|
|
|
|
/* pll2pll requires to switch to a safe clock first */
|
|
ctrl = ram_rd32(fuc, 0x004000);
|
|
pll2pll = (!(ctrl & 0x00000008)) && mclk.pll;
|
|
|
|
/* Pre, NVIDIA does this outside the script */
|
|
if (next->bios.ramcfg_10_02_10) {
|
|
ram_mask(fuc, 0x111104, 0x00000600, 0x00000000);
|
|
} else {
|
|
ram_mask(fuc, 0x111100, 0x40000000, 0x40000000);
|
|
ram_mask(fuc, 0x111104, 0x00000180, 0x00000000);
|
|
}
|
|
/* Always disable this bit during reclock */
|
|
ram_mask(fuc, 0x100200, 0x00000800, 0x00000000);
|
|
|
|
/* If switching from non-pll to pll, lock before disabling FB */
|
|
if (mclk.pll && !pll2pll) {
|
|
ram_mask(fuc, 0x004128, 0x003f3141, mclk.clk | 0x00000101);
|
|
gt215_ram_lock_pll(fuc, &mclk);
|
|
}
|
|
|
|
/* Start with disabling some CRTCs and PFIFO? */
|
|
ram_wait_vblank(fuc);
|
|
ram_wr32(fuc, 0x611200, 0x3300);
|
|
ram_mask(fuc, 0x002504, 0x1, 0x1);
|
|
ram_nsec(fuc, 10000);
|
|
ram_wait(fuc, 0x002504, 0x10, 0x10, 20000); /* XXX: or longer? */
|
|
ram_block(fuc);
|
|
ram_nsec(fuc, 2000);
|
|
|
|
if (!next->bios.ramcfg_10_02_10) {
|
|
if (ram->base.type == NVKM_RAM_TYPE_GDDR3)
|
|
ram_mask(fuc, 0x111100, 0x04020000, 0x00020000);
|
|
else
|
|
ram_mask(fuc, 0x111100, 0x04020000, 0x04020000);
|
|
}
|
|
|
|
/* If we're disabling the DLL, do it now */
|
|
switch (next->bios.ramcfg_DLLoff * ram->base.type) {
|
|
case NVKM_RAM_TYPE_DDR3:
|
|
nvkm_sddr3_dll_disable(fuc, ram->base.mr);
|
|
break;
|
|
case NVKM_RAM_TYPE_GDDR3:
|
|
nvkm_gddr3_dll_disable(fuc, ram->base.mr);
|
|
break;
|
|
}
|
|
|
|
if (next->bios.timing_10_ODT)
|
|
gt215_ram_gpio(fuc, 0x2e, 1);
|
|
|
|
/* Brace RAM for impact */
|
|
ram_wr32(fuc, 0x1002d4, 0x00000001);
|
|
ram_wr32(fuc, 0x1002d0, 0x00000001);
|
|
ram_wr32(fuc, 0x1002d0, 0x00000001);
|
|
ram_wr32(fuc, 0x100210, 0x00000000);
|
|
ram_wr32(fuc, 0x1002dc, 0x00000001);
|
|
ram_nsec(fuc, 2000);
|
|
|
|
if (device->chipset == 0xa3 && freq <= 500000)
|
|
ram_mask(fuc, 0x100700, 0x00000006, 0x00000006);
|
|
|
|
/* Alter FBVDD/Q, apparently must be done with PLL disabled, thus
|
|
* set it to bypass */
|
|
if (nvkm_gpio_get(gpio, 0, 0x18, DCB_GPIO_UNUSED) ==
|
|
next->bios.ramcfg_FBVDDQ) {
|
|
data = ram_rd32(fuc, 0x004000) & 0x9;
|
|
|
|
if (data == 0x1)
|
|
ram_mask(fuc, 0x004000, 0x8, 0x8);
|
|
if (data & 0x1)
|
|
ram_mask(fuc, 0x004000, 0x1, 0x0);
|
|
|
|
gt215_ram_gpio(fuc, 0x18, !next->bios.ramcfg_FBVDDQ);
|
|
|
|
if (data & 0x1)
|
|
ram_mask(fuc, 0x004000, 0x1, 0x1);
|
|
}
|
|
|
|
/* Fiddle with clocks */
|
|
/* There's 4 scenario's
|
|
* pll->pll: first switch to a 324MHz clock, set up new PLL, switch
|
|
* clk->pll: Set up new PLL, switch
|
|
* pll->clk: Set up clock, switch
|
|
* clk->clk: Overwrite ctrl and other bits, switch */
|
|
|
|
/* Switch to regular clock - 324MHz */
|
|
if (pll2pll) {
|
|
ram_mask(fuc, 0x004000, 0x00000004, 0x00000004);
|
|
ram_mask(fuc, 0x004168, 0x003f3141, 0x00083101);
|
|
ram_mask(fuc, 0x004000, 0x00000008, 0x00000008);
|
|
ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000);
|
|
ram_wr32(fuc, 0x004018, 0x00001000);
|
|
gt215_ram_lock_pll(fuc, &mclk);
|
|
}
|
|
|
|
if (mclk.pll) {
|
|
ram_mask(fuc, 0x004000, 0x00000105, 0x00000105);
|
|
ram_wr32(fuc, 0x004018, 0x00001000 | r004018);
|
|
ram_wr32(fuc, 0x100da0, r100da0);
|
|
} else {
|
|
ram_mask(fuc, 0x004168, 0x003f3141, mclk.clk | 0x00000101);
|
|
ram_mask(fuc, 0x004000, 0x00000108, 0x00000008);
|
|
ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000);
|
|
ram_wr32(fuc, 0x004018, 0x00009000 | r004018);
|
|
ram_wr32(fuc, 0x100da0, r100da0);
|
|
}
|
|
ram_nsec(fuc, 20000);
|
|
|
|
if (next->bios.rammap_10_04_08) {
|
|
ram_wr32(fuc, 0x1005a0, next->bios.ramcfg_10_06 << 16 |
|
|
next->bios.ramcfg_10_05 << 8 |
|
|
next->bios.ramcfg_10_05);
|
|
ram_wr32(fuc, 0x1005a4, next->bios.ramcfg_10_08 << 8 |
|
|
next->bios.ramcfg_10_07);
|
|
ram_wr32(fuc, 0x10f804, next->bios.ramcfg_10_09_f0 << 20 |
|
|
next->bios.ramcfg_10_03_0f << 16 |
|
|
next->bios.ramcfg_10_09_0f |
|
|
0x80000000);
|
|
ram_mask(fuc, 0x10053c, 0x00001000, 0x00000000);
|
|
} else {
|
|
if (train->state == NVA3_TRAIN_DONE) {
|
|
ram_wr32(fuc, 0x100080, 0x1020);
|
|
ram_mask(fuc, 0x111400, 0xffffffff, train->r_111400);
|
|
ram_mask(fuc, 0x1111e0, 0xffffffff, train->r_1111e0);
|
|
ram_mask(fuc, 0x100720, 0xffffffff, train->r_100720);
|
|
}
|
|
ram_mask(fuc, 0x10053c, 0x00001000, 0x00001000);
|
|
ram_mask(fuc, 0x10f804, 0x80000000, 0x00000000);
|
|
ram_mask(fuc, 0x100760, 0x22222222, r100760);
|
|
ram_mask(fuc, 0x1007a0, 0x22222222, r100760);
|
|
ram_mask(fuc, 0x1007e0, 0x22222222, r100760);
|
|
}
|
|
|
|
if (device->chipset == 0xa3 && freq > 500000) {
|
|
ram_mask(fuc, 0x100700, 0x00000006, 0x00000000);
|
|
}
|
|
|
|
/* Final switch */
|
|
if (mclk.pll) {
|
|
ram_mask(fuc, 0x1110e0, 0x00088000, 0x00011000);
|
|
ram_mask(fuc, 0x004000, 0x00000008, 0x00000000);
|
|
}
|
|
|
|
ram_wr32(fuc, 0x1002dc, 0x00000000);
|
|
ram_wr32(fuc, 0x1002d4, 0x00000001);
|
|
ram_wr32(fuc, 0x100210, 0x80000000);
|
|
ram_nsec(fuc, 2000);
|
|
|
|
/* Set RAM MR parameters and timings */
|
|
for (i = 2; i >= 0; i--) {
|
|
if (ram_rd32(fuc, mr[i]) != ram->base.mr[i]) {
|
|
ram_wr32(fuc, mr[i], ram->base.mr[i]);
|
|
ram_nsec(fuc, 1000);
|
|
}
|
|
}
|
|
|
|
ram_wr32(fuc, 0x100220[3], timing[3]);
|
|
ram_wr32(fuc, 0x100220[1], timing[1]);
|
|
ram_wr32(fuc, 0x100220[6], timing[6]);
|
|
ram_wr32(fuc, 0x100220[7], timing[7]);
|
|
ram_wr32(fuc, 0x100220[2], timing[2]);
|
|
ram_wr32(fuc, 0x100220[4], timing[4]);
|
|
ram_wr32(fuc, 0x100220[5], timing[5]);
|
|
ram_wr32(fuc, 0x100220[0], timing[0]);
|
|
ram_wr32(fuc, 0x100220[8], timing[8]);
|
|
|
|
/* Misc */
|
|
ram_mask(fuc, 0x100200, 0x00001000, !next->bios.ramcfg_10_02_08 << 12);
|
|
|
|
/* XXX: A lot of "chipset"/"ram type" specific stuff...? */
|
|
unk714 = ram_rd32(fuc, 0x100714) & ~0xf0000130;
|
|
unk718 = ram_rd32(fuc, 0x100718) & ~0x00000100;
|
|
unk71c = ram_rd32(fuc, 0x10071c) & ~0x00000100;
|
|
r111100 = ram_rd32(fuc, 0x111100) & ~0x3a800000;
|
|
|
|
/* NVA8 seems to skip various bits related to ramcfg_10_02_04 */
|
|
if (device->chipset == 0xa8) {
|
|
r111100 |= 0x08000000;
|
|
if (!next->bios.ramcfg_10_02_04)
|
|
unk714 |= 0x00000010;
|
|
} else {
|
|
if (next->bios.ramcfg_10_02_04) {
|
|
switch (ram->base.type) {
|
|
case NVKM_RAM_TYPE_DDR2:
|
|
case NVKM_RAM_TYPE_DDR3:
|
|
r111100 &= ~0x00000020;
|
|
if (next->bios.ramcfg_10_02_10)
|
|
r111100 |= 0x08000004;
|
|
else
|
|
r111100 |= 0x00000024;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
} else {
|
|
switch (ram->base.type) {
|
|
case NVKM_RAM_TYPE_DDR2:
|
|
case NVKM_RAM_TYPE_DDR3:
|
|
r111100 &= ~0x00000024;
|
|
r111100 |= 0x12800000;
|
|
|
|
if (next->bios.ramcfg_10_02_10)
|
|
r111100 |= 0x08000000;
|
|
unk714 |= 0x00000010;
|
|
break;
|
|
case NVKM_RAM_TYPE_GDDR3:
|
|
r111100 |= 0x30000000;
|
|
unk714 |= 0x00000020;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
unk714 |= (next->bios.ramcfg_10_04_01) << 8;
|
|
|
|
if (next->bios.ramcfg_10_02_20)
|
|
unk714 |= 0xf0000000;
|
|
if (next->bios.ramcfg_10_02_02)
|
|
unk718 |= 0x00000100;
|
|
if (next->bios.ramcfg_10_02_01)
|
|
unk71c |= 0x00000100;
|
|
if (next->bios.timing_10_24 != 0xff) {
|
|
unk718 &= ~0xf0000000;
|
|
unk718 |= next->bios.timing_10_24 << 28;
|
|
}
|
|
if (next->bios.ramcfg_10_02_10)
|
|
r111100 &= ~0x04020000;
|
|
|
|
ram_mask(fuc, 0x100714, 0xffffffff, unk714);
|
|
ram_mask(fuc, 0x10071c, 0xffffffff, unk71c);
|
|
ram_mask(fuc, 0x100718, 0xffffffff, unk718);
|
|
ram_mask(fuc, 0x111100, 0xffffffff, r111100);
|
|
|
|
if (!next->bios.timing_10_ODT)
|
|
gt215_ram_gpio(fuc, 0x2e, 0);
|
|
|
|
/* Reset DLL */
|
|
if (!next->bios.ramcfg_DLLoff)
|
|
nvkm_sddr2_dll_reset(fuc);
|
|
|
|
if (ram->base.type == NVKM_RAM_TYPE_GDDR3) {
|
|
ram_nsec(fuc, 31000);
|
|
} else {
|
|
ram_nsec(fuc, 14000);
|
|
}
|
|
|
|
if (ram->base.type == NVKM_RAM_TYPE_DDR3) {
|
|
ram_wr32(fuc, 0x100264, 0x1);
|
|
ram_nsec(fuc, 2000);
|
|
}
|
|
|
|
ram_nuke(fuc, 0x100700);
|
|
ram_mask(fuc, 0x100700, 0x01000000, 0x01000000);
|
|
ram_mask(fuc, 0x100700, 0x01000000, 0x00000000);
|
|
|
|
/* Re-enable FB */
|
|
ram_unblock(fuc);
|
|
ram_wr32(fuc, 0x611200, 0x3330);
|
|
|
|
/* Post fiddlings */
|
|
if (next->bios.rammap_10_04_02)
|
|
ram_mask(fuc, 0x100200, 0x00000800, 0x00000800);
|
|
if (next->bios.ramcfg_10_02_10) {
|
|
ram_mask(fuc, 0x111104, 0x00000180, 0x00000180);
|
|
ram_mask(fuc, 0x111100, 0x40000000, 0x00000000);
|
|
} else {
|
|
ram_mask(fuc, 0x111104, 0x00000600, 0x00000600);
|
|
}
|
|
|
|
if (mclk.pll) {
|
|
ram_mask(fuc, 0x004168, 0x00000001, 0x00000000);
|
|
ram_mask(fuc, 0x004168, 0x00000100, 0x00000000);
|
|
} else {
|
|
ram_mask(fuc, 0x004000, 0x00000001, 0x00000000);
|
|
ram_mask(fuc, 0x004128, 0x00000001, 0x00000000);
|
|
ram_mask(fuc, 0x004128, 0x00000100, 0x00000000);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
gt215_ram_prog(struct nvkm_ram *base)
|
|
{
|
|
struct gt215_ram *ram = gt215_ram(base);
|
|
struct gt215_ramfuc *fuc = &ram->fuc;
|
|
struct nvkm_device *device = ram->base.fb->subdev.device;
|
|
bool exec = nvkm_boolopt(device->cfgopt, "NvMemExec", true);
|
|
|
|
if (exec) {
|
|
nvkm_mask(device, 0x001534, 0x2, 0x2);
|
|
|
|
ram_exec(fuc, true);
|
|
|
|
/* Post-processing, avoids flicker */
|
|
nvkm_mask(device, 0x002504, 0x1, 0x0);
|
|
nvkm_mask(device, 0x001534, 0x2, 0x0);
|
|
|
|
nvkm_mask(device, 0x616308, 0x10, 0x10);
|
|
nvkm_mask(device, 0x616b08, 0x10, 0x10);
|
|
} else {
|
|
ram_exec(fuc, false);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
gt215_ram_tidy(struct nvkm_ram *base)
|
|
{
|
|
struct gt215_ram *ram = gt215_ram(base);
|
|
ram_exec(&ram->fuc, false);
|
|
}
|
|
|
|
static int
|
|
gt215_ram_init(struct nvkm_ram *base)
|
|
{
|
|
struct gt215_ram *ram = gt215_ram(base);
|
|
gt215_link_train_init(ram);
|
|
return 0;
|
|
}
|
|
|
|
static void *
|
|
gt215_ram_dtor(struct nvkm_ram *base)
|
|
{
|
|
struct gt215_ram *ram = gt215_ram(base);
|
|
gt215_link_train_fini(ram);
|
|
return ram;
|
|
}
|
|
|
|
static const struct nvkm_ram_func
|
|
gt215_ram_func = {
|
|
.dtor = gt215_ram_dtor,
|
|
.init = gt215_ram_init,
|
|
.calc = gt215_ram_calc,
|
|
.prog = gt215_ram_prog,
|
|
.tidy = gt215_ram_tidy,
|
|
};
|
|
|
|
int
|
|
gt215_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram)
|
|
{
|
|
struct gt215_ram *ram;
|
|
int ret, i;
|
|
|
|
if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL)))
|
|
return -ENOMEM;
|
|
*pram = &ram->base;
|
|
|
|
ret = nv50_ram_ctor(>215_ram_func, fb, &ram->base);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ram->fuc.r_0x001610 = ramfuc_reg(0x001610);
|
|
ram->fuc.r_0x001700 = ramfuc_reg(0x001700);
|
|
ram->fuc.r_0x002504 = ramfuc_reg(0x002504);
|
|
ram->fuc.r_0x004000 = ramfuc_reg(0x004000);
|
|
ram->fuc.r_0x004004 = ramfuc_reg(0x004004);
|
|
ram->fuc.r_0x004018 = ramfuc_reg(0x004018);
|
|
ram->fuc.r_0x004128 = ramfuc_reg(0x004128);
|
|
ram->fuc.r_0x004168 = ramfuc_reg(0x004168);
|
|
ram->fuc.r_0x100080 = ramfuc_reg(0x100080);
|
|
ram->fuc.r_0x100200 = ramfuc_reg(0x100200);
|
|
ram->fuc.r_0x100210 = ramfuc_reg(0x100210);
|
|
for (i = 0; i < 9; i++)
|
|
ram->fuc.r_0x100220[i] = ramfuc_reg(0x100220 + (i * 4));
|
|
ram->fuc.r_0x100264 = ramfuc_reg(0x100264);
|
|
ram->fuc.r_0x1002d0 = ramfuc_reg(0x1002d0);
|
|
ram->fuc.r_0x1002d4 = ramfuc_reg(0x1002d4);
|
|
ram->fuc.r_0x1002dc = ramfuc_reg(0x1002dc);
|
|
ram->fuc.r_0x10053c = ramfuc_reg(0x10053c);
|
|
ram->fuc.r_0x1005a0 = ramfuc_reg(0x1005a0);
|
|
ram->fuc.r_0x1005a4 = ramfuc_reg(0x1005a4);
|
|
ram->fuc.r_0x100700 = ramfuc_reg(0x100700);
|
|
ram->fuc.r_0x100714 = ramfuc_reg(0x100714);
|
|
ram->fuc.r_0x100718 = ramfuc_reg(0x100718);
|
|
ram->fuc.r_0x10071c = ramfuc_reg(0x10071c);
|
|
ram->fuc.r_0x100720 = ramfuc_reg(0x100720);
|
|
ram->fuc.r_0x100760 = ramfuc_stride(0x100760, 4, ram->base.part_mask);
|
|
ram->fuc.r_0x1007a0 = ramfuc_stride(0x1007a0, 4, ram->base.part_mask);
|
|
ram->fuc.r_0x1007e0 = ramfuc_stride(0x1007e0, 4, ram->base.part_mask);
|
|
ram->fuc.r_0x100da0 = ramfuc_stride(0x100da0, 4, ram->base.part_mask);
|
|
ram->fuc.r_0x10f804 = ramfuc_reg(0x10f804);
|
|
ram->fuc.r_0x1110e0 = ramfuc_stride(0x1110e0, 4, ram->base.part_mask);
|
|
ram->fuc.r_0x111100 = ramfuc_reg(0x111100);
|
|
ram->fuc.r_0x111104 = ramfuc_reg(0x111104);
|
|
ram->fuc.r_0x1111e0 = ramfuc_reg(0x1111e0);
|
|
ram->fuc.r_0x111400 = ramfuc_reg(0x111400);
|
|
ram->fuc.r_0x611200 = ramfuc_reg(0x611200);
|
|
|
|
if (ram->base.ranks > 1) {
|
|
ram->fuc.r_mr[0] = ramfuc_reg2(0x1002c0, 0x1002c8);
|
|
ram->fuc.r_mr[1] = ramfuc_reg2(0x1002c4, 0x1002cc);
|
|
ram->fuc.r_mr[2] = ramfuc_reg2(0x1002e0, 0x1002e8);
|
|
ram->fuc.r_mr[3] = ramfuc_reg2(0x1002e4, 0x1002ec);
|
|
} else {
|
|
ram->fuc.r_mr[0] = ramfuc_reg(0x1002c0);
|
|
ram->fuc.r_mr[1] = ramfuc_reg(0x1002c4);
|
|
ram->fuc.r_mr[2] = ramfuc_reg(0x1002e0);
|
|
ram->fuc.r_mr[3] = ramfuc_reg(0x1002e4);
|
|
}
|
|
ram->fuc.r_gpio[0] = ramfuc_reg(0x00e104);
|
|
ram->fuc.r_gpio[1] = ramfuc_reg(0x00e108);
|
|
ram->fuc.r_gpio[2] = ramfuc_reg(0x00e120);
|
|
ram->fuc.r_gpio[3] = ramfuc_reg(0x00e124);
|
|
|
|
return 0;
|
|
}
|