224 lines
6.2 KiB
C
224 lines
6.2 KiB
C
/*
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* Copyright 2013 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "ramnv40.h"
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#include <subdev/bios.h>
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#include <subdev/bios/bit.h>
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#include <subdev/bios/init.h>
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#include <subdev/bios/pll.h>
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#include <subdev/clk/pll.h>
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#include <subdev/timer.h>
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static int
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nv40_ram_calc(struct nvkm_ram *base, u32 freq)
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{
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struct nv40_ram *ram = nv40_ram(base);
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struct nvkm_subdev *subdev = &ram->base.fb->subdev;
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struct nvkm_bios *bios = subdev->device->bios;
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struct nvbios_pll pll;
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int N1, M1, N2, M2;
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int log2P, ret;
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ret = nvbios_pll_parse(bios, 0x04, &pll);
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if (ret) {
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nvkm_error(subdev, "mclk pll data not found\n");
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return ret;
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}
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ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P);
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if (ret < 0)
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return ret;
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ram->ctrl = 0x80000000 | (log2P << 16);
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ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20;
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if (N2 == M2) {
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ram->ctrl |= 0x00000100;
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ram->coef = (N1 << 8) | M1;
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} else {
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ram->ctrl |= 0x40000000;
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ram->coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
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}
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return 0;
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}
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static int
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nv40_ram_prog(struct nvkm_ram *base)
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{
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struct nv40_ram *ram = nv40_ram(base);
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struct nvkm_subdev *subdev = &ram->base.fb->subdev;
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struct nvkm_device *device = subdev->device;
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struct nvkm_bios *bios = device->bios;
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struct bit_entry M;
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u32 crtc_mask = 0;
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u8 sr1[2];
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int i;
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/* determine which CRTCs are active, fetch VGA_SR1 for each */
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for (i = 0; i < 2; i++) {
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u32 vbl = nvkm_rd32(device, 0x600808 + (i * 0x2000));
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u32 cnt = 0;
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do {
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if (vbl != nvkm_rd32(device, 0x600808 + (i * 0x2000))) {
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nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);
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sr1[i] = nvkm_rd08(device, 0x0c03c5 + (i * 0x2000));
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if (!(sr1[i] & 0x20))
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crtc_mask |= (1 << i);
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break;
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}
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udelay(1);
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} while (cnt++ < 32);
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}
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/* wait for vblank start on active crtcs, disable memory access */
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for (i = 0; i < 2; i++) {
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if (!(crtc_mask & (1 << i)))
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continue;
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nvkm_msec(device, 2000,
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u32 tmp = nvkm_rd32(device, 0x600808 + (i * 0x2000));
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if (!(tmp & 0x00010000))
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break;
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);
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nvkm_msec(device, 2000,
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u32 tmp = nvkm_rd32(device, 0x600808 + (i * 0x2000));
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if ( (tmp & 0x00010000))
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break;
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);
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nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);
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nvkm_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20);
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}
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/* prepare ram for reclocking */
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nvkm_wr32(device, 0x1002d4, 0x00000001); /* precharge */
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nvkm_wr32(device, 0x1002d0, 0x00000001); /* refresh */
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nvkm_wr32(device, 0x1002d0, 0x00000001); /* refresh */
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nvkm_mask(device, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */
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nvkm_wr32(device, 0x1002dc, 0x00000001); /* enable self-refresh */
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/* change the PLL of each memory partition */
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nvkm_mask(device, 0x00c040, 0x0000c000, 0x00000000);
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switch (device->chipset) {
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case 0x40:
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case 0x45:
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case 0x41:
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case 0x42:
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case 0x47:
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nvkm_mask(device, 0x004044, 0xc0771100, ram->ctrl);
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nvkm_mask(device, 0x00402c, 0xc0771100, ram->ctrl);
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nvkm_wr32(device, 0x004048, ram->coef);
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nvkm_wr32(device, 0x004030, ram->coef);
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fallthrough;
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case 0x43:
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case 0x49:
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case 0x4b:
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nvkm_mask(device, 0x004038, 0xc0771100, ram->ctrl);
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nvkm_wr32(device, 0x00403c, ram->coef);
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fallthrough;
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default:
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nvkm_mask(device, 0x004020, 0xc0771100, ram->ctrl);
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nvkm_wr32(device, 0x004024, ram->coef);
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break;
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}
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udelay(100);
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nvkm_mask(device, 0x00c040, 0x0000c000, 0x0000c000);
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/* re-enable normal operation of memory controller */
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nvkm_wr32(device, 0x1002dc, 0x00000000);
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nvkm_mask(device, 0x100210, 0x80000000, 0x80000000);
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udelay(100);
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/* execute memory reset script from vbios */
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if (!bit_entry(bios, 'M', &M))
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nvbios_init(subdev, nvbios_rd16(bios, M.offset + 0x00));
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/* make sure we're in vblank (hopefully the same one as before), and
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* then re-enable crtc memory access
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*/
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for (i = 0; i < 2; i++) {
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if (!(crtc_mask & (1 << i)))
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continue;
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nvkm_msec(device, 2000,
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u32 tmp = nvkm_rd32(device, 0x600808 + (i * 0x2000));
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if ( (tmp & 0x00010000))
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break;
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);
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nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);
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nvkm_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i]);
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}
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return 0;
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}
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static void
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nv40_ram_tidy(struct nvkm_ram *base)
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{
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}
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static const struct nvkm_ram_func
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nv40_ram_func = {
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.calc = nv40_ram_calc,
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.prog = nv40_ram_prog,
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.tidy = nv40_ram_tidy,
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};
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int
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nv40_ram_new_(struct nvkm_fb *fb, enum nvkm_ram_type type, u64 size,
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struct nvkm_ram **pram)
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{
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struct nv40_ram *ram;
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if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL)))
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return -ENOMEM;
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*pram = &ram->base;
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return nvkm_ram_ctor(&nv40_ram_func, fb, type, size, &ram->base);
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}
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int
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nv40_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram)
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{
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struct nvkm_device *device = fb->subdev.device;
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u32 pbus1218 = nvkm_rd32(device, 0x001218);
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u32 size = nvkm_rd32(device, 0x10020c) & 0xff000000;
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enum nvkm_ram_type type = NVKM_RAM_TYPE_UNKNOWN;
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int ret;
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switch (pbus1218 & 0x00000300) {
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case 0x00000000: type = NVKM_RAM_TYPE_SDRAM; break;
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case 0x00000100: type = NVKM_RAM_TYPE_DDR1 ; break;
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case 0x00000200: type = NVKM_RAM_TYPE_GDDR3; break;
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case 0x00000300: type = NVKM_RAM_TYPE_DDR2 ; break;
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}
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ret = nv40_ram_new_(fb, type, size, pram);
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if (ret)
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return ret;
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(*pram)->parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1;
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return 0;
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}
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