821 lines
22 KiB
C
821 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics SA 2014
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* Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
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*/
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/io.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/seq_file.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_debugfs.h>
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#include <drm/drm_device.h>
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#include <drm/drm_file.h>
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#include <drm/drm_print.h>
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#include <drm/drm_probe_helper.h>
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/* HDformatter registers */
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#define HDA_ANA_CFG 0x0000
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#define HDA_ANA_SCALE_CTRL_Y 0x0004
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#define HDA_ANA_SCALE_CTRL_CB 0x0008
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#define HDA_ANA_SCALE_CTRL_CR 0x000C
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#define HDA_ANA_ANC_CTRL 0x0010
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#define HDA_ANA_SRC_Y_CFG 0x0014
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#define HDA_COEFF_Y_PH1_TAP123 0x0018
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#define HDA_COEFF_Y_PH1_TAP456 0x001C
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#define HDA_COEFF_Y_PH2_TAP123 0x0020
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#define HDA_COEFF_Y_PH2_TAP456 0x0024
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#define HDA_COEFF_Y_PH3_TAP123 0x0028
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#define HDA_COEFF_Y_PH3_TAP456 0x002C
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#define HDA_COEFF_Y_PH4_TAP123 0x0030
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#define HDA_COEFF_Y_PH4_TAP456 0x0034
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#define HDA_ANA_SRC_C_CFG 0x0040
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#define HDA_COEFF_C_PH1_TAP123 0x0044
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#define HDA_COEFF_C_PH1_TAP456 0x0048
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#define HDA_COEFF_C_PH2_TAP123 0x004C
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#define HDA_COEFF_C_PH2_TAP456 0x0050
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#define HDA_COEFF_C_PH3_TAP123 0x0054
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#define HDA_COEFF_C_PH3_TAP456 0x0058
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#define HDA_COEFF_C_PH4_TAP123 0x005C
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#define HDA_COEFF_C_PH4_TAP456 0x0060
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#define HDA_SYNC_AWGI 0x0300
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/* HDA_ANA_CFG */
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#define CFG_AWG_ASYNC_EN BIT(0)
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#define CFG_AWG_ASYNC_HSYNC_MTD BIT(1)
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#define CFG_AWG_ASYNC_VSYNC_MTD BIT(2)
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#define CFG_AWG_SYNC_DEL BIT(3)
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#define CFG_AWG_FLTR_MODE_SHIFT 4
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#define CFG_AWG_FLTR_MODE_MASK (0xF << CFG_AWG_FLTR_MODE_SHIFT)
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#define CFG_AWG_FLTR_MODE_SD (0 << CFG_AWG_FLTR_MODE_SHIFT)
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#define CFG_AWG_FLTR_MODE_ED (1 << CFG_AWG_FLTR_MODE_SHIFT)
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#define CFG_AWG_FLTR_MODE_HD (2 << CFG_AWG_FLTR_MODE_SHIFT)
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#define CFG_SYNC_ON_PBPR_MASK BIT(8)
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#define CFG_PREFILTER_EN_MASK BIT(9)
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#define CFG_PBPR_SYNC_OFF_SHIFT 16
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#define CFG_PBPR_SYNC_OFF_MASK (0x7FF << CFG_PBPR_SYNC_OFF_SHIFT)
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#define CFG_PBPR_SYNC_OFF_VAL 0x117 /* Voltage dependent. stiH416 */
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/* Default scaling values */
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#define SCALE_CTRL_Y_DFLT 0x00C50256
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#define SCALE_CTRL_CB_DFLT 0x00DB0249
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#define SCALE_CTRL_CR_DFLT 0x00DB0249
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/* Video DACs control */
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#define DAC_CFG_HD_HZUVW_OFF_MASK BIT(1)
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/* Upsampler values for the alternative 2X Filter */
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#define SAMPLER_COEF_NB 8
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#define HDA_ANA_SRC_Y_CFG_ALT_2X 0x01130000
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static u32 coef_y_alt_2x[] = {
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0x00FE83FB, 0x1F900401, 0x00000000, 0x00000000,
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0x00F408F9, 0x055F7C25, 0x00000000, 0x00000000
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};
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#define HDA_ANA_SRC_C_CFG_ALT_2X 0x01750004
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static u32 coef_c_alt_2x[] = {
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0x001305F7, 0x05274BD0, 0x00000000, 0x00000000,
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0x0004907C, 0x09C80B9D, 0x00000000, 0x00000000
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};
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/* Upsampler values for the 4X Filter */
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#define HDA_ANA_SRC_Y_CFG_4X 0x01ED0005
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#define HDA_ANA_SRC_C_CFG_4X 0x01ED0004
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static u32 coef_yc_4x[] = {
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0x00FC827F, 0x008FE20B, 0x00F684FC, 0x050F7C24,
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0x00F4857C, 0x0A1F402E, 0x00FA027F, 0x0E076E1D
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};
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/* AWG instructions for some video modes */
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#define AWG_MAX_INST 64
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/* 720p@50 */
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static u32 AWGi_720p_50[] = {
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0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA,
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0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B,
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0x00000D8E, 0x00000104, 0x00001804, 0x00000971,
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0x00000C26, 0x0000003B, 0x00000FB4, 0x00000FB5,
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0x00000104, 0x00001AE8
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};
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#define NN_720p_50 ARRAY_SIZE(AWGi_720p_50)
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/* 720p@60 */
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static u32 AWGi_720p_60[] = {
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0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA,
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0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B,
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0x00000C44, 0x00000104, 0x00001804, 0x00000971,
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0x00000C26, 0x0000003B, 0x00000F0F, 0x00000F10,
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0x00000104, 0x00001AE8
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};
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#define NN_720p_60 ARRAY_SIZE(AWGi_720p_60)
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/* 1080p@30 */
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static u32 AWGi_1080p_30[] = {
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0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
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0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
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0x00000C2A, 0x00000104, 0x00001804, 0x00000971,
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0x00000C2A, 0x0000003B, 0x00000EBE, 0x00000EBF,
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0x00000EBF, 0x00000104, 0x00001A2F, 0x00001C4B,
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0x00001C52
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};
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#define NN_1080p_30 ARRAY_SIZE(AWGi_1080p_30)
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/* 1080p@25 */
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static u32 AWGi_1080p_25[] = {
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0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
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0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
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0x00000DE2, 0x00000104, 0x00001804, 0x00000971,
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0x00000C2A, 0x0000003B, 0x00000F51, 0x00000F51,
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0x00000F52, 0x00000104, 0x00001A2F, 0x00001C4B,
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0x00001C52
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};
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#define NN_1080p_25 ARRAY_SIZE(AWGi_1080p_25)
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/* 1080p@24 */
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static u32 AWGi_1080p_24[] = {
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0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
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0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
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0x00000E50, 0x00000104, 0x00001804, 0x00000971,
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0x00000C2A, 0x0000003B, 0x00000F76, 0x00000F76,
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0x00000F76, 0x00000104, 0x00001A2F, 0x00001C4B,
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0x00001C52
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};
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#define NN_1080p_24 ARRAY_SIZE(AWGi_1080p_24)
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/* 720x480p@60 */
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static u32 AWGi_720x480p_60[] = {
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0x00000904, 0x00000F18, 0x0000013B, 0x00001805,
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0x00000904, 0x00000C3D, 0x0000003B, 0x00001A06
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};
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#define NN_720x480p_60 ARRAY_SIZE(AWGi_720x480p_60)
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/* Video mode category */
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enum sti_hda_vid_cat {
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VID_SD,
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VID_ED,
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VID_HD_74M,
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VID_HD_148M
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};
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struct sti_hda_video_config {
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struct drm_display_mode mode;
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u32 *awg_instr;
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int nb_instr;
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enum sti_hda_vid_cat vid_cat;
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};
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/* HD analog supported modes
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* Interlaced modes may be added when supported by the whole display chain
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*/
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static const struct sti_hda_video_config hda_supported_modes[] = {
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/* 1080p30 74.250Mhz */
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{{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
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2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
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DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
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AWGi_1080p_30, NN_1080p_30, VID_HD_74M},
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/* 1080p30 74.176Mhz */
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{{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74176, 1920, 2008,
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2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
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DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
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AWGi_1080p_30, NN_1080p_30, VID_HD_74M},
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/* 1080p24 74.250Mhz */
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{{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
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2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
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DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
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AWGi_1080p_24, NN_1080p_24, VID_HD_74M},
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/* 1080p24 74.176Mhz */
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{{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74176, 1920, 2558,
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2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
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DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
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AWGi_1080p_24, NN_1080p_24, VID_HD_74M},
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/* 1080p25 74.250Mhz */
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{{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
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2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
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DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
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AWGi_1080p_25, NN_1080p_25, VID_HD_74M},
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/* 720p60 74.250Mhz */
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{{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
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1430, 1650, 0, 720, 725, 730, 750, 0,
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DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
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AWGi_720p_60, NN_720p_60, VID_HD_74M},
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/* 720p60 74.176Mhz */
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{{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74176, 1280, 1390,
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1430, 1650, 0, 720, 725, 730, 750, 0,
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DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
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AWGi_720p_60, NN_720p_60, VID_HD_74M},
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/* 720p50 74.250Mhz */
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{{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
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1760, 1980, 0, 720, 725, 730, 750, 0,
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DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
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AWGi_720p_50, NN_720p_50, VID_HD_74M},
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/* 720x480p60 27.027Mhz */
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{{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27027, 720, 736,
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798, 858, 0, 480, 489, 495, 525, 0,
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DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)},
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AWGi_720x480p_60, NN_720x480p_60, VID_ED},
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/* 720x480p60 27.000Mhz */
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{{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
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798, 858, 0, 480, 489, 495, 525, 0,
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DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)},
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AWGi_720x480p_60, NN_720x480p_60, VID_ED}
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};
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/*
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* STI hd analog structure
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*
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* @dev: driver device
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* @drm_dev: pointer to drm device
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* @mode: current display mode selected
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* @regs: HD analog register
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* @video_dacs_ctrl: video DACS control register
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* @enabled: true if HD analog is enabled else false
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*/
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struct sti_hda {
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struct device dev;
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struct drm_device *drm_dev;
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struct drm_display_mode mode;
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void __iomem *regs;
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void __iomem *video_dacs_ctrl;
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struct clk *clk_pix;
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struct clk *clk_hddac;
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bool enabled;
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};
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struct sti_hda_connector {
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struct drm_connector drm_connector;
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struct drm_encoder *encoder;
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struct sti_hda *hda;
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};
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#define to_sti_hda_connector(x) \
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container_of(x, struct sti_hda_connector, drm_connector)
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static u32 hda_read(struct sti_hda *hda, int offset)
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{
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return readl(hda->regs + offset);
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}
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static void hda_write(struct sti_hda *hda, u32 val, int offset)
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{
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writel(val, hda->regs + offset);
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}
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/**
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* hda_get_mode_idx - Search for a video mode in the supported modes table
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*
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* @mode: mode being searched
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* @idx: index of the found mode
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*
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* Return true if mode is found
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*/
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static bool hda_get_mode_idx(struct drm_display_mode mode, int *idx)
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{
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++)
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if (drm_mode_equal(&hda_supported_modes[i].mode, &mode)) {
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*idx = i;
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return true;
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}
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return false;
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}
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/**
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* hda_enable_hd_dacs - Enable the HD DACS
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*
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* @hda: pointer to HD analog structure
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* @enable: true if HD DACS need to be enabled, else false
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*/
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static void hda_enable_hd_dacs(struct sti_hda *hda, bool enable)
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{
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if (hda->video_dacs_ctrl) {
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u32 val;
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val = readl(hda->video_dacs_ctrl);
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if (enable)
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val &= ~DAC_CFG_HD_HZUVW_OFF_MASK;
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else
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val |= DAC_CFG_HD_HZUVW_OFF_MASK;
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writel(val, hda->video_dacs_ctrl);
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}
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}
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#define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \
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readl(hda->regs + reg))
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static void hda_dbg_cfg(struct seq_file *s, int val)
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{
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seq_puts(s, "\tAWG ");
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seq_puts(s, val & CFG_AWG_ASYNC_EN ? "enabled" : "disabled");
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}
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static void hda_dbg_awg_microcode(struct seq_file *s, void __iomem *reg)
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{
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unsigned int i;
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seq_puts(s, "\n\n HDA AWG microcode:");
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for (i = 0; i < AWG_MAX_INST; i++) {
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if (i % 8 == 0)
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seq_printf(s, "\n %04X:", i);
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seq_printf(s, " %04X", readl(reg + i * 4));
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}
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}
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static void hda_dbg_video_dacs_ctrl(struct seq_file *s, void __iomem *reg)
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{
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u32 val = readl(reg);
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seq_printf(s, "\n\n %-25s 0x%08X", "VIDEO_DACS_CONTROL", val);
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seq_puts(s, "\tHD DACs ");
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seq_puts(s, val & DAC_CFG_HD_HZUVW_OFF_MASK ? "disabled" : "enabled");
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}
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static int hda_dbg_show(struct seq_file *s, void *data)
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{
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struct drm_info_node *node = s->private;
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struct sti_hda *hda = (struct sti_hda *)node->info_ent->data;
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seq_printf(s, "HD Analog: (vaddr = 0x%p)", hda->regs);
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DBGFS_DUMP(HDA_ANA_CFG);
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hda_dbg_cfg(s, readl(hda->regs + HDA_ANA_CFG));
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DBGFS_DUMP(HDA_ANA_SCALE_CTRL_Y);
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DBGFS_DUMP(HDA_ANA_SCALE_CTRL_CB);
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DBGFS_DUMP(HDA_ANA_SCALE_CTRL_CR);
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DBGFS_DUMP(HDA_ANA_ANC_CTRL);
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DBGFS_DUMP(HDA_ANA_SRC_Y_CFG);
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DBGFS_DUMP(HDA_ANA_SRC_C_CFG);
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hda_dbg_awg_microcode(s, hda->regs + HDA_SYNC_AWGI);
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if (hda->video_dacs_ctrl)
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hda_dbg_video_dacs_ctrl(s, hda->video_dacs_ctrl);
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seq_putc(s, '\n');
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return 0;
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}
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static struct drm_info_list hda_debugfs_files[] = {
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{ "hda", hda_dbg_show, 0, NULL },
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};
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static void hda_debugfs_init(struct sti_hda *hda, struct drm_minor *minor)
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{
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(hda_debugfs_files); i++)
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hda_debugfs_files[i].data = hda;
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drm_debugfs_create_files(hda_debugfs_files,
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ARRAY_SIZE(hda_debugfs_files),
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minor->debugfs_root, minor);
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}
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/**
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* sti_hda_configure_awg - Configure AWG, writing instructions
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*
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* @hda: pointer to HD analog structure
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* @awg_instr: pointer to AWG instructions table
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* @nb: nb of AWG instructions
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*/
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static void sti_hda_configure_awg(struct sti_hda *hda, u32 *awg_instr, int nb)
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{
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unsigned int i;
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DRM_DEBUG_DRIVER("\n");
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for (i = 0; i < nb; i++)
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hda_write(hda, awg_instr[i], HDA_SYNC_AWGI + i * 4);
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for (i = nb; i < AWG_MAX_INST; i++)
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hda_write(hda, 0, HDA_SYNC_AWGI + i * 4);
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}
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static void sti_hda_disable(struct drm_bridge *bridge)
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{
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struct sti_hda *hda = bridge->driver_private;
|
|
u32 val;
|
|
|
|
if (!hda->enabled)
|
|
return;
|
|
|
|
DRM_DEBUG_DRIVER("\n");
|
|
|
|
/* Disable HD DAC and AWG */
|
|
val = hda_read(hda, HDA_ANA_CFG);
|
|
val &= ~CFG_AWG_ASYNC_EN;
|
|
hda_write(hda, val, HDA_ANA_CFG);
|
|
hda_write(hda, 0, HDA_ANA_ANC_CTRL);
|
|
|
|
hda_enable_hd_dacs(hda, false);
|
|
|
|
/* Disable/unprepare hda clock */
|
|
clk_disable_unprepare(hda->clk_hddac);
|
|
clk_disable_unprepare(hda->clk_pix);
|
|
|
|
hda->enabled = false;
|
|
}
|
|
|
|
static void sti_hda_pre_enable(struct drm_bridge *bridge)
|
|
{
|
|
struct sti_hda *hda = bridge->driver_private;
|
|
u32 val, i, mode_idx;
|
|
u32 src_filter_y, src_filter_c;
|
|
u32 *coef_y, *coef_c;
|
|
u32 filter_mode;
|
|
|
|
DRM_DEBUG_DRIVER("\n");
|
|
|
|
if (hda->enabled)
|
|
return;
|
|
|
|
/* Prepare/enable clocks */
|
|
if (clk_prepare_enable(hda->clk_pix))
|
|
DRM_ERROR("Failed to prepare/enable hda_pix clk\n");
|
|
if (clk_prepare_enable(hda->clk_hddac))
|
|
DRM_ERROR("Failed to prepare/enable hda_hddac clk\n");
|
|
|
|
if (!hda_get_mode_idx(hda->mode, &mode_idx)) {
|
|
DRM_ERROR("Undefined mode\n");
|
|
return;
|
|
}
|
|
|
|
switch (hda_supported_modes[mode_idx].vid_cat) {
|
|
case VID_HD_148M:
|
|
DRM_ERROR("Beyond HD analog capabilities\n");
|
|
return;
|
|
case VID_HD_74M:
|
|
/* HD use alternate 2x filter */
|
|
filter_mode = CFG_AWG_FLTR_MODE_HD;
|
|
src_filter_y = HDA_ANA_SRC_Y_CFG_ALT_2X;
|
|
src_filter_c = HDA_ANA_SRC_C_CFG_ALT_2X;
|
|
coef_y = coef_y_alt_2x;
|
|
coef_c = coef_c_alt_2x;
|
|
break;
|
|
case VID_ED:
|
|
/* ED uses 4x filter */
|
|
filter_mode = CFG_AWG_FLTR_MODE_ED;
|
|
src_filter_y = HDA_ANA_SRC_Y_CFG_4X;
|
|
src_filter_c = HDA_ANA_SRC_C_CFG_4X;
|
|
coef_y = coef_yc_4x;
|
|
coef_c = coef_yc_4x;
|
|
break;
|
|
case VID_SD:
|
|
DRM_ERROR("Not supported\n");
|
|
return;
|
|
default:
|
|
DRM_ERROR("Undefined resolution\n");
|
|
return;
|
|
}
|
|
DRM_DEBUG_DRIVER("Using HDA mode #%d\n", mode_idx);
|
|
|
|
/* Enable HD Video DACs */
|
|
hda_enable_hd_dacs(hda, true);
|
|
|
|
/* Configure scaler */
|
|
hda_write(hda, SCALE_CTRL_Y_DFLT, HDA_ANA_SCALE_CTRL_Y);
|
|
hda_write(hda, SCALE_CTRL_CB_DFLT, HDA_ANA_SCALE_CTRL_CB);
|
|
hda_write(hda, SCALE_CTRL_CR_DFLT, HDA_ANA_SCALE_CTRL_CR);
|
|
|
|
/* Configure sampler */
|
|
hda_write(hda , src_filter_y, HDA_ANA_SRC_Y_CFG);
|
|
hda_write(hda, src_filter_c, HDA_ANA_SRC_C_CFG);
|
|
for (i = 0; i < SAMPLER_COEF_NB; i++) {
|
|
hda_write(hda, coef_y[i], HDA_COEFF_Y_PH1_TAP123 + i * 4);
|
|
hda_write(hda, coef_c[i], HDA_COEFF_C_PH1_TAP123 + i * 4);
|
|
}
|
|
|
|
/* Configure main HDFormatter */
|
|
val = 0;
|
|
val |= (hda->mode.flags & DRM_MODE_FLAG_INTERLACE) ?
|
|
0 : CFG_AWG_ASYNC_VSYNC_MTD;
|
|
val |= (CFG_PBPR_SYNC_OFF_VAL << CFG_PBPR_SYNC_OFF_SHIFT);
|
|
val |= filter_mode;
|
|
hda_write(hda, val, HDA_ANA_CFG);
|
|
|
|
/* Configure AWG */
|
|
sti_hda_configure_awg(hda, hda_supported_modes[mode_idx].awg_instr,
|
|
hda_supported_modes[mode_idx].nb_instr);
|
|
|
|
/* Enable AWG */
|
|
val = hda_read(hda, HDA_ANA_CFG);
|
|
val |= CFG_AWG_ASYNC_EN;
|
|
hda_write(hda, val, HDA_ANA_CFG);
|
|
|
|
hda->enabled = true;
|
|
}
|
|
|
|
static void sti_hda_set_mode(struct drm_bridge *bridge,
|
|
const struct drm_display_mode *mode,
|
|
const struct drm_display_mode *adjusted_mode)
|
|
{
|
|
struct sti_hda *hda = bridge->driver_private;
|
|
u32 mode_idx;
|
|
int hddac_rate;
|
|
int ret;
|
|
|
|
DRM_DEBUG_DRIVER("\n");
|
|
|
|
drm_mode_copy(&hda->mode, mode);
|
|
|
|
if (!hda_get_mode_idx(hda->mode, &mode_idx)) {
|
|
DRM_ERROR("Undefined mode\n");
|
|
return;
|
|
}
|
|
|
|
switch (hda_supported_modes[mode_idx].vid_cat) {
|
|
case VID_HD_74M:
|
|
/* HD use alternate 2x filter */
|
|
hddac_rate = mode->clock * 1000 * 2;
|
|
break;
|
|
case VID_ED:
|
|
/* ED uses 4x filter */
|
|
hddac_rate = mode->clock * 1000 * 4;
|
|
break;
|
|
default:
|
|
DRM_ERROR("Undefined mode\n");
|
|
return;
|
|
}
|
|
|
|
/* HD DAC = 148.5Mhz or 108 Mhz */
|
|
ret = clk_set_rate(hda->clk_hddac, hddac_rate);
|
|
if (ret < 0)
|
|
DRM_ERROR("Cannot set rate (%dHz) for hda_hddac clk\n",
|
|
hddac_rate);
|
|
|
|
/* HDformatter clock = compositor clock */
|
|
ret = clk_set_rate(hda->clk_pix, mode->clock * 1000);
|
|
if (ret < 0)
|
|
DRM_ERROR("Cannot set rate (%dHz) for hda_pix clk\n",
|
|
mode->clock * 1000);
|
|
}
|
|
|
|
static void sti_hda_bridge_nope(struct drm_bridge *bridge)
|
|
{
|
|
/* do nothing */
|
|
}
|
|
|
|
static const struct drm_bridge_funcs sti_hda_bridge_funcs = {
|
|
.pre_enable = sti_hda_pre_enable,
|
|
.enable = sti_hda_bridge_nope,
|
|
.disable = sti_hda_disable,
|
|
.post_disable = sti_hda_bridge_nope,
|
|
.mode_set = sti_hda_set_mode,
|
|
};
|
|
|
|
static int sti_hda_connector_get_modes(struct drm_connector *connector)
|
|
{
|
|
unsigned int i;
|
|
int count = 0;
|
|
struct sti_hda_connector *hda_connector
|
|
= to_sti_hda_connector(connector);
|
|
struct sti_hda *hda = hda_connector->hda;
|
|
|
|
DRM_DEBUG_DRIVER("\n");
|
|
|
|
for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++) {
|
|
struct drm_display_mode *mode =
|
|
drm_mode_duplicate(hda->drm_dev,
|
|
&hda_supported_modes[i].mode);
|
|
if (!mode)
|
|
continue;
|
|
|
|
/* the first mode is the preferred mode */
|
|
if (i == 0)
|
|
mode->type |= DRM_MODE_TYPE_PREFERRED;
|
|
|
|
drm_mode_probed_add(connector, mode);
|
|
count++;
|
|
}
|
|
|
|
return count;
|
|
}
|
|
|
|
#define CLK_TOLERANCE_HZ 50
|
|
|
|
static enum drm_mode_status
|
|
sti_hda_connector_mode_valid(struct drm_connector *connector,
|
|
struct drm_display_mode *mode)
|
|
{
|
|
int target = mode->clock * 1000;
|
|
int target_min = target - CLK_TOLERANCE_HZ;
|
|
int target_max = target + CLK_TOLERANCE_HZ;
|
|
int result;
|
|
int idx;
|
|
struct sti_hda_connector *hda_connector
|
|
= to_sti_hda_connector(connector);
|
|
struct sti_hda *hda = hda_connector->hda;
|
|
|
|
if (!hda_get_mode_idx(*mode, &idx)) {
|
|
return MODE_BAD;
|
|
} else {
|
|
result = clk_round_rate(hda->clk_pix, target);
|
|
|
|
DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
|
|
target, result);
|
|
|
|
if ((result < target_min) || (result > target_max)) {
|
|
DRM_DEBUG_DRIVER("hda pixclk=%d not supported\n",
|
|
target);
|
|
return MODE_BAD;
|
|
}
|
|
}
|
|
|
|
return MODE_OK;
|
|
}
|
|
|
|
static const
|
|
struct drm_connector_helper_funcs sti_hda_connector_helper_funcs = {
|
|
.get_modes = sti_hda_connector_get_modes,
|
|
.mode_valid = sti_hda_connector_mode_valid,
|
|
};
|
|
|
|
static int sti_hda_late_register(struct drm_connector *connector)
|
|
{
|
|
struct sti_hda_connector *hda_connector
|
|
= to_sti_hda_connector(connector);
|
|
struct sti_hda *hda = hda_connector->hda;
|
|
|
|
hda_debugfs_init(hda, hda->drm_dev->primary);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct drm_connector_funcs sti_hda_connector_funcs = {
|
|
.fill_modes = drm_helper_probe_single_connector_modes,
|
|
.destroy = drm_connector_cleanup,
|
|
.reset = drm_atomic_helper_connector_reset,
|
|
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
|
|
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
|
|
.late_register = sti_hda_late_register,
|
|
};
|
|
|
|
static struct drm_encoder *sti_hda_find_encoder(struct drm_device *dev)
|
|
{
|
|
struct drm_encoder *encoder;
|
|
|
|
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
|
|
if (encoder->encoder_type == DRM_MODE_ENCODER_DAC)
|
|
return encoder;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static int sti_hda_bind(struct device *dev, struct device *master, void *data)
|
|
{
|
|
struct sti_hda *hda = dev_get_drvdata(dev);
|
|
struct drm_device *drm_dev = data;
|
|
struct drm_encoder *encoder;
|
|
struct sti_hda_connector *connector;
|
|
struct drm_connector *drm_connector;
|
|
struct drm_bridge *bridge;
|
|
int err;
|
|
|
|
/* Set the drm device handle */
|
|
hda->drm_dev = drm_dev;
|
|
|
|
encoder = sti_hda_find_encoder(drm_dev);
|
|
if (!encoder)
|
|
return -ENOMEM;
|
|
|
|
connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL);
|
|
if (!connector)
|
|
return -ENOMEM;
|
|
|
|
connector->hda = hda;
|
|
|
|
bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
|
|
if (!bridge)
|
|
return -ENOMEM;
|
|
|
|
bridge->driver_private = hda;
|
|
bridge->funcs = &sti_hda_bridge_funcs;
|
|
drm_bridge_attach(encoder, bridge, NULL, 0);
|
|
|
|
connector->encoder = encoder;
|
|
|
|
drm_connector = (struct drm_connector *)connector;
|
|
|
|
drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
|
|
|
|
drm_connector_init(drm_dev, drm_connector,
|
|
&sti_hda_connector_funcs, DRM_MODE_CONNECTOR_Component);
|
|
drm_connector_helper_add(drm_connector,
|
|
&sti_hda_connector_helper_funcs);
|
|
|
|
err = drm_connector_attach_encoder(drm_connector, encoder);
|
|
if (err) {
|
|
DRM_ERROR("Failed to attach a connector to a encoder\n");
|
|
goto err_sysfs;
|
|
}
|
|
|
|
/* force to disable hd dacs at startup */
|
|
hda_enable_hd_dacs(hda, false);
|
|
|
|
return 0;
|
|
|
|
err_sysfs:
|
|
return -EINVAL;
|
|
}
|
|
|
|
static void sti_hda_unbind(struct device *dev,
|
|
struct device *master, void *data)
|
|
{
|
|
}
|
|
|
|
static const struct component_ops sti_hda_ops = {
|
|
.bind = sti_hda_bind,
|
|
.unbind = sti_hda_unbind,
|
|
};
|
|
|
|
static int sti_hda_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct sti_hda *hda;
|
|
struct resource *res;
|
|
|
|
DRM_INFO("%s\n", __func__);
|
|
|
|
hda = devm_kzalloc(dev, sizeof(*hda), GFP_KERNEL);
|
|
if (!hda)
|
|
return -ENOMEM;
|
|
|
|
hda->dev = pdev->dev;
|
|
|
|
/* Get resources */
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hda-reg");
|
|
if (!res) {
|
|
DRM_ERROR("Invalid hda resource\n");
|
|
return -ENOMEM;
|
|
}
|
|
hda->regs = devm_ioremap(dev, res->start, resource_size(res));
|
|
if (!hda->regs)
|
|
return -ENOMEM;
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
|
"video-dacs-ctrl");
|
|
if (res) {
|
|
hda->video_dacs_ctrl = devm_ioremap(dev, res->start,
|
|
resource_size(res));
|
|
if (!hda->video_dacs_ctrl)
|
|
return -ENOMEM;
|
|
} else {
|
|
/* If no existing video-dacs-ctrl resource continue the probe */
|
|
DRM_DEBUG_DRIVER("No video-dacs-ctrl resource\n");
|
|
hda->video_dacs_ctrl = NULL;
|
|
}
|
|
|
|
/* Get clock resources */
|
|
hda->clk_pix = devm_clk_get(dev, "pix");
|
|
if (IS_ERR(hda->clk_pix)) {
|
|
DRM_ERROR("Cannot get hda_pix clock\n");
|
|
return PTR_ERR(hda->clk_pix);
|
|
}
|
|
|
|
hda->clk_hddac = devm_clk_get(dev, "hddac");
|
|
if (IS_ERR(hda->clk_hddac)) {
|
|
DRM_ERROR("Cannot get hda_hddac clock\n");
|
|
return PTR_ERR(hda->clk_hddac);
|
|
}
|
|
|
|
platform_set_drvdata(pdev, hda);
|
|
|
|
return component_add(&pdev->dev, &sti_hda_ops);
|
|
}
|
|
|
|
static int sti_hda_remove(struct platform_device *pdev)
|
|
{
|
|
component_del(&pdev->dev, &sti_hda_ops);
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id hda_of_match[] = {
|
|
{ .compatible = "st,stih416-hda", },
|
|
{ .compatible = "st,stih407-hda", },
|
|
{ /* end node */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, hda_of_match);
|
|
|
|
struct platform_driver sti_hda_driver = {
|
|
.driver = {
|
|
.name = "sti-hda",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = hda_of_match,
|
|
},
|
|
.probe = sti_hda_probe,
|
|
.remove = sti_hda_remove,
|
|
};
|
|
|
|
MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
|
|
MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
|
|
MODULE_LICENSE("GPL");
|