443 lines
12 KiB
C
443 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics SA 2014
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* Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
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* Fabien Dessenne <fabien.dessenne@st.com>
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* Vincent Abriou <vincent.abriou@st.com>
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* for STMicroelectronics.
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*/
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/notifier.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <drm/drm_modes.h>
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#include <drm/drm_print.h>
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#include "sti_drv.h"
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#include "sti_vtg.h"
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#define VTG_MODE_MASTER 0
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/* registers offset */
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#define VTG_MODE 0x0000
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#define VTG_CLKLN 0x0008
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#define VTG_HLFLN 0x000C
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#define VTG_DRST_AUTOC 0x0010
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#define VTG_VID_TFO 0x0040
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#define VTG_VID_TFS 0x0044
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#define VTG_VID_BFO 0x0048
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#define VTG_VID_BFS 0x004C
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#define VTG_HOST_ITS 0x0078
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#define VTG_HOST_ITS_BCLR 0x007C
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#define VTG_HOST_ITM_BCLR 0x0088
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#define VTG_HOST_ITM_BSET 0x008C
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#define VTG_H_HD_1 0x00C0
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#define VTG_TOP_V_VD_1 0x00C4
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#define VTG_BOT_V_VD_1 0x00C8
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#define VTG_TOP_V_HD_1 0x00CC
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#define VTG_BOT_V_HD_1 0x00D0
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#define VTG_H_HD_2 0x00E0
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#define VTG_TOP_V_VD_2 0x00E4
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#define VTG_BOT_V_VD_2 0x00E8
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#define VTG_TOP_V_HD_2 0x00EC
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#define VTG_BOT_V_HD_2 0x00F0
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#define VTG_H_HD_3 0x0100
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#define VTG_TOP_V_VD_3 0x0104
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#define VTG_BOT_V_VD_3 0x0108
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#define VTG_TOP_V_HD_3 0x010C
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#define VTG_BOT_V_HD_3 0x0110
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#define VTG_H_HD_4 0x0120
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#define VTG_TOP_V_VD_4 0x0124
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#define VTG_BOT_V_VD_4 0x0128
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#define VTG_TOP_V_HD_4 0x012c
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#define VTG_BOT_V_HD_4 0x0130
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#define VTG_IRQ_BOTTOM BIT(0)
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#define VTG_IRQ_TOP BIT(1)
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#define VTG_IRQ_MASK (VTG_IRQ_TOP | VTG_IRQ_BOTTOM)
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/* Delay introduced by the HDMI in nb of pixel */
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#define HDMI_DELAY (5)
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/* Delay introduced by the DVO in nb of pixel */
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#define DVO_DELAY (7)
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/* delay introduced by the Arbitrary Waveform Generator in nb of pixels */
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#define AWG_DELAY_HD (-9)
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#define AWG_DELAY_ED (-8)
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#define AWG_DELAY_SD (-7)
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/*
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* STI VTG register offset structure
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*
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*@h_hd: stores the VTG_H_HD_x register offset
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*@top_v_vd: stores the VTG_TOP_V_VD_x register offset
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*@bot_v_vd: stores the VTG_BOT_V_VD_x register offset
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*@top_v_hd: stores the VTG_TOP_V_HD_x register offset
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*@bot_v_hd: stores the VTG_BOT_V_HD_x register offset
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*/
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struct sti_vtg_regs_offs {
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u32 h_hd;
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u32 top_v_vd;
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u32 bot_v_vd;
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u32 top_v_hd;
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u32 bot_v_hd;
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};
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#define VTG_MAX_SYNC_OUTPUT 4
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static const struct sti_vtg_regs_offs vtg_regs_offs[VTG_MAX_SYNC_OUTPUT] = {
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{ VTG_H_HD_1,
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VTG_TOP_V_VD_1, VTG_BOT_V_VD_1, VTG_TOP_V_HD_1, VTG_BOT_V_HD_1 },
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{ VTG_H_HD_2,
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VTG_TOP_V_VD_2, VTG_BOT_V_VD_2, VTG_TOP_V_HD_2, VTG_BOT_V_HD_2 },
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{ VTG_H_HD_3,
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VTG_TOP_V_VD_3, VTG_BOT_V_VD_3, VTG_TOP_V_HD_3, VTG_BOT_V_HD_3 },
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{ VTG_H_HD_4,
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VTG_TOP_V_VD_4, VTG_BOT_V_VD_4, VTG_TOP_V_HD_4, VTG_BOT_V_HD_4 }
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};
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/*
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* STI VTG synchronisation parameters structure
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*
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*@hsync: sample number falling and rising edge
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*@vsync_line_top: vertical top field line number falling and rising edge
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*@vsync_line_bot: vertical bottom field line number falling and rising edge
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*@vsync_off_top: vertical top field sample number rising and falling edge
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*@vsync_off_bot: vertical bottom field sample number rising and falling edge
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*/
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struct sti_vtg_sync_params {
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u32 hsync;
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u32 vsync_line_top;
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u32 vsync_line_bot;
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u32 vsync_off_top;
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u32 vsync_off_bot;
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};
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/*
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* STI VTG structure
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*
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* @regs: register mapping
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* @sync_params: synchronisation parameters used to generate timings
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* @irq: VTG irq
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* @irq_status: store the IRQ status value
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* @notifier_list: notifier callback
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* @crtc: the CRTC for vblank event
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*/
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struct sti_vtg {
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void __iomem *regs;
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struct sti_vtg_sync_params sync_params[VTG_MAX_SYNC_OUTPUT];
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int irq;
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u32 irq_status;
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struct raw_notifier_head notifier_list;
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struct drm_crtc *crtc;
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};
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struct sti_vtg *of_vtg_find(struct device_node *np)
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{
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struct platform_device *pdev;
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pdev = of_find_device_by_node(np);
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if (!pdev)
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return NULL;
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return (struct sti_vtg *)platform_get_drvdata(pdev);
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}
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static void vtg_reset(struct sti_vtg *vtg)
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{
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writel(1, vtg->regs + VTG_DRST_AUTOC);
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}
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static void vtg_set_output_window(void __iomem *regs,
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const struct drm_display_mode *mode)
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{
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u32 video_top_field_start;
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u32 video_top_field_stop;
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u32 video_bottom_field_start;
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u32 video_bottom_field_stop;
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u32 xstart = sti_vtg_get_pixel_number(*mode, 0);
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u32 ystart = sti_vtg_get_line_number(*mode, 0);
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u32 xstop = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
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u32 ystop = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
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/* Set output window to fit the display mode selected */
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video_top_field_start = (ystart << 16) | xstart;
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video_top_field_stop = (ystop << 16) | xstop;
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/* Only progressive supported for now */
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video_bottom_field_start = video_top_field_start;
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video_bottom_field_stop = video_top_field_stop;
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writel(video_top_field_start, regs + VTG_VID_TFO);
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writel(video_top_field_stop, regs + VTG_VID_TFS);
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writel(video_bottom_field_start, regs + VTG_VID_BFO);
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writel(video_bottom_field_stop, regs + VTG_VID_BFS);
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}
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static void vtg_set_hsync_vsync_pos(struct sti_vtg_sync_params *sync,
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int delay,
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const struct drm_display_mode *mode)
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{
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long clocksperline, start, stop;
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u32 risesync_top, fallsync_top;
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u32 risesync_offs_top, fallsync_offs_top;
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clocksperline = mode->htotal;
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/* Get the hsync position */
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start = 0;
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stop = mode->hsync_end - mode->hsync_start;
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start += delay;
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stop += delay;
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if (start < 0)
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start += clocksperline;
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else if (start >= clocksperline)
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start -= clocksperline;
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if (stop < 0)
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stop += clocksperline;
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else if (stop >= clocksperline)
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stop -= clocksperline;
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sync->hsync = (stop << 16) | start;
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/* Get the vsync position */
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if (delay >= 0) {
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risesync_top = 1;
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fallsync_top = risesync_top;
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fallsync_top += mode->vsync_end - mode->vsync_start;
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fallsync_offs_top = (u32)delay;
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risesync_offs_top = (u32)delay;
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} else {
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risesync_top = mode->vtotal;
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fallsync_top = mode->vsync_end - mode->vsync_start;
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fallsync_offs_top = clocksperline + delay;
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risesync_offs_top = clocksperline + delay;
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}
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sync->vsync_line_top = (fallsync_top << 16) | risesync_top;
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sync->vsync_off_top = (fallsync_offs_top << 16) | risesync_offs_top;
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/* Only progressive supported for now */
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sync->vsync_line_bot = sync->vsync_line_top;
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sync->vsync_off_bot = sync->vsync_off_top;
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}
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static void vtg_set_mode(struct sti_vtg *vtg,
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int type,
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struct sti_vtg_sync_params *sync,
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const struct drm_display_mode *mode)
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{
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unsigned int i;
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/* Set the number of clock cycles per line */
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writel(mode->htotal, vtg->regs + VTG_CLKLN);
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/* Set Half Line Per Field (only progressive supported for now) */
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writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN);
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/* Program output window */
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vtg_set_output_window(vtg->regs, mode);
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/* Set hsync and vsync position for HDMI */
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vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDMI - 1], HDMI_DELAY, mode);
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/* Set hsync and vsync position for HD DCS */
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vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDDCS - 1], 0, mode);
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/* Set hsync and vsync position for HDF */
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vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDF - 1], AWG_DELAY_HD, mode);
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/* Set hsync and vsync position for DVO */
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vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_DVO - 1], DVO_DELAY, mode);
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/* Progam the syncs outputs */
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for (i = 0; i < VTG_MAX_SYNC_OUTPUT ; i++) {
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writel(sync[i].hsync,
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vtg->regs + vtg_regs_offs[i].h_hd);
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writel(sync[i].vsync_line_top,
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vtg->regs + vtg_regs_offs[i].top_v_vd);
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writel(sync[i].vsync_line_bot,
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vtg->regs + vtg_regs_offs[i].bot_v_vd);
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writel(sync[i].vsync_off_top,
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vtg->regs + vtg_regs_offs[i].top_v_hd);
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writel(sync[i].vsync_off_bot,
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vtg->regs + vtg_regs_offs[i].bot_v_hd);
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}
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/* mode */
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writel(type, vtg->regs + VTG_MODE);
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}
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static void vtg_enable_irq(struct sti_vtg *vtg)
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{
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/* clear interrupt status and mask */
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writel(0xFFFF, vtg->regs + VTG_HOST_ITS_BCLR);
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writel(0xFFFF, vtg->regs + VTG_HOST_ITM_BCLR);
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writel(VTG_IRQ_MASK, vtg->regs + VTG_HOST_ITM_BSET);
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}
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void sti_vtg_set_config(struct sti_vtg *vtg,
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const struct drm_display_mode *mode)
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{
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/* write configuration */
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vtg_set_mode(vtg, VTG_MODE_MASTER, vtg->sync_params, mode);
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vtg_reset(vtg);
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vtg_enable_irq(vtg);
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}
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/**
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* sti_vtg_get_line_number
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*
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* @mode: display mode to be used
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* @y: line
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*
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* Return the line number according to the display mode taking
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* into account the Sync and Back Porch information.
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* Video frame line numbers start at 1, y starts at 0.
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* In interlaced modes the start line is the field line number of the odd
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* field, but y is still defined as a progressive frame.
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*/
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u32 sti_vtg_get_line_number(struct drm_display_mode mode, int y)
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{
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u32 start_line = mode.vtotal - mode.vsync_start + 1;
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if (mode.flags & DRM_MODE_FLAG_INTERLACE)
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start_line *= 2;
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return start_line + y;
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}
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/**
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* sti_vtg_get_pixel_number
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*
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* @mode: display mode to be used
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* @x: row
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*
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* Return the pixel number according to the display mode taking
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* into account the Sync and Back Porch information.
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* Pixels are counted from 0.
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*/
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u32 sti_vtg_get_pixel_number(struct drm_display_mode mode, int x)
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{
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return mode.htotal - mode.hsync_start + x;
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}
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int sti_vtg_register_client(struct sti_vtg *vtg, struct notifier_block *nb,
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struct drm_crtc *crtc)
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{
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vtg->crtc = crtc;
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return raw_notifier_chain_register(&vtg->notifier_list, nb);
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}
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int sti_vtg_unregister_client(struct sti_vtg *vtg, struct notifier_block *nb)
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{
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return raw_notifier_chain_unregister(&vtg->notifier_list, nb);
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}
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static irqreturn_t vtg_irq_thread(int irq, void *arg)
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{
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struct sti_vtg *vtg = arg;
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u32 event;
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event = (vtg->irq_status & VTG_IRQ_TOP) ?
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VTG_TOP_FIELD_EVENT : VTG_BOTTOM_FIELD_EVENT;
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raw_notifier_call_chain(&vtg->notifier_list, event, vtg->crtc);
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return IRQ_HANDLED;
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}
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static irqreturn_t vtg_irq(int irq, void *arg)
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{
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struct sti_vtg *vtg = arg;
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vtg->irq_status = readl(vtg->regs + VTG_HOST_ITS);
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writel(vtg->irq_status, vtg->regs + VTG_HOST_ITS_BCLR);
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/* force sync bus write */
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readl(vtg->regs + VTG_HOST_ITS);
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return IRQ_WAKE_THREAD;
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}
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static int vtg_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct sti_vtg *vtg;
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struct resource *res;
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int ret;
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vtg = devm_kzalloc(dev, sizeof(*vtg), GFP_KERNEL);
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if (!vtg)
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return -ENOMEM;
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/* Get Memory ressources */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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DRM_ERROR("Get memory resource failed\n");
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return -ENOMEM;
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}
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vtg->regs = devm_ioremap(dev, res->start, resource_size(res));
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if (!vtg->regs) {
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DRM_ERROR("failed to remap I/O memory\n");
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return -ENOMEM;
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}
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vtg->irq = platform_get_irq(pdev, 0);
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if (vtg->irq < 0) {
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DRM_ERROR("Failed to get VTG interrupt\n");
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return vtg->irq;
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}
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RAW_INIT_NOTIFIER_HEAD(&vtg->notifier_list);
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ret = devm_request_threaded_irq(dev, vtg->irq, vtg_irq,
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vtg_irq_thread, IRQF_ONESHOT,
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dev_name(dev), vtg);
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if (ret < 0) {
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DRM_ERROR("Failed to register VTG interrupt\n");
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return ret;
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}
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platform_set_drvdata(pdev, vtg);
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DRM_INFO("%s %s\n", __func__, dev_name(dev));
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return 0;
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}
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static const struct of_device_id vtg_of_match[] = {
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{ .compatible = "st,vtg", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, vtg_of_match);
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struct platform_driver sti_vtg_driver = {
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.driver = {
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.name = "sti-vtg",
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.owner = THIS_MODULE,
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.of_match_table = vtg_of_match,
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},
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.probe = vtg_probe,
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};
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MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
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MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
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MODULE_LICENSE("GPL");
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