642 lines
16 KiB
C
642 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Synopsys DesignWare I2C adapter driver.
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*
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* Based on the TI DAVINCI I2C adapter driver.
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*
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* Copyright (C) 2006 Texas Instruments.
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* Copyright (C) 2007 MontaVista Software Inc.
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* Copyright (C) 2009 Provigent Ltd.
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*/
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#include <linux/acpi.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/export.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/swab.h>
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#include <linux/types.h>
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#include <linux/units.h>
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#include "i2c-designware-core.h"
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static char *abort_sources[] = {
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[ABRT_7B_ADDR_NOACK] =
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"slave address not acknowledged (7bit mode)",
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[ABRT_10ADDR1_NOACK] =
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"first address byte not acknowledged (10bit mode)",
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[ABRT_10ADDR2_NOACK] =
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"second address byte not acknowledged (10bit mode)",
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[ABRT_TXDATA_NOACK] =
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"data not acknowledged",
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[ABRT_GCALL_NOACK] =
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"no acknowledgement for a general call",
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[ABRT_GCALL_READ] =
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"read after general call",
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[ABRT_SBYTE_ACKDET] =
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"start byte acknowledged",
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[ABRT_SBYTE_NORSTRT] =
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"trying to send start byte when restart is disabled",
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[ABRT_10B_RD_NORSTRT] =
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"trying to read when restart is disabled (10bit mode)",
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[ABRT_MASTER_DIS] =
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"trying to use disabled adapter",
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[ARB_LOST] =
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"lost arbitration",
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[ABRT_SLAVE_FLUSH_TXFIFO] =
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"read command so flush old data in the TX FIFO",
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[ABRT_SLAVE_ARBLOST] =
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"slave lost the bus while transmitting data to a remote master",
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[ABRT_SLAVE_RD_INTX] =
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"incorrect slave-transmitter mode configuration",
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};
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static int dw_reg_read(void *context, unsigned int reg, unsigned int *val)
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{
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struct dw_i2c_dev *dev = context;
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*val = readl_relaxed(dev->base + reg);
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return 0;
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}
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static int dw_reg_write(void *context, unsigned int reg, unsigned int val)
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{
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struct dw_i2c_dev *dev = context;
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writel_relaxed(val, dev->base + reg);
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return 0;
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}
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static int dw_reg_read_swab(void *context, unsigned int reg, unsigned int *val)
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{
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struct dw_i2c_dev *dev = context;
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*val = swab32(readl_relaxed(dev->base + reg));
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return 0;
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}
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static int dw_reg_write_swab(void *context, unsigned int reg, unsigned int val)
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{
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struct dw_i2c_dev *dev = context;
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writel_relaxed(swab32(val), dev->base + reg);
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return 0;
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}
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static int dw_reg_read_word(void *context, unsigned int reg, unsigned int *val)
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{
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struct dw_i2c_dev *dev = context;
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*val = readw_relaxed(dev->base + reg) |
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(readw_relaxed(dev->base + reg + 2) << 16);
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return 0;
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}
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static int dw_reg_write_word(void *context, unsigned int reg, unsigned int val)
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{
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struct dw_i2c_dev *dev = context;
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writew_relaxed(val, dev->base + reg);
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writew_relaxed(val >> 16, dev->base + reg + 2);
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return 0;
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}
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/**
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* i2c_dw_init_regmap() - Initialize registers map
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* @dev: device private data
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*
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* Autodetects needed register access mode and creates the regmap with
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* corresponding read/write callbacks. This must be called before doing any
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* other register access.
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*/
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int i2c_dw_init_regmap(struct dw_i2c_dev *dev)
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{
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struct regmap_config map_cfg = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.disable_locking = true,
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.reg_read = dw_reg_read,
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.reg_write = dw_reg_write,
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.max_register = DW_IC_COMP_TYPE,
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};
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u32 reg;
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int ret;
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/*
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* Skip detecting the registers map configuration if the regmap has
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* already been provided by a higher code.
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*/
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if (dev->map)
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return 0;
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ret = i2c_dw_acquire_lock(dev);
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if (ret)
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return ret;
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reg = readl(dev->base + DW_IC_COMP_TYPE);
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i2c_dw_release_lock(dev);
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if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU)
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map_cfg.max_register = AMD_UCSI_INTR_REG;
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if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) {
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map_cfg.reg_read = dw_reg_read_swab;
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map_cfg.reg_write = dw_reg_write_swab;
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} else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
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map_cfg.reg_read = dw_reg_read_word;
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map_cfg.reg_write = dw_reg_write_word;
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} else if (reg != DW_IC_COMP_TYPE_VALUE) {
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dev_err(dev->dev,
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"Unknown Synopsys component type: 0x%08x\n", reg);
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return -ENODEV;
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}
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/*
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* Note we'll check the return value of the regmap IO accessors only
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* at the probe stage. The rest of the code won't do this because
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* basically we have MMIO-based regmap so non of the read/write methods
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* can fail.
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*/
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dev->map = devm_regmap_init(dev->dev, NULL, dev, &map_cfg);
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if (IS_ERR(dev->map)) {
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dev_err(dev->dev, "Failed to init the registers map\n");
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return PTR_ERR(dev->map);
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}
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return 0;
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}
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static const u32 supported_speeds[] = {
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I2C_MAX_HIGH_SPEED_MODE_FREQ,
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I2C_MAX_FAST_MODE_PLUS_FREQ,
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I2C_MAX_FAST_MODE_FREQ,
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I2C_MAX_STANDARD_MODE_FREQ,
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};
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int i2c_dw_validate_speed(struct dw_i2c_dev *dev)
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{
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struct i2c_timings *t = &dev->timings;
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unsigned int i;
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/*
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* Only standard mode at 100kHz, fast mode at 400kHz,
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* fast mode plus at 1MHz and high speed mode at 3.4MHz are supported.
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*/
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for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
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if (t->bus_freq_hz == supported_speeds[i])
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return 0;
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}
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dev_err(dev->dev,
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"%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n",
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t->bus_freq_hz);
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return -EINVAL;
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}
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EXPORT_SYMBOL_GPL(i2c_dw_validate_speed);
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#ifdef CONFIG_ACPI
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#include <linux/dmi.h>
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/*
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* The HCNT/LCNT information coming from ACPI should be the most accurate
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* for given platform. However, some systems get it wrong. On such systems
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* we get better results by calculating those based on the input clock.
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*/
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static const struct dmi_system_id i2c_dw_no_acpi_params[] = {
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{
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.ident = "Dell Inspiron 7348",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
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DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 7348"),
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},
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},
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{}
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};
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static void i2c_dw_acpi_params(struct device *device, char method[],
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u16 *hcnt, u16 *lcnt, u32 *sda_hold)
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{
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struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER };
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acpi_handle handle = ACPI_HANDLE(device);
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union acpi_object *obj;
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if (dmi_check_system(i2c_dw_no_acpi_params))
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return;
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if (ACPI_FAILURE(acpi_evaluate_object(handle, method, NULL, &buf)))
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return;
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obj = (union acpi_object *)buf.pointer;
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if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) {
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const union acpi_object *objs = obj->package.elements;
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*hcnt = (u16)objs[0].integer.value;
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*lcnt = (u16)objs[1].integer.value;
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*sda_hold = (u32)objs[2].integer.value;
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}
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kfree(buf.pointer);
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}
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int i2c_dw_acpi_configure(struct device *device)
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{
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struct dw_i2c_dev *dev = dev_get_drvdata(device);
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struct i2c_timings *t = &dev->timings;
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u32 ss_ht = 0, fp_ht = 0, hs_ht = 0, fs_ht = 0;
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/*
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* Try to get SDA hold time and *CNT values from an ACPI method for
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* selected speed modes.
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*/
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i2c_dw_acpi_params(device, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht);
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i2c_dw_acpi_params(device, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht);
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i2c_dw_acpi_params(device, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht);
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i2c_dw_acpi_params(device, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht);
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switch (t->bus_freq_hz) {
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case I2C_MAX_STANDARD_MODE_FREQ:
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dev->sda_hold_time = ss_ht;
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break;
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case I2C_MAX_FAST_MODE_PLUS_FREQ:
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dev->sda_hold_time = fp_ht;
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break;
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case I2C_MAX_HIGH_SPEED_MODE_FREQ:
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dev->sda_hold_time = hs_ht;
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break;
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case I2C_MAX_FAST_MODE_FREQ:
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default:
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dev->sda_hold_time = fs_ht;
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break;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(i2c_dw_acpi_configure);
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static u32 i2c_dw_acpi_round_bus_speed(struct device *device)
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{
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u32 acpi_speed;
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int i;
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acpi_speed = i2c_acpi_find_bus_speed(device);
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/*
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* Some DSTDs use a non standard speed, round down to the lowest
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* standard speed.
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*/
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for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
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if (acpi_speed >= supported_speeds[i])
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return supported_speeds[i];
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}
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return 0;
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}
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#else /* CONFIG_ACPI */
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static inline u32 i2c_dw_acpi_round_bus_speed(struct device *device) { return 0; }
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#endif /* CONFIG_ACPI */
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void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev)
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{
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u32 acpi_speed = i2c_dw_acpi_round_bus_speed(dev->dev);
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struct i2c_timings *t = &dev->timings;
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/*
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* Find bus speed from the "clock-frequency" device property, ACPI
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* or by using fast mode if neither is set.
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*/
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if (acpi_speed && t->bus_freq_hz)
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t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed);
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else if (acpi_speed || t->bus_freq_hz)
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t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed);
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else
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t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
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}
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EXPORT_SYMBOL_GPL(i2c_dw_adjust_bus_speed);
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u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
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{
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/*
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* DesignWare I2C core doesn't seem to have solid strategy to meet
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* the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
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* will result in violation of the tHD;STA spec.
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*/
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if (cond)
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/*
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* Conditional expression:
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*
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* IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
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*
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* This is based on the DW manuals, and represents an ideal
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* configuration. The resulting I2C bus speed will be
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* faster than any of the others.
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*
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* If your hardware is free from tHD;STA issue, try this one.
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*/
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return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * tSYMBOL, MICRO) -
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8 + offset;
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else
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/*
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* Conditional expression:
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*
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* IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
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*
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* This is just experimental rule; the tHD;STA period turned
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* out to be proportinal to (_HCNT + 3). With this setting,
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* we could meet both tHIGH and tHD;STA timing specs.
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*
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* If unsure, you'd better to take this alternative.
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*
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* The reason why we need to take into account "tf" here,
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* is the same as described in i2c_dw_scl_lcnt().
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*/
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return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tSYMBOL + tf), MICRO) -
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3 + offset;
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}
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u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
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{
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/*
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* Conditional expression:
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*
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* IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
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*
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* DW I2C core starts counting the SCL CNTs for the LOW period
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* of the SCL clock (tLOW) as soon as it pulls the SCL line.
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* In order to meet the tLOW timing spec, we need to take into
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* account the fall time of SCL signal (tf). Default tf value
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* should be 0.3 us, for safety.
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*/
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return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tLOW + tf), MICRO) -
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1 + offset;
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}
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int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev)
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{
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unsigned int reg;
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int ret;
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ret = i2c_dw_acquire_lock(dev);
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if (ret)
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return ret;
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/* Configure SDA Hold Time if required */
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ret = regmap_read(dev->map, DW_IC_COMP_VERSION, ®);
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if (ret)
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goto err_release_lock;
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if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
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if (!dev->sda_hold_time) {
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/* Keep previous hold time setting if no one set it */
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ret = regmap_read(dev->map, DW_IC_SDA_HOLD,
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&dev->sda_hold_time);
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if (ret)
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goto err_release_lock;
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}
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/*
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* Workaround for avoiding TX arbitration lost in case I2C
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* slave pulls SDA down "too quickly" after falling edge of
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* SCL by enabling non-zero SDA RX hold. Specification says it
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* extends incoming SDA low to high transition while SCL is
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* high but it appears to help also above issue.
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*/
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if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
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dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
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dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n",
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dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK,
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dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT);
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} else if (dev->set_sda_hold_time) {
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dev->set_sda_hold_time(dev);
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} else if (dev->sda_hold_time) {
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dev_warn(dev->dev,
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"Hardware too old to adjust SDA hold time.\n");
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dev->sda_hold_time = 0;
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}
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err_release_lock:
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i2c_dw_release_lock(dev);
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return ret;
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}
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void __i2c_dw_disable(struct dw_i2c_dev *dev)
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{
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int timeout = 100;
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unsigned int status;
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do {
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__i2c_dw_disable_nowait(dev);
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/*
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* The enable status register may be unimplemented, but
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* in that case this test reads zero and exits the loop.
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*/
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regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status);
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if ((status & 1) == 0)
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return;
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/*
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* Wait 10 times the signaling period of the highest I2C
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* transfer supported by the driver (for 400KHz this is
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* 25us) as described in the DesignWare I2C databook.
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*/
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usleep_range(25, 250);
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} while (timeout--);
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dev_warn(dev->dev, "timeout in disabling adapter\n");
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}
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u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev)
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{
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/*
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* Clock is not necessary if we got LCNT/HCNT values directly from
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* the platform code.
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*/
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if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
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return 0;
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return dev->get_clk_rate_khz(dev);
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}
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int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare)
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{
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int ret;
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if (prepare) {
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/* Optional interface clock */
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ret = clk_prepare_enable(dev->pclk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(dev->clk);
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if (ret)
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clk_disable_unprepare(dev->pclk);
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return ret;
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|
}
|
|
|
|
clk_disable_unprepare(dev->clk);
|
|
clk_disable_unprepare(dev->pclk);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk);
|
|
|
|
int i2c_dw_acquire_lock(struct dw_i2c_dev *dev)
|
|
{
|
|
int ret;
|
|
|
|
if (!dev->acquire_lock)
|
|
return 0;
|
|
|
|
ret = dev->acquire_lock();
|
|
if (!ret)
|
|
return 0;
|
|
|
|
dev_err(dev->dev, "couldn't acquire bus ownership\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
void i2c_dw_release_lock(struct dw_i2c_dev *dev)
|
|
{
|
|
if (dev->release_lock)
|
|
dev->release_lock();
|
|
}
|
|
|
|
/*
|
|
* Waiting for bus not busy
|
|
*/
|
|
int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
|
|
{
|
|
unsigned int status;
|
|
int ret;
|
|
|
|
ret = regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status,
|
|
!(status & DW_IC_STATUS_ACTIVITY),
|
|
1100, 20000);
|
|
if (ret) {
|
|
dev_warn(dev->dev, "timeout waiting for bus ready\n");
|
|
|
|
i2c_recover_bus(&dev->adapter);
|
|
|
|
regmap_read(dev->map, DW_IC_STATUS, &status);
|
|
if (!(status & DW_IC_STATUS_ACTIVITY))
|
|
ret = 0;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
|
|
{
|
|
unsigned long abort_source = dev->abort_source;
|
|
int i;
|
|
|
|
if (abort_source & DW_IC_TX_ABRT_NOACK) {
|
|
for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
|
|
dev_dbg(dev->dev,
|
|
"%s: %s\n", __func__, abort_sources[i]);
|
|
return -EREMOTEIO;
|
|
}
|
|
|
|
for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
|
|
dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
|
|
|
|
if (abort_source & DW_IC_TX_ARB_LOST)
|
|
return -EAGAIN;
|
|
else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
|
|
return -EINVAL; /* wrong msgs[] data */
|
|
else
|
|
return -EIO;
|
|
}
|
|
|
|
int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev)
|
|
{
|
|
u32 tx_fifo_depth, rx_fifo_depth;
|
|
unsigned int param;
|
|
int ret;
|
|
|
|
/* DW_IC_COMP_PARAM_1 not implement for IP issue */
|
|
if ((dev->flags & MODEL_MASK) == MODEL_WANGXUN_SP) {
|
|
dev->tx_fifo_depth = TXGBE_TX_FIFO_DEPTH;
|
|
dev->rx_fifo_depth = TXGBE_RX_FIFO_DEPTH;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Try to detect the FIFO depth if not set by interface driver,
|
|
* the depth could be from 2 to 256 from HW spec.
|
|
*/
|
|
ret = i2c_dw_acquire_lock(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, ¶m);
|
|
i2c_dw_release_lock(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
tx_fifo_depth = ((param >> 16) & 0xff) + 1;
|
|
rx_fifo_depth = ((param >> 8) & 0xff) + 1;
|
|
if (!dev->tx_fifo_depth) {
|
|
dev->tx_fifo_depth = tx_fifo_depth;
|
|
dev->rx_fifo_depth = rx_fifo_depth;
|
|
} else if (tx_fifo_depth >= 2) {
|
|
dev->tx_fifo_depth = min_t(u32, dev->tx_fifo_depth,
|
|
tx_fifo_depth);
|
|
dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth,
|
|
rx_fifo_depth);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
u32 i2c_dw_func(struct i2c_adapter *adap)
|
|
{
|
|
struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
|
|
|
|
return dev->functionality;
|
|
}
|
|
|
|
void i2c_dw_disable(struct dw_i2c_dev *dev)
|
|
{
|
|
unsigned int dummy;
|
|
int ret;
|
|
|
|
ret = i2c_dw_acquire_lock(dev);
|
|
if (ret)
|
|
return;
|
|
|
|
/* Disable controller */
|
|
__i2c_dw_disable(dev);
|
|
|
|
/* Disable all interrupts */
|
|
regmap_write(dev->map, DW_IC_INTR_MASK, 0);
|
|
regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
|
|
|
|
i2c_dw_release_lock(dev);
|
|
}
|
|
|
|
MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
|
|
MODULE_LICENSE("GPL");
|