729 lines
21 KiB
C
729 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Aspeed AST2400/2500/2600 ADC
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*
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* Copyright (C) 2017 Google, Inc.
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* Copyright (C) 2021 Aspeed Technology Inc.
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*
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* ADC clock formula:
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* Ast2400/Ast2500:
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* clock period = period of PCLK * 2 * (ADC0C[31:17] + 1) * (ADC0C[9:0] + 1)
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* Ast2600:
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* clock period = period of PCLK * 2 * (ADC0C[15:0] + 1)
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/bitfield.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/driver.h>
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#include <linux/iopoll.h>
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#define ASPEED_RESOLUTION_BITS 10
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#define ASPEED_CLOCKS_PER_SAMPLE 12
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#define ASPEED_REG_ENGINE_CONTROL 0x00
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#define ASPEED_REG_INTERRUPT_CONTROL 0x04
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#define ASPEED_REG_VGA_DETECT_CONTROL 0x08
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#define ASPEED_REG_CLOCK_CONTROL 0x0C
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#define ASPEED_REG_COMPENSATION_TRIM 0xC4
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/*
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* The register offset between 0xC8~0xCC can be read and won't affect the
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* hardware logic in each version of ADC.
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*/
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#define ASPEED_REG_MAX 0xD0
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#define ASPEED_ADC_ENGINE_ENABLE BIT(0)
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#define ASPEED_ADC_OP_MODE GENMASK(3, 1)
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#define ASPEED_ADC_OP_MODE_PWR_DOWN 0
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#define ASPEED_ADC_OP_MODE_STANDBY 1
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#define ASPEED_ADC_OP_MODE_NORMAL 7
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#define ASPEED_ADC_CTRL_COMPENSATION BIT(4)
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#define ASPEED_ADC_AUTO_COMPENSATION BIT(5)
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/*
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* Bit 6 determines not only the reference voltage range but also the dividing
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* circuit for battery sensing.
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*/
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#define ASPEED_ADC_REF_VOLTAGE GENMASK(7, 6)
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#define ASPEED_ADC_REF_VOLTAGE_2500mV 0
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#define ASPEED_ADC_REF_VOLTAGE_1200mV 1
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#define ASPEED_ADC_REF_VOLTAGE_EXT_HIGH 2
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#define ASPEED_ADC_REF_VOLTAGE_EXT_LOW 3
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#define ASPEED_ADC_BAT_SENSING_DIV BIT(6)
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#define ASPEED_ADC_BAT_SENSING_DIV_2_3 0
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#define ASPEED_ADC_BAT_SENSING_DIV_1_3 1
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#define ASPEED_ADC_CTRL_INIT_RDY BIT(8)
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#define ASPEED_ADC_CH7_MODE BIT(12)
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#define ASPEED_ADC_CH7_NORMAL 0
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#define ASPEED_ADC_CH7_BAT 1
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#define ASPEED_ADC_BAT_SENSING_ENABLE BIT(13)
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#define ASPEED_ADC_CTRL_CHANNEL GENMASK(31, 16)
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#define ASPEED_ADC_CTRL_CHANNEL_ENABLE(ch) FIELD_PREP(ASPEED_ADC_CTRL_CHANNEL, BIT(ch))
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#define ASPEED_ADC_INIT_POLLING_TIME 500
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#define ASPEED_ADC_INIT_TIMEOUT 500000
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/*
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* When the sampling rate is too high, the ADC may not have enough charging
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* time, resulting in a low voltage value. Thus, the default uses a slow
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* sampling rate for most use cases.
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*/
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#define ASPEED_ADC_DEF_SAMPLING_RATE 65000
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struct aspeed_adc_trim_locate {
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const unsigned int offset;
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const unsigned int field;
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};
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struct aspeed_adc_model_data {
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const char *model_name;
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unsigned int min_sampling_rate; // Hz
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unsigned int max_sampling_rate; // Hz
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unsigned int vref_fixed_mv;
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bool wait_init_sequence;
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bool need_prescaler;
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bool bat_sense_sup;
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u8 scaler_bit_width;
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unsigned int num_channels;
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const struct aspeed_adc_trim_locate *trim_locate;
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};
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struct adc_gain {
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u8 mult;
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u8 div;
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};
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struct aspeed_adc_data {
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struct device *dev;
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const struct aspeed_adc_model_data *model_data;
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struct regulator *regulator;
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void __iomem *base;
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spinlock_t clk_lock;
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struct clk_hw *fixed_div_clk;
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struct clk_hw *clk_prescaler;
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struct clk_hw *clk_scaler;
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struct reset_control *rst;
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int vref_mv;
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u32 sample_period_ns;
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int cv;
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bool battery_sensing;
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struct adc_gain battery_mode_gain;
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};
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#define ASPEED_CHAN(_idx, _data_reg_addr) { \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = (_idx), \
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.address = (_data_reg_addr), \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
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BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
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BIT(IIO_CHAN_INFO_OFFSET), \
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}
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static const struct iio_chan_spec aspeed_adc_iio_channels[] = {
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ASPEED_CHAN(0, 0x10),
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ASPEED_CHAN(1, 0x12),
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ASPEED_CHAN(2, 0x14),
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ASPEED_CHAN(3, 0x16),
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ASPEED_CHAN(4, 0x18),
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ASPEED_CHAN(5, 0x1A),
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ASPEED_CHAN(6, 0x1C),
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ASPEED_CHAN(7, 0x1E),
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ASPEED_CHAN(8, 0x20),
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ASPEED_CHAN(9, 0x22),
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ASPEED_CHAN(10, 0x24),
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ASPEED_CHAN(11, 0x26),
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ASPEED_CHAN(12, 0x28),
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ASPEED_CHAN(13, 0x2A),
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ASPEED_CHAN(14, 0x2C),
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ASPEED_CHAN(15, 0x2E),
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};
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#define ASPEED_BAT_CHAN(_idx, _data_reg_addr) { \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = (_idx), \
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.address = (_data_reg_addr), \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_OFFSET), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
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BIT(IIO_CHAN_INFO_SAMP_FREQ), \
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}
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static const struct iio_chan_spec aspeed_adc_iio_bat_channels[] = {
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ASPEED_CHAN(0, 0x10),
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ASPEED_CHAN(1, 0x12),
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ASPEED_CHAN(2, 0x14),
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ASPEED_CHAN(3, 0x16),
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ASPEED_CHAN(4, 0x18),
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ASPEED_CHAN(5, 0x1A),
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ASPEED_CHAN(6, 0x1C),
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ASPEED_BAT_CHAN(7, 0x1E),
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};
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static int aspeed_adc_set_trim_data(struct iio_dev *indio_dev)
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{
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struct device_node *syscon;
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struct regmap *scu;
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u32 scu_otp, trimming_val;
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struct aspeed_adc_data *data = iio_priv(indio_dev);
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syscon = of_find_node_by_name(NULL, "syscon");
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if (syscon == NULL) {
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dev_warn(data->dev, "Couldn't find syscon node\n");
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return -EOPNOTSUPP;
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}
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scu = syscon_node_to_regmap(syscon);
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of_node_put(syscon);
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if (IS_ERR(scu)) {
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dev_warn(data->dev, "Failed to get syscon regmap\n");
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return -EOPNOTSUPP;
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}
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if (data->model_data->trim_locate) {
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if (regmap_read(scu, data->model_data->trim_locate->offset,
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&scu_otp)) {
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dev_warn(data->dev,
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"Failed to get adc trimming data\n");
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trimming_val = 0x8;
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} else {
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trimming_val =
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((scu_otp) &
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(data->model_data->trim_locate->field)) >>
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__ffs(data->model_data->trim_locate->field);
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if (!trimming_val)
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trimming_val = 0x8;
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}
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dev_dbg(data->dev,
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"trimming val = %d, offset = %08x, fields = %08x\n",
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trimming_val, data->model_data->trim_locate->offset,
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data->model_data->trim_locate->field);
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writel(trimming_val, data->base + ASPEED_REG_COMPENSATION_TRIM);
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}
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return 0;
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}
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static int aspeed_adc_compensation(struct iio_dev *indio_dev)
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{
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struct aspeed_adc_data *data = iio_priv(indio_dev);
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u32 index, adc_raw = 0;
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u32 adc_engine_control_reg_val;
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adc_engine_control_reg_val =
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readl(data->base + ASPEED_REG_ENGINE_CONTROL);
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adc_engine_control_reg_val &= ~ASPEED_ADC_OP_MODE;
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adc_engine_control_reg_val |=
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(FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) |
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ASPEED_ADC_ENGINE_ENABLE);
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/*
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* Enable compensating sensing:
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* After that, the input voltage of ADC will force to half of the reference
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* voltage. So the expected reading raw data will become half of the max
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* value. We can get compensating value = 0x200 - ADC read raw value.
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* It is recommended to average at least 10 samples to get a final CV.
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*/
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writel(adc_engine_control_reg_val | ASPEED_ADC_CTRL_COMPENSATION |
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ASPEED_ADC_CTRL_CHANNEL_ENABLE(0),
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data->base + ASPEED_REG_ENGINE_CONTROL);
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/*
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* After enable compensating sensing mode need to wait some time for ADC stable
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* Experiment result is 1ms.
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*/
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mdelay(1);
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for (index = 0; index < 16; index++) {
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/*
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* Waiting for the sampling period ensures that the value acquired
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* is fresh each time.
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*/
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ndelay(data->sample_period_ns);
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adc_raw += readw(data->base + aspeed_adc_iio_channels[0].address);
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}
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adc_raw >>= 4;
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data->cv = BIT(ASPEED_RESOLUTION_BITS - 1) - adc_raw;
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writel(adc_engine_control_reg_val,
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data->base + ASPEED_REG_ENGINE_CONTROL);
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dev_dbg(data->dev, "Compensating value = %d\n", data->cv);
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return 0;
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}
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static int aspeed_adc_set_sampling_rate(struct iio_dev *indio_dev, u32 rate)
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{
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struct aspeed_adc_data *data = iio_priv(indio_dev);
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if (rate < data->model_data->min_sampling_rate ||
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rate > data->model_data->max_sampling_rate)
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return -EINVAL;
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/* Each sampling needs 12 clocks to convert.*/
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clk_set_rate(data->clk_scaler->clk, rate * ASPEED_CLOCKS_PER_SAMPLE);
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rate = clk_get_rate(data->clk_scaler->clk);
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data->sample_period_ns = DIV_ROUND_UP_ULL(
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(u64)NSEC_PER_SEC * ASPEED_CLOCKS_PER_SAMPLE, rate);
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dev_dbg(data->dev, "Adc clock = %d sample period = %d ns", rate,
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data->sample_period_ns);
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return 0;
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}
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static int aspeed_adc_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct aspeed_adc_data *data = iio_priv(indio_dev);
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u32 adc_engine_control_reg_val;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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if (data->battery_sensing && chan->channel == 7) {
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adc_engine_control_reg_val =
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readl(data->base + ASPEED_REG_ENGINE_CONTROL);
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writel(adc_engine_control_reg_val |
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FIELD_PREP(ASPEED_ADC_CH7_MODE,
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ASPEED_ADC_CH7_BAT) |
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ASPEED_ADC_BAT_SENSING_ENABLE,
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data->base + ASPEED_REG_ENGINE_CONTROL);
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/*
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* After enable battery sensing mode need to wait some time for adc stable
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* Experiment result is 1ms.
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*/
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mdelay(1);
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*val = readw(data->base + chan->address);
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*val = (*val * data->battery_mode_gain.mult) /
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data->battery_mode_gain.div;
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/* Restore control register value */
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writel(adc_engine_control_reg_val,
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data->base + ASPEED_REG_ENGINE_CONTROL);
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} else
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*val = readw(data->base + chan->address);
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_OFFSET:
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if (data->battery_sensing && chan->channel == 7)
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*val = (data->cv * data->battery_mode_gain.mult) /
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data->battery_mode_gain.div;
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else
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*val = data->cv;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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*val = data->vref_mv;
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*val2 = ASPEED_RESOLUTION_BITS;
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return IIO_VAL_FRACTIONAL_LOG2;
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case IIO_CHAN_INFO_SAMP_FREQ:
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*val = clk_get_rate(data->clk_scaler->clk) /
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ASPEED_CLOCKS_PER_SAMPLE;
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return IIO_VAL_INT;
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default:
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return -EINVAL;
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}
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}
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static int aspeed_adc_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val, int val2, long mask)
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{
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switch (mask) {
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case IIO_CHAN_INFO_SAMP_FREQ:
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return aspeed_adc_set_sampling_rate(indio_dev, val);
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case IIO_CHAN_INFO_SCALE:
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case IIO_CHAN_INFO_RAW:
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/*
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* Technically, these could be written but the only reasons
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* for doing so seem better handled in userspace. EPERM is
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* returned to signal this is a policy choice rather than a
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* hardware limitation.
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*/
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return -EPERM;
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default:
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return -EINVAL;
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}
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}
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static int aspeed_adc_reg_access(struct iio_dev *indio_dev,
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unsigned int reg, unsigned int writeval,
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unsigned int *readval)
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{
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struct aspeed_adc_data *data = iio_priv(indio_dev);
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if (!readval || reg % 4 || reg > ASPEED_REG_MAX)
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return -EINVAL;
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*readval = readl(data->base + reg);
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return 0;
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}
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static const struct iio_info aspeed_adc_iio_info = {
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.read_raw = aspeed_adc_read_raw,
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.write_raw = aspeed_adc_write_raw,
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.debugfs_reg_access = aspeed_adc_reg_access,
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};
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static void aspeed_adc_unregister_fixed_divider(void *data)
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{
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struct clk_hw *clk = data;
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clk_hw_unregister_fixed_factor(clk);
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}
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static void aspeed_adc_reset_assert(void *data)
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{
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struct reset_control *rst = data;
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reset_control_assert(rst);
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}
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static void aspeed_adc_clk_disable_unprepare(void *data)
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{
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struct clk *clk = data;
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clk_disable_unprepare(clk);
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}
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static void aspeed_adc_power_down(void *data)
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{
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struct aspeed_adc_data *priv_data = data;
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writel(FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_PWR_DOWN),
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priv_data->base + ASPEED_REG_ENGINE_CONTROL);
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}
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static void aspeed_adc_reg_disable(void *data)
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{
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struct regulator *reg = data;
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regulator_disable(reg);
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}
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static int aspeed_adc_vref_config(struct iio_dev *indio_dev)
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{
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struct aspeed_adc_data *data = iio_priv(indio_dev);
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int ret;
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u32 adc_engine_control_reg_val;
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if (data->model_data->vref_fixed_mv) {
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data->vref_mv = data->model_data->vref_fixed_mv;
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return 0;
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}
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adc_engine_control_reg_val =
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readl(data->base + ASPEED_REG_ENGINE_CONTROL);
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data->regulator = devm_regulator_get_optional(data->dev, "vref");
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if (!IS_ERR(data->regulator)) {
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ret = regulator_enable(data->regulator);
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if (ret)
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return ret;
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ret = devm_add_action_or_reset(
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data->dev, aspeed_adc_reg_disable, data->regulator);
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if (ret)
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return ret;
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data->vref_mv = regulator_get_voltage(data->regulator);
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/* Conversion from uV to mV */
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data->vref_mv /= 1000;
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if ((data->vref_mv >= 1550) && (data->vref_mv <= 2700))
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writel(adc_engine_control_reg_val |
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FIELD_PREP(
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ASPEED_ADC_REF_VOLTAGE,
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ASPEED_ADC_REF_VOLTAGE_EXT_HIGH),
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data->base + ASPEED_REG_ENGINE_CONTROL);
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else if ((data->vref_mv >= 900) && (data->vref_mv <= 1650))
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writel(adc_engine_control_reg_val |
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FIELD_PREP(
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ASPEED_ADC_REF_VOLTAGE,
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ASPEED_ADC_REF_VOLTAGE_EXT_LOW),
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data->base + ASPEED_REG_ENGINE_CONTROL);
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else {
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dev_err(data->dev, "Regulator voltage %d not support",
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data->vref_mv);
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return -EOPNOTSUPP;
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}
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} else {
|
|
if (PTR_ERR(data->regulator) != -ENODEV)
|
|
return PTR_ERR(data->regulator);
|
|
data->vref_mv = 2500000;
|
|
of_property_read_u32(data->dev->of_node,
|
|
"aspeed,int-vref-microvolt",
|
|
&data->vref_mv);
|
|
/* Conversion from uV to mV */
|
|
data->vref_mv /= 1000;
|
|
if (data->vref_mv == 2500)
|
|
writel(adc_engine_control_reg_val |
|
|
FIELD_PREP(ASPEED_ADC_REF_VOLTAGE,
|
|
ASPEED_ADC_REF_VOLTAGE_2500mV),
|
|
data->base + ASPEED_REG_ENGINE_CONTROL);
|
|
else if (data->vref_mv == 1200)
|
|
writel(adc_engine_control_reg_val |
|
|
FIELD_PREP(ASPEED_ADC_REF_VOLTAGE,
|
|
ASPEED_ADC_REF_VOLTAGE_1200mV),
|
|
data->base + ASPEED_REG_ENGINE_CONTROL);
|
|
else {
|
|
dev_err(data->dev, "Voltage %d not support", data->vref_mv);
|
|
return -EOPNOTSUPP;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int aspeed_adc_probe(struct platform_device *pdev)
|
|
{
|
|
struct iio_dev *indio_dev;
|
|
struct aspeed_adc_data *data;
|
|
int ret;
|
|
u32 adc_engine_control_reg_val;
|
|
unsigned long scaler_flags = 0;
|
|
char clk_name[32], clk_parent_name[32];
|
|
|
|
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data));
|
|
if (!indio_dev)
|
|
return -ENOMEM;
|
|
|
|
data = iio_priv(indio_dev);
|
|
data->dev = &pdev->dev;
|
|
data->model_data = of_device_get_match_data(&pdev->dev);
|
|
platform_set_drvdata(pdev, indio_dev);
|
|
|
|
data->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(data->base))
|
|
return PTR_ERR(data->base);
|
|
|
|
/* Register ADC clock prescaler with source specified by device tree. */
|
|
spin_lock_init(&data->clk_lock);
|
|
snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), "%s",
|
|
of_clk_get_parent_name(pdev->dev.of_node, 0));
|
|
snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-fixed-div",
|
|
data->model_data->model_name);
|
|
data->fixed_div_clk = clk_hw_register_fixed_factor(
|
|
&pdev->dev, clk_name, clk_parent_name, 0, 1, 2);
|
|
if (IS_ERR(data->fixed_div_clk))
|
|
return PTR_ERR(data->fixed_div_clk);
|
|
|
|
ret = devm_add_action_or_reset(data->dev,
|
|
aspeed_adc_unregister_fixed_divider,
|
|
data->fixed_div_clk);
|
|
if (ret)
|
|
return ret;
|
|
snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), clk_name);
|
|
|
|
if (data->model_data->need_prescaler) {
|
|
snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-prescaler",
|
|
data->model_data->model_name);
|
|
data->clk_prescaler = devm_clk_hw_register_divider(
|
|
&pdev->dev, clk_name, clk_parent_name, 0,
|
|
data->base + ASPEED_REG_CLOCK_CONTROL, 17, 15, 0,
|
|
&data->clk_lock);
|
|
if (IS_ERR(data->clk_prescaler))
|
|
return PTR_ERR(data->clk_prescaler);
|
|
snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name),
|
|
clk_name);
|
|
scaler_flags = CLK_SET_RATE_PARENT;
|
|
}
|
|
/*
|
|
* Register ADC clock scaler downstream from the prescaler. Allow rate
|
|
* setting to adjust the prescaler as well.
|
|
*/
|
|
snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-scaler",
|
|
data->model_data->model_name);
|
|
data->clk_scaler = devm_clk_hw_register_divider(
|
|
&pdev->dev, clk_name, clk_parent_name, scaler_flags,
|
|
data->base + ASPEED_REG_CLOCK_CONTROL, 0,
|
|
data->model_data->scaler_bit_width,
|
|
data->model_data->need_prescaler ? CLK_DIVIDER_ONE_BASED : 0,
|
|
&data->clk_lock);
|
|
if (IS_ERR(data->clk_scaler))
|
|
return PTR_ERR(data->clk_scaler);
|
|
|
|
data->rst = devm_reset_control_get_shared(&pdev->dev, NULL);
|
|
if (IS_ERR(data->rst)) {
|
|
dev_err(&pdev->dev,
|
|
"invalid or missing reset controller device tree entry");
|
|
return PTR_ERR(data->rst);
|
|
}
|
|
reset_control_deassert(data->rst);
|
|
|
|
ret = devm_add_action_or_reset(data->dev, aspeed_adc_reset_assert,
|
|
data->rst);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = aspeed_adc_vref_config(indio_dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = aspeed_adc_set_trim_data(indio_dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (of_find_property(data->dev->of_node, "aspeed,battery-sensing",
|
|
NULL)) {
|
|
if (data->model_data->bat_sense_sup) {
|
|
data->battery_sensing = 1;
|
|
if (readl(data->base + ASPEED_REG_ENGINE_CONTROL) &
|
|
ASPEED_ADC_BAT_SENSING_DIV) {
|
|
data->battery_mode_gain.mult = 3;
|
|
data->battery_mode_gain.div = 1;
|
|
} else {
|
|
data->battery_mode_gain.mult = 3;
|
|
data->battery_mode_gain.div = 2;
|
|
}
|
|
} else
|
|
dev_warn(&pdev->dev,
|
|
"Failed to enable battery-sensing mode\n");
|
|
}
|
|
|
|
ret = clk_prepare_enable(data->clk_scaler->clk);
|
|
if (ret)
|
|
return ret;
|
|
ret = devm_add_action_or_reset(data->dev,
|
|
aspeed_adc_clk_disable_unprepare,
|
|
data->clk_scaler->clk);
|
|
if (ret)
|
|
return ret;
|
|
ret = aspeed_adc_set_sampling_rate(indio_dev,
|
|
ASPEED_ADC_DEF_SAMPLING_RATE);
|
|
if (ret)
|
|
return ret;
|
|
|
|
adc_engine_control_reg_val =
|
|
readl(data->base + ASPEED_REG_ENGINE_CONTROL);
|
|
adc_engine_control_reg_val |=
|
|
FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) |
|
|
ASPEED_ADC_ENGINE_ENABLE;
|
|
/* Enable engine in normal mode. */
|
|
writel(adc_engine_control_reg_val,
|
|
data->base + ASPEED_REG_ENGINE_CONTROL);
|
|
|
|
ret = devm_add_action_or_reset(data->dev, aspeed_adc_power_down,
|
|
data);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (data->model_data->wait_init_sequence) {
|
|
/* Wait for initial sequence complete. */
|
|
ret = readl_poll_timeout(data->base + ASPEED_REG_ENGINE_CONTROL,
|
|
adc_engine_control_reg_val,
|
|
adc_engine_control_reg_val &
|
|
ASPEED_ADC_CTRL_INIT_RDY,
|
|
ASPEED_ADC_INIT_POLLING_TIME,
|
|
ASPEED_ADC_INIT_TIMEOUT);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
aspeed_adc_compensation(indio_dev);
|
|
/* Start all channels in normal mode. */
|
|
adc_engine_control_reg_val =
|
|
readl(data->base + ASPEED_REG_ENGINE_CONTROL);
|
|
adc_engine_control_reg_val |= ASPEED_ADC_CTRL_CHANNEL;
|
|
writel(adc_engine_control_reg_val,
|
|
data->base + ASPEED_REG_ENGINE_CONTROL);
|
|
|
|
indio_dev->name = data->model_data->model_name;
|
|
indio_dev->info = &aspeed_adc_iio_info;
|
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
|
indio_dev->channels = data->battery_sensing ?
|
|
aspeed_adc_iio_bat_channels :
|
|
aspeed_adc_iio_channels;
|
|
indio_dev->num_channels = data->model_data->num_channels;
|
|
|
|
ret = devm_iio_device_register(data->dev, indio_dev);
|
|
return ret;
|
|
}
|
|
|
|
static const struct aspeed_adc_trim_locate ast2500_adc_trim = {
|
|
.offset = 0x154,
|
|
.field = GENMASK(31, 28),
|
|
};
|
|
|
|
static const struct aspeed_adc_trim_locate ast2600_adc0_trim = {
|
|
.offset = 0x5d0,
|
|
.field = GENMASK(3, 0),
|
|
};
|
|
|
|
static const struct aspeed_adc_trim_locate ast2600_adc1_trim = {
|
|
.offset = 0x5d0,
|
|
.field = GENMASK(7, 4),
|
|
};
|
|
|
|
static const struct aspeed_adc_model_data ast2400_model_data = {
|
|
.model_name = "ast2400-adc",
|
|
.vref_fixed_mv = 2500,
|
|
.min_sampling_rate = 10000,
|
|
.max_sampling_rate = 500000,
|
|
.need_prescaler = true,
|
|
.scaler_bit_width = 10,
|
|
.num_channels = 16,
|
|
};
|
|
|
|
static const struct aspeed_adc_model_data ast2500_model_data = {
|
|
.model_name = "ast2500-adc",
|
|
.vref_fixed_mv = 1800,
|
|
.min_sampling_rate = 1,
|
|
.max_sampling_rate = 1000000,
|
|
.wait_init_sequence = true,
|
|
.need_prescaler = true,
|
|
.scaler_bit_width = 10,
|
|
.num_channels = 16,
|
|
.trim_locate = &ast2500_adc_trim,
|
|
};
|
|
|
|
static const struct aspeed_adc_model_data ast2600_adc0_model_data = {
|
|
.model_name = "ast2600-adc0",
|
|
.min_sampling_rate = 10000,
|
|
.max_sampling_rate = 500000,
|
|
.wait_init_sequence = true,
|
|
.bat_sense_sup = true,
|
|
.scaler_bit_width = 16,
|
|
.num_channels = 8,
|
|
.trim_locate = &ast2600_adc0_trim,
|
|
};
|
|
|
|
static const struct aspeed_adc_model_data ast2600_adc1_model_data = {
|
|
.model_name = "ast2600-adc1",
|
|
.min_sampling_rate = 10000,
|
|
.max_sampling_rate = 500000,
|
|
.wait_init_sequence = true,
|
|
.bat_sense_sup = true,
|
|
.scaler_bit_width = 16,
|
|
.num_channels = 8,
|
|
.trim_locate = &ast2600_adc1_trim,
|
|
};
|
|
|
|
static const struct of_device_id aspeed_adc_matches[] = {
|
|
{ .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data },
|
|
{ .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data },
|
|
{ .compatible = "aspeed,ast2600-adc0", .data = &ast2600_adc0_model_data },
|
|
{ .compatible = "aspeed,ast2600-adc1", .data = &ast2600_adc1_model_data },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, aspeed_adc_matches);
|
|
|
|
static struct platform_driver aspeed_adc_driver = {
|
|
.probe = aspeed_adc_probe,
|
|
.driver = {
|
|
.name = KBUILD_MODNAME,
|
|
.of_match_table = aspeed_adc_matches,
|
|
}
|
|
};
|
|
|
|
module_platform_driver(aspeed_adc_driver);
|
|
|
|
MODULE_AUTHOR("Rick Altherr <raltherr@google.com>");
|
|
MODULE_DESCRIPTION("Aspeed AST2400/2500/2600 ADC Driver");
|
|
MODULE_LICENSE("GPL");
|