618 lines
16 KiB
C
618 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* ADF4350/ADF4351 SPI Wideband Synthesizer driver
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*
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* Copyright 2012-2013 Analog Devices Inc.
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*/
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/property.h>
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#include <linux/slab.h>
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#include <linux/sysfs.h>
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#include <linux/spi/spi.h>
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#include <linux/regulator/consumer.h>
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#include <linux/err.h>
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#include <linux/gcd.h>
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#include <linux/gpio/consumer.h>
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#include <asm/div64.h>
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#include <linux/clk.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/iio/frequency/adf4350.h>
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enum {
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ADF4350_FREQ,
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ADF4350_FREQ_REFIN,
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ADF4350_FREQ_RESOLUTION,
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ADF4350_PWRDOWN,
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};
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struct adf4350_state {
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struct spi_device *spi;
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struct regulator *reg;
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struct gpio_desc *lock_detect_gpiod;
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struct adf4350_platform_data *pdata;
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struct clk *clk;
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unsigned long clkin;
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unsigned long chspc; /* Channel Spacing */
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unsigned long fpfd; /* Phase Frequency Detector */
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unsigned long min_out_freq;
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unsigned r0_fract;
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unsigned r0_int;
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unsigned r1_mod;
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unsigned r4_rf_div_sel;
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unsigned long regs[6];
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unsigned long regs_hw[6];
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unsigned long long freq_req;
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/*
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* Lock to protect the state of the device from potential concurrent
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* writes. The device is configured via a sequence of SPI writes,
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* and this lock is meant to prevent the start of another sequence
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* before another one has finished.
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*/
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struct mutex lock;
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/*
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* DMA (thus cache coherency maintenance) may require that
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* transfer buffers live in their own cache lines.
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*/
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__be32 val __aligned(IIO_DMA_MINALIGN);
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};
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static struct adf4350_platform_data default_pdata = {
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.channel_spacing = 10000,
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.r2_user_settings = ADF4350_REG2_PD_POLARITY_POS |
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ADF4350_REG2_CHARGE_PUMP_CURR_uA(2500),
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.r3_user_settings = ADF4350_REG3_12BIT_CLKDIV_MODE(0),
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.r4_user_settings = ADF4350_REG4_OUTPUT_PWR(3) |
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ADF4350_REG4_MUTE_TILL_LOCK_EN,
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};
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static int adf4350_sync_config(struct adf4350_state *st)
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{
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int ret, i, doublebuf = 0;
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for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) {
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if ((st->regs_hw[i] != st->regs[i]) ||
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((i == ADF4350_REG0) && doublebuf)) {
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switch (i) {
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case ADF4350_REG1:
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case ADF4350_REG4:
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doublebuf = 1;
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break;
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}
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st->val = cpu_to_be32(st->regs[i] | i);
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ret = spi_write(st->spi, &st->val, 4);
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if (ret < 0)
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return ret;
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st->regs_hw[i] = st->regs[i];
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dev_dbg(&st->spi->dev, "[%d] 0x%X\n",
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i, (u32)st->regs[i] | i);
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}
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}
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return 0;
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}
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static int adf4350_reg_access(struct iio_dev *indio_dev,
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unsigned reg, unsigned writeval,
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unsigned *readval)
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{
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struct adf4350_state *st = iio_priv(indio_dev);
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int ret;
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if (reg > ADF4350_REG5)
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return -EINVAL;
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mutex_lock(&st->lock);
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if (readval == NULL) {
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st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2));
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ret = adf4350_sync_config(st);
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} else {
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*readval = st->regs_hw[reg];
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ret = 0;
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}
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mutex_unlock(&st->lock);
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return ret;
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}
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static int adf4350_tune_r_cnt(struct adf4350_state *st, unsigned short r_cnt)
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{
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struct adf4350_platform_data *pdata = st->pdata;
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do {
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r_cnt++;
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st->fpfd = (st->clkin * (pdata->ref_doubler_en ? 2 : 1)) /
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(r_cnt * (pdata->ref_div2_en ? 2 : 1));
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} while (st->fpfd > ADF4350_MAX_FREQ_PFD);
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return r_cnt;
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}
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static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq)
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{
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struct adf4350_platform_data *pdata = st->pdata;
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u64 tmp;
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u32 div_gcd, prescaler, chspc;
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u16 mdiv, r_cnt = 0;
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u8 band_sel_div;
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if (freq > ADF4350_MAX_OUT_FREQ || freq < st->min_out_freq)
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return -EINVAL;
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if (freq > ADF4350_MAX_FREQ_45_PRESC) {
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prescaler = ADF4350_REG1_PRESCALER;
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mdiv = 75;
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} else {
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prescaler = 0;
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mdiv = 23;
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}
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st->r4_rf_div_sel = 0;
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while (freq < ADF4350_MIN_VCO_FREQ) {
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freq <<= 1;
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st->r4_rf_div_sel++;
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}
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/*
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* Allow a predefined reference division factor
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* if not set, compute our own
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*/
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if (pdata->ref_div_factor)
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r_cnt = pdata->ref_div_factor - 1;
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chspc = st->chspc;
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do {
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do {
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do {
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r_cnt = adf4350_tune_r_cnt(st, r_cnt);
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st->r1_mod = st->fpfd / chspc;
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if (r_cnt > ADF4350_MAX_R_CNT) {
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/* try higher spacing values */
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chspc++;
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r_cnt = 0;
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}
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} while ((st->r1_mod > ADF4350_MAX_MODULUS) && r_cnt);
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} while (r_cnt == 0);
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tmp = freq * (u64)st->r1_mod + (st->fpfd >> 1);
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do_div(tmp, st->fpfd); /* Div round closest (n + d/2)/d */
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st->r0_fract = do_div(tmp, st->r1_mod);
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st->r0_int = tmp;
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} while (mdiv > st->r0_int);
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band_sel_div = DIV_ROUND_UP(st->fpfd, ADF4350_MAX_BANDSEL_CLK);
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if (st->r0_fract && st->r1_mod) {
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div_gcd = gcd(st->r1_mod, st->r0_fract);
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st->r1_mod /= div_gcd;
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st->r0_fract /= div_gcd;
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} else {
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st->r0_fract = 0;
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st->r1_mod = 1;
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}
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dev_dbg(&st->spi->dev, "VCO: %llu Hz, PFD %lu Hz\n"
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"REF_DIV %d, R0_INT %d, R0_FRACT %d\n"
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"R1_MOD %d, RF_DIV %d\nPRESCALER %s, BAND_SEL_DIV %d\n",
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freq, st->fpfd, r_cnt, st->r0_int, st->r0_fract, st->r1_mod,
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1 << st->r4_rf_div_sel, prescaler ? "8/9" : "4/5",
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band_sel_div);
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st->regs[ADF4350_REG0] = ADF4350_REG0_INT(st->r0_int) |
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ADF4350_REG0_FRACT(st->r0_fract);
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st->regs[ADF4350_REG1] = ADF4350_REG1_PHASE(1) |
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ADF4350_REG1_MOD(st->r1_mod) |
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prescaler;
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st->regs[ADF4350_REG2] =
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ADF4350_REG2_10BIT_R_CNT(r_cnt) |
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ADF4350_REG2_DOUBLE_BUFF_EN |
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(pdata->ref_doubler_en ? ADF4350_REG2_RMULT2_EN : 0) |
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(pdata->ref_div2_en ? ADF4350_REG2_RDIV2_EN : 0) |
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(pdata->r2_user_settings & (ADF4350_REG2_PD_POLARITY_POS |
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ADF4350_REG2_LDP_6ns | ADF4350_REG2_LDF_INT_N |
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ADF4350_REG2_CHARGE_PUMP_CURR_uA(5000) |
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ADF4350_REG2_MUXOUT(0x7) | ADF4350_REG2_NOISE_MODE(0x3)));
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st->regs[ADF4350_REG3] = pdata->r3_user_settings &
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(ADF4350_REG3_12BIT_CLKDIV(0xFFF) |
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ADF4350_REG3_12BIT_CLKDIV_MODE(0x3) |
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ADF4350_REG3_12BIT_CSR_EN |
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ADF4351_REG3_CHARGE_CANCELLATION_EN |
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ADF4351_REG3_ANTI_BACKLASH_3ns_EN |
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ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH);
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st->regs[ADF4350_REG4] =
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ADF4350_REG4_FEEDBACK_FUND |
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ADF4350_REG4_RF_DIV_SEL(st->r4_rf_div_sel) |
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ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(band_sel_div) |
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ADF4350_REG4_RF_OUT_EN |
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(pdata->r4_user_settings &
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(ADF4350_REG4_OUTPUT_PWR(0x3) |
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ADF4350_REG4_AUX_OUTPUT_PWR(0x3) |
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ADF4350_REG4_AUX_OUTPUT_EN |
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ADF4350_REG4_AUX_OUTPUT_FUND |
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ADF4350_REG4_MUTE_TILL_LOCK_EN));
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st->regs[ADF4350_REG5] = ADF4350_REG5_LD_PIN_MODE_DIGITAL;
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st->freq_req = freq;
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return adf4350_sync_config(st);
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}
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static ssize_t adf4350_write(struct iio_dev *indio_dev,
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uintptr_t private,
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const struct iio_chan_spec *chan,
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const char *buf, size_t len)
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{
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struct adf4350_state *st = iio_priv(indio_dev);
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unsigned long long readin;
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unsigned long tmp;
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int ret;
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ret = kstrtoull(buf, 10, &readin);
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if (ret)
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return ret;
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mutex_lock(&st->lock);
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switch ((u32)private) {
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case ADF4350_FREQ:
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ret = adf4350_set_freq(st, readin);
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break;
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case ADF4350_FREQ_REFIN:
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if (readin > ADF4350_MAX_FREQ_REFIN) {
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ret = -EINVAL;
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break;
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}
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if (st->clk) {
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tmp = clk_round_rate(st->clk, readin);
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if (tmp != readin) {
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ret = -EINVAL;
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break;
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}
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ret = clk_set_rate(st->clk, tmp);
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if (ret < 0)
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break;
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}
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st->clkin = readin;
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ret = adf4350_set_freq(st, st->freq_req);
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break;
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case ADF4350_FREQ_RESOLUTION:
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if (readin == 0)
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ret = -EINVAL;
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else
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st->chspc = readin;
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break;
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case ADF4350_PWRDOWN:
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if (readin)
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st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
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else
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st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN;
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adf4350_sync_config(st);
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break;
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default:
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ret = -EINVAL;
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}
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mutex_unlock(&st->lock);
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return ret ? ret : len;
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}
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static ssize_t adf4350_read(struct iio_dev *indio_dev,
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uintptr_t private,
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const struct iio_chan_spec *chan,
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char *buf)
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{
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struct adf4350_state *st = iio_priv(indio_dev);
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unsigned long long val;
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int ret = 0;
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mutex_lock(&st->lock);
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switch ((u32)private) {
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case ADF4350_FREQ:
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val = (u64)((st->r0_int * st->r1_mod) + st->r0_fract) *
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(u64)st->fpfd;
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do_div(val, st->r1_mod * (1 << st->r4_rf_div_sel));
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/* PLL unlocked? return error */
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if (st->lock_detect_gpiod)
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if (!gpiod_get_value(st->lock_detect_gpiod)) {
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dev_dbg(&st->spi->dev, "PLL un-locked\n");
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ret = -EBUSY;
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}
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break;
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case ADF4350_FREQ_REFIN:
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if (st->clk)
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st->clkin = clk_get_rate(st->clk);
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val = st->clkin;
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break;
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case ADF4350_FREQ_RESOLUTION:
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val = st->chspc;
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break;
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case ADF4350_PWRDOWN:
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val = !!(st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN);
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break;
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default:
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ret = -EINVAL;
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val = 0;
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}
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mutex_unlock(&st->lock);
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return ret < 0 ? ret : sprintf(buf, "%llu\n", val);
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}
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#define _ADF4350_EXT_INFO(_name, _ident) { \
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.name = _name, \
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.read = adf4350_read, \
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.write = adf4350_write, \
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.private = _ident, \
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.shared = IIO_SEPARATE, \
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}
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static const struct iio_chan_spec_ext_info adf4350_ext_info[] = {
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/* Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are
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* values > 2^32 in order to support the entire frequency range
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* in Hz. Using scale is a bit ugly.
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*/
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_ADF4350_EXT_INFO("frequency", ADF4350_FREQ),
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_ADF4350_EXT_INFO("frequency_resolution", ADF4350_FREQ_RESOLUTION),
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_ADF4350_EXT_INFO("refin_frequency", ADF4350_FREQ_REFIN),
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_ADF4350_EXT_INFO("powerdown", ADF4350_PWRDOWN),
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{ },
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};
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static const struct iio_chan_spec adf4350_chan = {
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.type = IIO_ALTVOLTAGE,
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.indexed = 1,
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.output = 1,
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.ext_info = adf4350_ext_info,
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};
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static const struct iio_info adf4350_info = {
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.debugfs_reg_access = &adf4350_reg_access,
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};
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static struct adf4350_platform_data *adf4350_parse_dt(struct device *dev)
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{
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struct adf4350_platform_data *pdata;
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unsigned int tmp;
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pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
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if (!pdata)
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return NULL;
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snprintf(pdata->name, sizeof(pdata->name), "%pfw", dev_fwnode(dev));
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tmp = 10000;
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device_property_read_u32(dev, "adi,channel-spacing", &tmp);
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pdata->channel_spacing = tmp;
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tmp = 0;
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device_property_read_u32(dev, "adi,power-up-frequency", &tmp);
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pdata->power_up_frequency = tmp;
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tmp = 0;
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device_property_read_u32(dev, "adi,reference-div-factor", &tmp);
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pdata->ref_div_factor = tmp;
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pdata->ref_doubler_en = device_property_read_bool(dev, "adi,reference-doubler-enable");
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pdata->ref_div2_en = device_property_read_bool(dev, "adi,reference-div2-enable");
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/* r2_user_settings */
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pdata->r2_user_settings = 0;
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if (device_property_read_bool(dev, "adi,phase-detector-polarity-positive-enable"))
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pdata->r2_user_settings |= ADF4350_REG2_PD_POLARITY_POS;
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if (device_property_read_bool(dev, "adi,lock-detect-precision-6ns-enable"))
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pdata->r2_user_settings |= ADF4350_REG2_LDP_6ns;
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if (device_property_read_bool(dev, "adi,lock-detect-function-integer-n-enable"))
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pdata->r2_user_settings |= ADF4350_REG2_LDF_INT_N;
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tmp = 2500;
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device_property_read_u32(dev, "adi,charge-pump-current", &tmp);
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pdata->r2_user_settings |= ADF4350_REG2_CHARGE_PUMP_CURR_uA(tmp);
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tmp = 0;
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device_property_read_u32(dev, "adi,muxout-select", &tmp);
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pdata->r2_user_settings |= ADF4350_REG2_MUXOUT(tmp);
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if (device_property_read_bool(dev, "adi,low-spur-mode-enable"))
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pdata->r2_user_settings |= ADF4350_REG2_NOISE_MODE(0x3);
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/* r3_user_settings */
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pdata->r3_user_settings = 0;
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if (device_property_read_bool(dev, "adi,cycle-slip-reduction-enable"))
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pdata->r3_user_settings |= ADF4350_REG3_12BIT_CSR_EN;
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if (device_property_read_bool(dev, "adi,charge-cancellation-enable"))
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pdata->r3_user_settings |= ADF4351_REG3_CHARGE_CANCELLATION_EN;
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if (device_property_read_bool(dev, "adi,anti-backlash-3ns-enable"))
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pdata->r3_user_settings |= ADF4351_REG3_ANTI_BACKLASH_3ns_EN;
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if (device_property_read_bool(dev, "adi,band-select-clock-mode-high-enable"))
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pdata->r3_user_settings |= ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH;
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tmp = 0;
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device_property_read_u32(dev, "adi,12bit-clk-divider", &tmp);
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pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV(tmp);
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tmp = 0;
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device_property_read_u32(dev, "adi,clk-divider-mode", &tmp);
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pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV_MODE(tmp);
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/* r4_user_settings */
|
|
|
|
pdata->r4_user_settings = 0;
|
|
if (device_property_read_bool(dev, "adi,aux-output-enable"))
|
|
pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_EN;
|
|
if (device_property_read_bool(dev, "adi,aux-output-fundamental-enable"))
|
|
pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_FUND;
|
|
if (device_property_read_bool(dev, "adi,mute-till-lock-enable"))
|
|
pdata->r4_user_settings |= ADF4350_REG4_MUTE_TILL_LOCK_EN;
|
|
|
|
tmp = 0;
|
|
device_property_read_u32(dev, "adi,output-power", &tmp);
|
|
pdata->r4_user_settings |= ADF4350_REG4_OUTPUT_PWR(tmp);
|
|
|
|
tmp = 0;
|
|
device_property_read_u32(dev, "adi,aux-output-power", &tmp);
|
|
pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_PWR(tmp);
|
|
|
|
return pdata;
|
|
}
|
|
|
|
static int adf4350_probe(struct spi_device *spi)
|
|
{
|
|
struct adf4350_platform_data *pdata;
|
|
struct iio_dev *indio_dev;
|
|
struct adf4350_state *st;
|
|
struct clk *clk = NULL;
|
|
int ret;
|
|
|
|
if (dev_fwnode(&spi->dev)) {
|
|
pdata = adf4350_parse_dt(&spi->dev);
|
|
if (pdata == NULL)
|
|
return -EINVAL;
|
|
} else {
|
|
pdata = spi->dev.platform_data;
|
|
}
|
|
|
|
if (!pdata) {
|
|
dev_warn(&spi->dev, "no platform data? using default\n");
|
|
pdata = &default_pdata;
|
|
}
|
|
|
|
if (!pdata->clkin) {
|
|
clk = devm_clk_get(&spi->dev, "clkin");
|
|
if (IS_ERR(clk))
|
|
return -EPROBE_DEFER;
|
|
|
|
ret = clk_prepare_enable(clk);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
|
|
if (indio_dev == NULL) {
|
|
ret = -ENOMEM;
|
|
goto error_disable_clk;
|
|
}
|
|
|
|
st = iio_priv(indio_dev);
|
|
|
|
st->reg = devm_regulator_get(&spi->dev, "vcc");
|
|
if (!IS_ERR(st->reg)) {
|
|
ret = regulator_enable(st->reg);
|
|
if (ret)
|
|
goto error_disable_clk;
|
|
}
|
|
|
|
spi_set_drvdata(spi, indio_dev);
|
|
st->spi = spi;
|
|
st->pdata = pdata;
|
|
|
|
indio_dev->name = (pdata->name[0] != 0) ? pdata->name :
|
|
spi_get_device_id(spi)->name;
|
|
|
|
indio_dev->info = &adf4350_info;
|
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
|
indio_dev->channels = &adf4350_chan;
|
|
indio_dev->num_channels = 1;
|
|
|
|
mutex_init(&st->lock);
|
|
|
|
st->chspc = pdata->channel_spacing;
|
|
if (clk) {
|
|
st->clk = clk;
|
|
st->clkin = clk_get_rate(clk);
|
|
} else {
|
|
st->clkin = pdata->clkin;
|
|
}
|
|
|
|
st->min_out_freq = spi_get_device_id(spi)->driver_data == 4351 ?
|
|
ADF4351_MIN_OUT_FREQ : ADF4350_MIN_OUT_FREQ;
|
|
|
|
memset(st->regs_hw, 0xFF, sizeof(st->regs_hw));
|
|
|
|
st->lock_detect_gpiod = devm_gpiod_get_optional(&spi->dev, NULL,
|
|
GPIOD_IN);
|
|
if (IS_ERR(st->lock_detect_gpiod)) {
|
|
ret = PTR_ERR(st->lock_detect_gpiod);
|
|
goto error_disable_reg;
|
|
}
|
|
|
|
if (pdata->power_up_frequency) {
|
|
ret = adf4350_set_freq(st, pdata->power_up_frequency);
|
|
if (ret)
|
|
goto error_disable_reg;
|
|
}
|
|
|
|
ret = iio_device_register(indio_dev);
|
|
if (ret)
|
|
goto error_disable_reg;
|
|
|
|
return 0;
|
|
|
|
error_disable_reg:
|
|
if (!IS_ERR(st->reg))
|
|
regulator_disable(st->reg);
|
|
error_disable_clk:
|
|
clk_disable_unprepare(clk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void adf4350_remove(struct spi_device *spi)
|
|
{
|
|
struct iio_dev *indio_dev = spi_get_drvdata(spi);
|
|
struct adf4350_state *st = iio_priv(indio_dev);
|
|
struct regulator *reg = st->reg;
|
|
|
|
st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
|
|
adf4350_sync_config(st);
|
|
|
|
iio_device_unregister(indio_dev);
|
|
|
|
clk_disable_unprepare(st->clk);
|
|
|
|
if (!IS_ERR(reg))
|
|
regulator_disable(reg);
|
|
}
|
|
|
|
static const struct of_device_id adf4350_of_match[] = {
|
|
{ .compatible = "adi,adf4350", },
|
|
{ .compatible = "adi,adf4351", },
|
|
{ /* sentinel */ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, adf4350_of_match);
|
|
|
|
static const struct spi_device_id adf4350_id[] = {
|
|
{"adf4350", 4350},
|
|
{"adf4351", 4351},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(spi, adf4350_id);
|
|
|
|
static struct spi_driver adf4350_driver = {
|
|
.driver = {
|
|
.name = "adf4350",
|
|
.of_match_table = adf4350_of_match,
|
|
},
|
|
.probe = adf4350_probe,
|
|
.remove = adf4350_remove,
|
|
.id_table = adf4350_id,
|
|
};
|
|
module_spi_driver(adf4350_driver);
|
|
|
|
MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
|
|
MODULE_DESCRIPTION("Analog Devices ADF4350/ADF4351 PLL");
|
|
MODULE_LICENSE("GPL v2");
|