1023 lines
24 KiB
C
1023 lines
24 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
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/*
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* Copyright 2018-2023 Amazon.com, Inc. or its affiliates. All rights reserved.
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*/
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#ifndef _EFA_ADMIN_CMDS_H_
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#define _EFA_ADMIN_CMDS_H_
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#define EFA_ADMIN_API_VERSION_MAJOR 0
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#define EFA_ADMIN_API_VERSION_MINOR 1
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/* EFA admin queue opcodes */
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enum efa_admin_aq_opcode {
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EFA_ADMIN_CREATE_QP = 1,
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EFA_ADMIN_MODIFY_QP = 2,
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EFA_ADMIN_QUERY_QP = 3,
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EFA_ADMIN_DESTROY_QP = 4,
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EFA_ADMIN_CREATE_AH = 5,
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EFA_ADMIN_DESTROY_AH = 6,
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EFA_ADMIN_REG_MR = 7,
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EFA_ADMIN_DEREG_MR = 8,
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EFA_ADMIN_CREATE_CQ = 9,
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EFA_ADMIN_DESTROY_CQ = 10,
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EFA_ADMIN_GET_FEATURE = 11,
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EFA_ADMIN_SET_FEATURE = 12,
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EFA_ADMIN_GET_STATS = 13,
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EFA_ADMIN_ALLOC_PD = 14,
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EFA_ADMIN_DEALLOC_PD = 15,
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EFA_ADMIN_ALLOC_UAR = 16,
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EFA_ADMIN_DEALLOC_UAR = 17,
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EFA_ADMIN_CREATE_EQ = 18,
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EFA_ADMIN_DESTROY_EQ = 19,
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EFA_ADMIN_MAX_OPCODE = 19,
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};
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enum efa_admin_aq_feature_id {
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EFA_ADMIN_DEVICE_ATTR = 1,
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EFA_ADMIN_AENQ_CONFIG = 2,
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EFA_ADMIN_NETWORK_ATTR = 3,
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EFA_ADMIN_QUEUE_ATTR = 4,
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EFA_ADMIN_HW_HINTS = 5,
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EFA_ADMIN_HOST_INFO = 6,
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EFA_ADMIN_EVENT_QUEUE_ATTR = 7,
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};
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/* QP transport type */
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enum efa_admin_qp_type {
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/* Unreliable Datagram */
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EFA_ADMIN_QP_TYPE_UD = 1,
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/* Scalable Reliable Datagram */
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EFA_ADMIN_QP_TYPE_SRD = 2,
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};
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/* QP state */
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enum efa_admin_qp_state {
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EFA_ADMIN_QP_STATE_RESET = 0,
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EFA_ADMIN_QP_STATE_INIT = 1,
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EFA_ADMIN_QP_STATE_RTR = 2,
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EFA_ADMIN_QP_STATE_RTS = 3,
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EFA_ADMIN_QP_STATE_SQD = 4,
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EFA_ADMIN_QP_STATE_SQE = 5,
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EFA_ADMIN_QP_STATE_ERR = 6,
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};
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enum efa_admin_get_stats_type {
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EFA_ADMIN_GET_STATS_TYPE_BASIC = 0,
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EFA_ADMIN_GET_STATS_TYPE_MESSAGES = 1,
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EFA_ADMIN_GET_STATS_TYPE_RDMA_READ = 2,
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};
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enum efa_admin_get_stats_scope {
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EFA_ADMIN_GET_STATS_SCOPE_ALL = 0,
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EFA_ADMIN_GET_STATS_SCOPE_QUEUE = 1,
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};
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/*
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* QP allocation sizes, converted by fabric QueuePair (QP) create command
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* from QP capabilities.
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*/
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struct efa_admin_qp_alloc_size {
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/* Send descriptor ring size in bytes */
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u32 send_queue_ring_size;
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/* Max number of WQEs that can be outstanding on send queue. */
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u32 send_queue_depth;
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/*
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* Recv descriptor ring size in bytes, sufficient for user-provided
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* number of WQEs
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*/
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u32 recv_queue_ring_size;
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/* Max number of WQEs that can be outstanding on recv queue */
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u32 recv_queue_depth;
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};
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struct efa_admin_create_qp_cmd {
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/* Common Admin Queue descriptor */
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struct efa_admin_aq_common_desc aq_common_desc;
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/* Protection Domain associated with this QP */
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u16 pd;
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/* QP type */
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u8 qp_type;
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/*
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* 0 : sq_virt - If set, SQ ring base address is
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* virtual (IOVA returned by MR registration)
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* 1 : rq_virt - If set, RQ ring base address is
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* virtual (IOVA returned by MR registration)
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* 7:2 : reserved - MBZ
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*/
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u8 flags;
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/*
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* Send queue (SQ) ring base physical address. This field is not
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* used if this is a Low Latency Queue(LLQ).
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*/
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u64 sq_base_addr;
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/* Receive queue (RQ) ring base address. */
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u64 rq_base_addr;
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/* Index of CQ to be associated with Send Queue completions */
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u32 send_cq_idx;
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/* Index of CQ to be associated with Recv Queue completions */
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u32 recv_cq_idx;
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/*
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* Memory registration key for the SQ ring, used only when not in
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* LLQ mode and base address is virtual
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*/
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u32 sq_l_key;
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/*
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* Memory registration key for the RQ ring, used only when base
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* address is virtual
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*/
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u32 rq_l_key;
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/* Requested QP allocation sizes */
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struct efa_admin_qp_alloc_size qp_alloc_size;
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/* UAR number */
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u16 uar;
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/* MBZ */
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u16 reserved;
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/* MBZ */
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u32 reserved2;
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};
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struct efa_admin_create_qp_resp {
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/* Common Admin Queue completion descriptor */
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struct efa_admin_acq_common_desc acq_common_desc;
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/*
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* Opaque handle to be used for consequent admin operations on the
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* QP
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*/
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u32 qp_handle;
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/*
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* QP number in the given EFA virtual device. Least-significant bits (as
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* needed according to max_qp) carry unique QP ID
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*/
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u16 qp_num;
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/* MBZ */
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u16 reserved;
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/* Index of sub-CQ for Send Queue completions */
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u16 send_sub_cq_idx;
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/* Index of sub-CQ for Receive Queue completions */
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u16 recv_sub_cq_idx;
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/* SQ doorbell address, as offset to PCIe DB BAR */
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u32 sq_db_offset;
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/* RQ doorbell address, as offset to PCIe DB BAR */
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u32 rq_db_offset;
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/*
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* low latency send queue ring base address as an offset to PCIe
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* MMIO LLQ_MEM BAR
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*/
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u32 llq_descriptors_offset;
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};
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struct efa_admin_modify_qp_cmd {
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/* Common Admin Queue descriptor */
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struct efa_admin_aq_common_desc aq_common_desc;
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/*
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* Mask indicating which fields should be updated
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* 0 : qp_state
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* 1 : cur_qp_state
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* 2 : qkey
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* 3 : sq_psn
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* 4 : sq_drained_async_notify
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* 5 : rnr_retry
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* 31:6 : reserved
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*/
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u32 modify_mask;
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/* QP handle returned by create_qp command */
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u32 qp_handle;
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/* QP state */
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u32 qp_state;
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/* Override current QP state (before applying the transition) */
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u32 cur_qp_state;
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/* QKey */
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u32 qkey;
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/* SQ PSN */
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u32 sq_psn;
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/* Enable async notification when SQ is drained */
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u8 sq_drained_async_notify;
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/* Number of RNR retries (valid only for SRD QPs) */
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u8 rnr_retry;
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/* MBZ */
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u16 reserved2;
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};
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struct efa_admin_modify_qp_resp {
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/* Common Admin Queue completion descriptor */
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struct efa_admin_acq_common_desc acq_common_desc;
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};
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struct efa_admin_query_qp_cmd {
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/* Common Admin Queue descriptor */
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struct efa_admin_aq_common_desc aq_common_desc;
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/* QP handle returned by create_qp command */
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u32 qp_handle;
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};
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struct efa_admin_query_qp_resp {
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/* Common Admin Queue completion descriptor */
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struct efa_admin_acq_common_desc acq_common_desc;
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/* QP state */
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u32 qp_state;
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/* QKey */
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u32 qkey;
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/* SQ PSN */
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u32 sq_psn;
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/* Indicates that draining is in progress */
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u8 sq_draining;
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/* Number of RNR retries (valid only for SRD QPs) */
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u8 rnr_retry;
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/* MBZ */
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u16 reserved2;
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};
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struct efa_admin_destroy_qp_cmd {
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/* Common Admin Queue descriptor */
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struct efa_admin_aq_common_desc aq_common_desc;
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/* QP handle returned by create_qp command */
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u32 qp_handle;
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};
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struct efa_admin_destroy_qp_resp {
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/* Common Admin Queue completion descriptor */
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struct efa_admin_acq_common_desc acq_common_desc;
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};
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/*
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* Create Address Handle command parameters. Must not be called more than
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* once for the same destination
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*/
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struct efa_admin_create_ah_cmd {
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/* Common Admin Queue descriptor */
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struct efa_admin_aq_common_desc aq_common_desc;
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/* Destination address in network byte order */
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u8 dest_addr[16];
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/* PD number */
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u16 pd;
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/* MBZ */
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u16 reserved;
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};
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struct efa_admin_create_ah_resp {
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/* Common Admin Queue completion descriptor */
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struct efa_admin_acq_common_desc acq_common_desc;
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/* Target interface address handle (opaque) */
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u16 ah;
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/* MBZ */
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u16 reserved;
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};
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struct efa_admin_destroy_ah_cmd {
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/* Common Admin Queue descriptor */
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struct efa_admin_aq_common_desc aq_common_desc;
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/* Target interface address handle (opaque) */
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u16 ah;
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/* PD number */
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u16 pd;
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};
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struct efa_admin_destroy_ah_resp {
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/* Common Admin Queue completion descriptor */
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struct efa_admin_acq_common_desc acq_common_desc;
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};
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/*
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* Registration of MemoryRegion, required for QP working with Virtual
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* Addresses. In standard verbs semantics, region length is limited to 2GB
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* space, but EFA offers larger MR support for large memory space, to ease
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* on users working with very large datasets (i.e. full GPU memory mapping).
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*/
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struct efa_admin_reg_mr_cmd {
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/* Common Admin Queue descriptor */
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struct efa_admin_aq_common_desc aq_common_desc;
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/* Protection Domain */
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u16 pd;
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/* MBZ */
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u16 reserved16_w1;
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/* Physical Buffer List, each element is page-aligned. */
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union {
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/*
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* Inline array of guest-physical page addresses of user
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* memory pages (optimization for short region
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* registrations)
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*/
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u64 inline_pbl_array[4];
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/* points to PBL (direct or indirect, chained if needed) */
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struct efa_admin_ctrl_buff_info pbl;
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} pbl;
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/* Memory region length, in bytes. */
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u64 mr_length;
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/*
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* flags and page size
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* 4:0 : phys_page_size_shift - page size is (1 <<
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* phys_page_size_shift). Page size is used for
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* building the Virtual to Physical address mapping
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* 6:5 : reserved - MBZ
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* 7 : mem_addr_phy_mode_en - Enable bit for physical
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* memory registration (no translation), can be used
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* only by privileged clients. If set, PBL must
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* contain a single entry.
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*/
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u8 flags;
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/*
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* permissions
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* 0 : local_write_enable - Local write permissions:
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* must be set for RQ buffers and buffers posted for
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* RDMA Read requests
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* 1 : remote_write_enable - Remote write
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* permissions: must be set to enable RDMA write to
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* the region
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* 2 : remote_read_enable - Remote read permissions:
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* must be set to enable RDMA read from the region
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* 7:3 : reserved2 - MBZ
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*/
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u8 permissions;
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/* MBZ */
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u16 reserved16_w5;
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/* number of pages in PBL (redundant, could be calculated) */
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u32 page_num;
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/*
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* IO Virtual Address associated with this MR. If
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* mem_addr_phy_mode_en is set, contains the physical address of
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* the region.
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*/
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u64 iova;
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};
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struct efa_admin_reg_mr_resp {
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/* Common Admin Queue completion descriptor */
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struct efa_admin_acq_common_desc acq_common_desc;
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/*
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* L_Key, to be used in conjunction with local buffer references in
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* SQ and RQ WQE, or with virtual RQ/CQ rings
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*/
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u32 l_key;
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/*
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* R_Key, to be used in RDMA messages to refer to remotely accessed
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* memory region
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*/
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u32 r_key;
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};
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struct efa_admin_dereg_mr_cmd {
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/* Common Admin Queue descriptor */
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struct efa_admin_aq_common_desc aq_common_desc;
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/* L_Key, memory region's l_key */
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u32 l_key;
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};
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struct efa_admin_dereg_mr_resp {
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/* Common Admin Queue completion descriptor */
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struct efa_admin_acq_common_desc acq_common_desc;
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};
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struct efa_admin_create_cq_cmd {
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struct efa_admin_aq_common_desc aq_common_desc;
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/*
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* 4:0 : reserved5 - MBZ
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* 5 : interrupt_mode_enabled - if set, cq operates
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* in interrupt mode (i.e. CQ events and EQ elements
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* are generated), otherwise - polling
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* 6 : virt - If set, ring base address is virtual
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* (IOVA returned by MR registration)
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* 7 : reserved6 - MBZ
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*/
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u8 cq_caps_1;
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/*
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* 4:0 : cq_entry_size_words - size of CQ entry in
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* 32-bit words, valid values: 4, 8.
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* 5 : set_src_addr - If set, source address will be
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* filled on RX completions from unknown senders.
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* Requires 8 words CQ entry size.
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* 7:6 : reserved7 - MBZ
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*/
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u8 cq_caps_2;
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/* completion queue depth in # of entries. must be power of 2 */
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u16 cq_depth;
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/* EQ number assigned to this cq */
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u16 eqn;
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/* MBZ */
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u16 reserved;
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/*
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* CQ ring base address, virtual or physical depending on 'virt'
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* flag
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*/
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struct efa_common_mem_addr cq_ba;
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/*
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* Memory registration key for the ring, used only when base
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* address is virtual
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*/
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u32 l_key;
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/*
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* number of sub cqs - must be equal to sub_cqs_per_cq of queue
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* attributes.
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*/
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u16 num_sub_cqs;
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/* UAR number */
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u16 uar;
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};
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struct efa_admin_create_cq_resp {
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struct efa_admin_acq_common_desc acq_common_desc;
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u16 cq_idx;
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/* actual cq depth in number of entries */
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u16 cq_actual_depth;
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/* CQ doorbell address, as offset to PCIe DB BAR */
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u32 db_offset;
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/*
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* 0 : db_valid - If set, doorbell offset is valid.
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* Always set when interrupts are requested.
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*/
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u32 flags;
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};
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struct efa_admin_destroy_cq_cmd {
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struct efa_admin_aq_common_desc aq_common_desc;
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u16 cq_idx;
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/* MBZ */
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u16 reserved1;
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};
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struct efa_admin_destroy_cq_resp {
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struct efa_admin_acq_common_desc acq_common_desc;
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};
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/*
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* EFA AQ Get Statistics command. Extended statistics are placed in control
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* buffer pointed by AQ entry
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*/
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struct efa_admin_aq_get_stats_cmd {
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struct efa_admin_aq_common_desc aq_common_descriptor;
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union {
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/* command specific inline data */
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u32 inline_data_w1[3];
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struct efa_admin_ctrl_buff_info control_buffer;
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} u;
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/* stats type as defined in enum efa_admin_get_stats_type */
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u8 type;
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/* stats scope defined in enum efa_admin_get_stats_scope */
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u8 scope;
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u16 scope_modifier;
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};
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struct efa_admin_basic_stats {
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u64 tx_bytes;
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u64 tx_pkts;
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u64 rx_bytes;
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u64 rx_pkts;
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u64 rx_drops;
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};
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struct efa_admin_messages_stats {
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u64 send_bytes;
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u64 send_wrs;
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u64 recv_bytes;
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u64 recv_wrs;
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};
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struct efa_admin_rdma_read_stats {
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u64 read_wrs;
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u64 read_bytes;
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u64 read_wr_err;
|
|
|
|
u64 read_resp_bytes;
|
|
};
|
|
|
|
struct efa_admin_acq_get_stats_resp {
|
|
struct efa_admin_acq_common_desc acq_common_desc;
|
|
|
|
union {
|
|
struct efa_admin_basic_stats basic_stats;
|
|
|
|
struct efa_admin_messages_stats messages_stats;
|
|
|
|
struct efa_admin_rdma_read_stats rdma_read_stats;
|
|
} u;
|
|
};
|
|
|
|
struct efa_admin_get_set_feature_common_desc {
|
|
/* MBZ */
|
|
u8 reserved0;
|
|
|
|
/* as appears in efa_admin_aq_feature_id */
|
|
u8 feature_id;
|
|
|
|
/* MBZ */
|
|
u16 reserved16;
|
|
};
|
|
|
|
struct efa_admin_feature_device_attr_desc {
|
|
/* Bitmap of efa_admin_aq_feature_id */
|
|
u64 supported_features;
|
|
|
|
/* Bitmap of supported page sizes in MR registrations */
|
|
u64 page_size_cap;
|
|
|
|
u32 fw_version;
|
|
|
|
u32 admin_api_version;
|
|
|
|
u32 device_version;
|
|
|
|
/* Bar used for SQ and RQ doorbells */
|
|
u16 db_bar;
|
|
|
|
/* Indicates how many bits are used on physical address access */
|
|
u8 phys_addr_width;
|
|
|
|
/* Indicates how many bits are used on virtual address access */
|
|
u8 virt_addr_width;
|
|
|
|
/*
|
|
* 0 : rdma_read - If set, RDMA Read is supported on
|
|
* TX queues
|
|
* 1 : rnr_retry - If set, RNR retry is supported on
|
|
* modify QP command
|
|
* 2 : data_polling_128 - If set, 128 bytes data
|
|
* polling is supported
|
|
* 3 : rdma_write - If set, RDMA Write is supported
|
|
* on TX queues
|
|
* 31:4 : reserved - MBZ
|
|
*/
|
|
u32 device_caps;
|
|
|
|
/* Max RDMA transfer size in bytes */
|
|
u32 max_rdma_size;
|
|
};
|
|
|
|
struct efa_admin_feature_queue_attr_desc {
|
|
/* The maximum number of queue pairs supported */
|
|
u32 max_qp;
|
|
|
|
/* Maximum number of WQEs per Send Queue */
|
|
u32 max_sq_depth;
|
|
|
|
/* Maximum size of data that can be sent inline in a Send WQE */
|
|
u32 inline_buf_size;
|
|
|
|
/* Maximum number of buffer descriptors per Recv Queue */
|
|
u32 max_rq_depth;
|
|
|
|
/* The maximum number of completion queues supported per VF */
|
|
u32 max_cq;
|
|
|
|
/* Maximum number of CQEs per Completion Queue */
|
|
u32 max_cq_depth;
|
|
|
|
/* Number of sub-CQs to be created for each CQ */
|
|
u16 sub_cqs_per_cq;
|
|
|
|
/* Minimum number of WQEs per SQ */
|
|
u16 min_sq_depth;
|
|
|
|
/* Maximum number of SGEs (buffers) allowed for a single send WQE */
|
|
u16 max_wr_send_sges;
|
|
|
|
/* Maximum number of SGEs allowed for a single recv WQE */
|
|
u16 max_wr_recv_sges;
|
|
|
|
/* The maximum number of memory regions supported */
|
|
u32 max_mr;
|
|
|
|
/* The maximum number of pages can be registered */
|
|
u32 max_mr_pages;
|
|
|
|
/* The maximum number of protection domains supported */
|
|
u32 max_pd;
|
|
|
|
/* The maximum number of address handles supported */
|
|
u32 max_ah;
|
|
|
|
/* The maximum size of LLQ in bytes */
|
|
u32 max_llq_size;
|
|
|
|
/* Maximum number of SGEs for a single RDMA read/write WQE */
|
|
u16 max_wr_rdma_sges;
|
|
|
|
/*
|
|
* Maximum number of bytes that can be written to SQ between two
|
|
* consecutive doorbells (in units of 64B). Driver must ensure that only
|
|
* complete WQEs are written to queue before issuing a doorbell.
|
|
* Examples: max_tx_batch=16 and WQE size = 64B, means up to 16 WQEs can
|
|
* be written to SQ between two consecutive doorbells. max_tx_batch=11
|
|
* and WQE size = 128B, means up to 5 WQEs can be written to SQ between
|
|
* two consecutive doorbells. Zero means unlimited.
|
|
*/
|
|
u16 max_tx_batch;
|
|
};
|
|
|
|
struct efa_admin_event_queue_attr_desc {
|
|
/* The maximum number of event queues supported */
|
|
u32 max_eq;
|
|
|
|
/* Maximum number of EQEs per Event Queue */
|
|
u32 max_eq_depth;
|
|
|
|
/* Supported events bitmask */
|
|
u32 event_bitmask;
|
|
};
|
|
|
|
struct efa_admin_feature_aenq_desc {
|
|
/* bitmask for AENQ groups the device can report */
|
|
u32 supported_groups;
|
|
|
|
/* bitmask for AENQ groups to report */
|
|
u32 enabled_groups;
|
|
};
|
|
|
|
struct efa_admin_feature_network_attr_desc {
|
|
/* Raw address data in network byte order */
|
|
u8 addr[16];
|
|
|
|
/* max packet payload size in bytes */
|
|
u32 mtu;
|
|
};
|
|
|
|
/*
|
|
* When hint value is 0, hints capabilities are not supported or driver
|
|
* should use its own predefined value
|
|
*/
|
|
struct efa_admin_hw_hints {
|
|
/* value in ms */
|
|
u16 mmio_read_timeout;
|
|
|
|
/* value in ms */
|
|
u16 driver_watchdog_timeout;
|
|
|
|
/* value in ms */
|
|
u16 admin_completion_timeout;
|
|
|
|
/* poll interval in ms */
|
|
u16 poll_interval;
|
|
};
|
|
|
|
struct efa_admin_get_feature_cmd {
|
|
struct efa_admin_aq_common_desc aq_common_descriptor;
|
|
|
|
struct efa_admin_ctrl_buff_info control_buffer;
|
|
|
|
struct efa_admin_get_set_feature_common_desc feature_common;
|
|
|
|
u32 raw[11];
|
|
};
|
|
|
|
struct efa_admin_get_feature_resp {
|
|
struct efa_admin_acq_common_desc acq_common_desc;
|
|
|
|
union {
|
|
u32 raw[14];
|
|
|
|
struct efa_admin_feature_device_attr_desc device_attr;
|
|
|
|
struct efa_admin_feature_aenq_desc aenq;
|
|
|
|
struct efa_admin_feature_network_attr_desc network_attr;
|
|
|
|
struct efa_admin_feature_queue_attr_desc queue_attr;
|
|
|
|
struct efa_admin_event_queue_attr_desc event_queue_attr;
|
|
|
|
struct efa_admin_hw_hints hw_hints;
|
|
} u;
|
|
};
|
|
|
|
struct efa_admin_set_feature_cmd {
|
|
struct efa_admin_aq_common_desc aq_common_descriptor;
|
|
|
|
struct efa_admin_ctrl_buff_info control_buffer;
|
|
|
|
struct efa_admin_get_set_feature_common_desc feature_common;
|
|
|
|
union {
|
|
u32 raw[11];
|
|
|
|
/* AENQ configuration */
|
|
struct efa_admin_feature_aenq_desc aenq;
|
|
} u;
|
|
};
|
|
|
|
struct efa_admin_set_feature_resp {
|
|
struct efa_admin_acq_common_desc acq_common_desc;
|
|
|
|
union {
|
|
u32 raw[14];
|
|
} u;
|
|
};
|
|
|
|
struct efa_admin_alloc_pd_cmd {
|
|
struct efa_admin_aq_common_desc aq_common_descriptor;
|
|
};
|
|
|
|
struct efa_admin_alloc_pd_resp {
|
|
struct efa_admin_acq_common_desc acq_common_desc;
|
|
|
|
/* PD number */
|
|
u16 pd;
|
|
|
|
/* MBZ */
|
|
u16 reserved;
|
|
};
|
|
|
|
struct efa_admin_dealloc_pd_cmd {
|
|
struct efa_admin_aq_common_desc aq_common_descriptor;
|
|
|
|
/* PD number */
|
|
u16 pd;
|
|
|
|
/* MBZ */
|
|
u16 reserved;
|
|
};
|
|
|
|
struct efa_admin_dealloc_pd_resp {
|
|
struct efa_admin_acq_common_desc acq_common_desc;
|
|
};
|
|
|
|
struct efa_admin_alloc_uar_cmd {
|
|
struct efa_admin_aq_common_desc aq_common_descriptor;
|
|
};
|
|
|
|
struct efa_admin_alloc_uar_resp {
|
|
struct efa_admin_acq_common_desc acq_common_desc;
|
|
|
|
/* UAR number */
|
|
u16 uar;
|
|
|
|
/* MBZ */
|
|
u16 reserved;
|
|
};
|
|
|
|
struct efa_admin_dealloc_uar_cmd {
|
|
struct efa_admin_aq_common_desc aq_common_descriptor;
|
|
|
|
/* UAR number */
|
|
u16 uar;
|
|
|
|
/* MBZ */
|
|
u16 reserved;
|
|
};
|
|
|
|
struct efa_admin_dealloc_uar_resp {
|
|
struct efa_admin_acq_common_desc acq_common_desc;
|
|
};
|
|
|
|
struct efa_admin_create_eq_cmd {
|
|
struct efa_admin_aq_common_desc aq_common_descriptor;
|
|
|
|
/* Size of the EQ in entries, must be power of 2 */
|
|
u16 depth;
|
|
|
|
/* MSI-X table entry index */
|
|
u8 msix_vec;
|
|
|
|
/*
|
|
* 4:0 : entry_size_words - size of EQ entry in
|
|
* 32-bit words
|
|
* 7:5 : reserved - MBZ
|
|
*/
|
|
u8 caps;
|
|
|
|
/* EQ ring base address */
|
|
struct efa_common_mem_addr ba;
|
|
|
|
/*
|
|
* Enabled events on this EQ
|
|
* 0 : completion_events - Enable completion events
|
|
* 31:1 : reserved - MBZ
|
|
*/
|
|
u32 event_bitmask;
|
|
|
|
/* MBZ */
|
|
u32 reserved;
|
|
};
|
|
|
|
struct efa_admin_create_eq_resp {
|
|
struct efa_admin_acq_common_desc acq_common_desc;
|
|
|
|
/* EQ number */
|
|
u16 eqn;
|
|
|
|
/* MBZ */
|
|
u16 reserved;
|
|
};
|
|
|
|
struct efa_admin_destroy_eq_cmd {
|
|
struct efa_admin_aq_common_desc aq_common_descriptor;
|
|
|
|
/* EQ number */
|
|
u16 eqn;
|
|
|
|
/* MBZ */
|
|
u16 reserved;
|
|
};
|
|
|
|
struct efa_admin_destroy_eq_resp {
|
|
struct efa_admin_acq_common_desc acq_common_desc;
|
|
};
|
|
|
|
/* asynchronous event notification groups */
|
|
enum efa_admin_aenq_group {
|
|
EFA_ADMIN_FATAL_ERROR = 1,
|
|
EFA_ADMIN_WARNING = 2,
|
|
EFA_ADMIN_NOTIFICATION = 3,
|
|
EFA_ADMIN_KEEP_ALIVE = 4,
|
|
EFA_ADMIN_AENQ_GROUPS_NUM = 5,
|
|
};
|
|
|
|
struct efa_admin_mmio_req_read_less_resp {
|
|
u16 req_id;
|
|
|
|
u16 reg_off;
|
|
|
|
/* value is valid when poll is cleared */
|
|
u32 reg_val;
|
|
};
|
|
|
|
enum efa_admin_os_type {
|
|
EFA_ADMIN_OS_LINUX = 0,
|
|
};
|
|
|
|
struct efa_admin_host_info {
|
|
/* OS distribution string format */
|
|
u8 os_dist_str[128];
|
|
|
|
/* Defined in enum efa_admin_os_type */
|
|
u32 os_type;
|
|
|
|
/* Kernel version string format */
|
|
u8 kernel_ver_str[32];
|
|
|
|
/* Kernel version numeric format */
|
|
u32 kernel_ver;
|
|
|
|
/*
|
|
* 7:0 : driver_module_type
|
|
* 15:8 : driver_sub_minor
|
|
* 23:16 : driver_minor
|
|
* 31:24 : driver_major
|
|
*/
|
|
u32 driver_ver;
|
|
|
|
/*
|
|
* Device's Bus, Device and Function
|
|
* 2:0 : function
|
|
* 7:3 : device
|
|
* 15:8 : bus
|
|
*/
|
|
u16 bdf;
|
|
|
|
/*
|
|
* Spec version
|
|
* 7:0 : spec_minor
|
|
* 15:8 : spec_major
|
|
*/
|
|
u16 spec_ver;
|
|
|
|
/*
|
|
* 0 : intree - Intree driver
|
|
* 1 : gdr - GPUDirect RDMA supported
|
|
* 31:2 : reserved2
|
|
*/
|
|
u32 flags;
|
|
};
|
|
|
|
/* create_qp_cmd */
|
|
#define EFA_ADMIN_CREATE_QP_CMD_SQ_VIRT_MASK BIT(0)
|
|
#define EFA_ADMIN_CREATE_QP_CMD_RQ_VIRT_MASK BIT(1)
|
|
|
|
/* modify_qp_cmd */
|
|
#define EFA_ADMIN_MODIFY_QP_CMD_QP_STATE_MASK BIT(0)
|
|
#define EFA_ADMIN_MODIFY_QP_CMD_CUR_QP_STATE_MASK BIT(1)
|
|
#define EFA_ADMIN_MODIFY_QP_CMD_QKEY_MASK BIT(2)
|
|
#define EFA_ADMIN_MODIFY_QP_CMD_SQ_PSN_MASK BIT(3)
|
|
#define EFA_ADMIN_MODIFY_QP_CMD_SQ_DRAINED_ASYNC_NOTIFY_MASK BIT(4)
|
|
#define EFA_ADMIN_MODIFY_QP_CMD_RNR_RETRY_MASK BIT(5)
|
|
|
|
/* reg_mr_cmd */
|
|
#define EFA_ADMIN_REG_MR_CMD_PHYS_PAGE_SIZE_SHIFT_MASK GENMASK(4, 0)
|
|
#define EFA_ADMIN_REG_MR_CMD_MEM_ADDR_PHY_MODE_EN_MASK BIT(7)
|
|
#define EFA_ADMIN_REG_MR_CMD_LOCAL_WRITE_ENABLE_MASK BIT(0)
|
|
#define EFA_ADMIN_REG_MR_CMD_REMOTE_WRITE_ENABLE_MASK BIT(1)
|
|
#define EFA_ADMIN_REG_MR_CMD_REMOTE_READ_ENABLE_MASK BIT(2)
|
|
|
|
/* create_cq_cmd */
|
|
#define EFA_ADMIN_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
|
|
#define EFA_ADMIN_CREATE_CQ_CMD_VIRT_MASK BIT(6)
|
|
#define EFA_ADMIN_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
|
|
#define EFA_ADMIN_CREATE_CQ_CMD_SET_SRC_ADDR_MASK BIT(5)
|
|
|
|
/* create_cq_resp */
|
|
#define EFA_ADMIN_CREATE_CQ_RESP_DB_VALID_MASK BIT(0)
|
|
|
|
/* feature_device_attr_desc */
|
|
#define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_RDMA_READ_MASK BIT(0)
|
|
#define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_RNR_RETRY_MASK BIT(1)
|
|
#define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_DATA_POLLING_128_MASK BIT(2)
|
|
#define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_RDMA_WRITE_MASK BIT(3)
|
|
|
|
/* create_eq_cmd */
|
|
#define EFA_ADMIN_CREATE_EQ_CMD_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
|
|
#define EFA_ADMIN_CREATE_EQ_CMD_VIRT_MASK BIT(6)
|
|
#define EFA_ADMIN_CREATE_EQ_CMD_COMPLETION_EVENTS_MASK BIT(0)
|
|
|
|
/* host_info */
|
|
#define EFA_ADMIN_HOST_INFO_DRIVER_MODULE_TYPE_MASK GENMASK(7, 0)
|
|
#define EFA_ADMIN_HOST_INFO_DRIVER_SUB_MINOR_MASK GENMASK(15, 8)
|
|
#define EFA_ADMIN_HOST_INFO_DRIVER_MINOR_MASK GENMASK(23, 16)
|
|
#define EFA_ADMIN_HOST_INFO_DRIVER_MAJOR_MASK GENMASK(31, 24)
|
|
#define EFA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)
|
|
#define EFA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)
|
|
#define EFA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)
|
|
#define EFA_ADMIN_HOST_INFO_SPEC_MINOR_MASK GENMASK(7, 0)
|
|
#define EFA_ADMIN_HOST_INFO_SPEC_MAJOR_MASK GENMASK(15, 8)
|
|
#define EFA_ADMIN_HOST_INFO_INTREE_MASK BIT(0)
|
|
#define EFA_ADMIN_HOST_INFO_GDR_MASK BIT(1)
|
|
|
|
#endif /* _EFA_ADMIN_CMDS_H_ */
|