486 lines
14 KiB
C
486 lines
14 KiB
C
/*
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* Copyright (c) 2013-2017, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/debugfs.h>
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#include "mlx5_ib.h"
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#include "cmd.h"
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enum mlx5_ib_cong_node_type {
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MLX5_IB_RROCE_ECN_RP = 1,
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MLX5_IB_RROCE_ECN_NP = 2,
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MLX5_IB_RROCE_GENERAL = 3,
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};
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static const char * const mlx5_ib_dbg_cc_name[] = {
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"rp_clamp_tgt_rate",
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"rp_clamp_tgt_rate_ati",
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"rp_time_reset",
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"rp_byte_reset",
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"rp_threshold",
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"rp_ai_rate",
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"rp_max_rate",
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"rp_hai_rate",
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"rp_min_dec_fac",
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"rp_min_rate",
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"rp_rate_to_set_on_first_cnp",
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"rp_dce_tcp_g",
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"rp_dce_tcp_rtt",
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"rp_rate_reduce_monitor_period",
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"rp_initial_alpha_value",
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"rp_gd",
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"np_min_time_between_cnps",
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"np_cnp_dscp",
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"np_cnp_prio_mode",
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"np_cnp_prio",
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"rtt_resp_dscp_valid",
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"rtt_resp_dscp",
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};
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#define MLX5_IB_RP_CLAMP_TGT_RATE_ATTR BIT(1)
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#define MLX5_IB_RP_CLAMP_TGT_RATE_ATI_ATTR BIT(2)
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#define MLX5_IB_RP_TIME_RESET_ATTR BIT(3)
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#define MLX5_IB_RP_BYTE_RESET_ATTR BIT(4)
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#define MLX5_IB_RP_THRESHOLD_ATTR BIT(5)
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#define MLX5_IB_RP_MAX_RATE_ATTR BIT(6)
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#define MLX5_IB_RP_AI_RATE_ATTR BIT(7)
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#define MLX5_IB_RP_HAI_RATE_ATTR BIT(8)
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#define MLX5_IB_RP_MIN_DEC_FAC_ATTR BIT(9)
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#define MLX5_IB_RP_MIN_RATE_ATTR BIT(10)
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#define MLX5_IB_RP_RATE_TO_SET_ON_FIRST_CNP_ATTR BIT(11)
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#define MLX5_IB_RP_DCE_TCP_G_ATTR BIT(12)
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#define MLX5_IB_RP_DCE_TCP_RTT_ATTR BIT(13)
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#define MLX5_IB_RP_RATE_REDUCE_MONITOR_PERIOD_ATTR BIT(14)
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#define MLX5_IB_RP_INITIAL_ALPHA_VALUE_ATTR BIT(15)
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#define MLX5_IB_RP_GD_ATTR BIT(16)
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#define MLX5_IB_NP_MIN_TIME_BETWEEN_CNPS_ATTR BIT(2)
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#define MLX5_IB_NP_CNP_DSCP_ATTR BIT(3)
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#define MLX5_IB_NP_CNP_PRIO_MODE_ATTR BIT(4)
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#define MLX5_IB_GENERAL_RTT_RESP_DSCP_ATTR BIT(0)
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static enum mlx5_ib_cong_node_type
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mlx5_ib_param_to_node(enum mlx5_ib_dbg_cc_types param_offset)
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{
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if (param_offset <= MLX5_IB_DBG_CC_RP_GD)
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return MLX5_IB_RROCE_ECN_RP;
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if (param_offset <= MLX5_IB_DBG_CC_NP_CNP_PRIO)
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return MLX5_IB_RROCE_ECN_NP;
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return MLX5_IB_RROCE_GENERAL;
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}
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static u32 mlx5_get_cc_param_val(void *field, int offset)
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{
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switch (offset) {
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case MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE:
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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clamp_tgt_rate);
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case MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI:
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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clamp_tgt_rate_after_time_inc);
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case MLX5_IB_DBG_CC_RP_TIME_RESET:
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rpg_time_reset);
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case MLX5_IB_DBG_CC_RP_BYTE_RESET:
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rpg_byte_reset);
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case MLX5_IB_DBG_CC_RP_THRESHOLD:
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rpg_threshold);
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case MLX5_IB_DBG_CC_RP_AI_RATE:
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rpg_ai_rate);
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case MLX5_IB_DBG_CC_RP_MAX_RATE:
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rpg_max_rate);
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case MLX5_IB_DBG_CC_RP_HAI_RATE:
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rpg_hai_rate);
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case MLX5_IB_DBG_CC_RP_MIN_DEC_FAC:
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rpg_min_dec_fac);
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case MLX5_IB_DBG_CC_RP_MIN_RATE:
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rpg_min_rate);
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case MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP:
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rate_to_set_on_first_cnp);
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case MLX5_IB_DBG_CC_RP_DCE_TCP_G:
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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dce_tcp_g);
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case MLX5_IB_DBG_CC_RP_DCE_TCP_RTT:
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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dce_tcp_rtt);
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case MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD:
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rate_reduce_monitor_period);
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case MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE:
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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initial_alpha_value);
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case MLX5_IB_DBG_CC_RP_GD:
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return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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rpg_gd);
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case MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS:
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return MLX5_GET(cong_control_r_roce_ecn_np, field,
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min_time_between_cnps);
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case MLX5_IB_DBG_CC_NP_CNP_DSCP:
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return MLX5_GET(cong_control_r_roce_ecn_np, field,
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cnp_dscp);
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case MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE:
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return MLX5_GET(cong_control_r_roce_ecn_np, field,
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cnp_prio_mode);
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case MLX5_IB_DBG_CC_NP_CNP_PRIO:
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return MLX5_GET(cong_control_r_roce_ecn_np, field,
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cnp_802p_prio);
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case MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP_VALID:
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return MLX5_GET(cong_control_r_roce_general, field,
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rtt_resp_dscp_valid);
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case MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP:
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return MLX5_GET(cong_control_r_roce_general, field,
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rtt_resp_dscp);
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default:
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return 0;
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}
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}
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static void mlx5_ib_set_cc_param_mask_val(void *field, int offset,
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u32 var, u32 *attr_mask)
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{
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switch (offset) {
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case MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE:
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*attr_mask |= MLX5_IB_RP_CLAMP_TGT_RATE_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_rp, field,
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clamp_tgt_rate, var);
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break;
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case MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI:
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*attr_mask |= MLX5_IB_RP_CLAMP_TGT_RATE_ATI_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_rp, field,
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clamp_tgt_rate_after_time_inc, var);
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break;
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case MLX5_IB_DBG_CC_RP_TIME_RESET:
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*attr_mask |= MLX5_IB_RP_TIME_RESET_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_rp, field,
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rpg_time_reset, var);
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break;
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case MLX5_IB_DBG_CC_RP_BYTE_RESET:
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*attr_mask |= MLX5_IB_RP_BYTE_RESET_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_rp, field,
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rpg_byte_reset, var);
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break;
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case MLX5_IB_DBG_CC_RP_THRESHOLD:
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*attr_mask |= MLX5_IB_RP_THRESHOLD_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_rp, field,
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rpg_threshold, var);
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break;
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case MLX5_IB_DBG_CC_RP_AI_RATE:
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*attr_mask |= MLX5_IB_RP_AI_RATE_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_rp, field,
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rpg_ai_rate, var);
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break;
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case MLX5_IB_DBG_CC_RP_MAX_RATE:
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*attr_mask |= MLX5_IB_RP_MAX_RATE_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_rp, field,
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rpg_max_rate, var);
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break;
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case MLX5_IB_DBG_CC_RP_HAI_RATE:
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*attr_mask |= MLX5_IB_RP_HAI_RATE_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_rp, field,
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rpg_hai_rate, var);
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break;
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case MLX5_IB_DBG_CC_RP_MIN_DEC_FAC:
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*attr_mask |= MLX5_IB_RP_MIN_DEC_FAC_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_rp, field,
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rpg_min_dec_fac, var);
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break;
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case MLX5_IB_DBG_CC_RP_MIN_RATE:
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*attr_mask |= MLX5_IB_RP_MIN_RATE_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_rp, field,
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rpg_min_rate, var);
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break;
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case MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP:
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*attr_mask |= MLX5_IB_RP_RATE_TO_SET_ON_FIRST_CNP_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_rp, field,
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rate_to_set_on_first_cnp, var);
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break;
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case MLX5_IB_DBG_CC_RP_DCE_TCP_G:
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*attr_mask |= MLX5_IB_RP_DCE_TCP_G_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_rp, field,
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dce_tcp_g, var);
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break;
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case MLX5_IB_DBG_CC_RP_DCE_TCP_RTT:
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*attr_mask |= MLX5_IB_RP_DCE_TCP_RTT_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_rp, field,
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dce_tcp_rtt, var);
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break;
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case MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD:
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*attr_mask |= MLX5_IB_RP_RATE_REDUCE_MONITOR_PERIOD_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_rp, field,
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rate_reduce_monitor_period, var);
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break;
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case MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE:
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*attr_mask |= MLX5_IB_RP_INITIAL_ALPHA_VALUE_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_rp, field,
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initial_alpha_value, var);
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break;
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case MLX5_IB_DBG_CC_RP_GD:
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*attr_mask |= MLX5_IB_RP_GD_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_rp, field,
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rpg_gd, var);
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break;
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case MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS:
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*attr_mask |= MLX5_IB_NP_MIN_TIME_BETWEEN_CNPS_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_np, field,
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min_time_between_cnps, var);
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break;
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case MLX5_IB_DBG_CC_NP_CNP_DSCP:
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*attr_mask |= MLX5_IB_NP_CNP_DSCP_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_np, field, cnp_dscp, var);
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break;
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case MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE:
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*attr_mask |= MLX5_IB_NP_CNP_PRIO_MODE_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_np, field, cnp_prio_mode, var);
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break;
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case MLX5_IB_DBG_CC_NP_CNP_PRIO:
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*attr_mask |= MLX5_IB_NP_CNP_PRIO_MODE_ATTR;
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MLX5_SET(cong_control_r_roce_ecn_np, field, cnp_prio_mode, 0);
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MLX5_SET(cong_control_r_roce_ecn_np, field, cnp_802p_prio, var);
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break;
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case MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP_VALID:
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*attr_mask |= MLX5_IB_GENERAL_RTT_RESP_DSCP_ATTR;
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MLX5_SET(cong_control_r_roce_general, field, rtt_resp_dscp_valid, var);
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break;
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case MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP:
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*attr_mask |= MLX5_IB_GENERAL_RTT_RESP_DSCP_ATTR;
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MLX5_SET(cong_control_r_roce_general, field, rtt_resp_dscp_valid, 1);
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MLX5_SET(cong_control_r_roce_general, field, rtt_resp_dscp, var);
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break;
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}
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}
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static int mlx5_ib_get_cc_params(struct mlx5_ib_dev *dev, u32 port_num,
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int offset, u32 *var)
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{
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int outlen = MLX5_ST_SZ_BYTES(query_cong_params_out);
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void *out;
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void *field;
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int err;
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enum mlx5_ib_cong_node_type node;
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struct mlx5_core_dev *mdev;
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/* Takes a 1-based port number */
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mdev = mlx5_ib_get_native_port_mdev(dev, port_num + 1, NULL);
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if (!mdev)
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return -ENODEV;
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out = kvzalloc(outlen, GFP_KERNEL);
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if (!out) {
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err = -ENOMEM;
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goto alloc_err;
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}
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node = mlx5_ib_param_to_node(offset);
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err = mlx5_cmd_query_cong_params(mdev, node, out);
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if (err)
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goto free;
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field = MLX5_ADDR_OF(query_cong_params_out, out, congestion_parameters);
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*var = mlx5_get_cc_param_val(field, offset);
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free:
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kvfree(out);
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alloc_err:
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mlx5_ib_put_native_port_mdev(dev, port_num + 1);
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return err;
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}
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static int mlx5_ib_set_cc_params(struct mlx5_ib_dev *dev, u32 port_num,
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int offset, u32 var)
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{
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int inlen = MLX5_ST_SZ_BYTES(modify_cong_params_in);
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void *in;
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void *field;
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enum mlx5_ib_cong_node_type node;
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struct mlx5_core_dev *mdev;
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u32 attr_mask = 0;
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int err;
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/* Takes a 1-based port number */
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mdev = mlx5_ib_get_native_port_mdev(dev, port_num + 1, NULL);
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if (!mdev)
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return -ENODEV;
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in = kvzalloc(inlen, GFP_KERNEL);
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if (!in) {
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err = -ENOMEM;
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goto alloc_err;
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}
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MLX5_SET(modify_cong_params_in, in, opcode,
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MLX5_CMD_OP_MODIFY_CONG_PARAMS);
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node = mlx5_ib_param_to_node(offset);
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MLX5_SET(modify_cong_params_in, in, cong_protocol, node);
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field = MLX5_ADDR_OF(modify_cong_params_in, in, congestion_parameters);
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mlx5_ib_set_cc_param_mask_val(field, offset, var, &attr_mask);
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field = MLX5_ADDR_OF(modify_cong_params_in, in, field_select);
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MLX5_SET(field_select_r_roce_rp, field, field_select_r_roce_rp,
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attr_mask);
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err = mlx5_cmd_exec_in(dev->mdev, modify_cong_params, in);
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kvfree(in);
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alloc_err:
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mlx5_ib_put_native_port_mdev(dev, port_num + 1);
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return err;
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}
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static ssize_t set_param(struct file *filp, const char __user *buf,
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size_t count, loff_t *pos)
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{
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struct mlx5_ib_dbg_param *param = filp->private_data;
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int offset = param->offset;
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char lbuf[11] = { };
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u32 var;
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int ret;
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if (count > sizeof(lbuf))
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return -EINVAL;
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if (copy_from_user(lbuf, buf, count))
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return -EFAULT;
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lbuf[sizeof(lbuf) - 1] = '\0';
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if (kstrtou32(lbuf, 0, &var))
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return -EINVAL;
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ret = mlx5_ib_set_cc_params(param->dev, param->port_num, offset, var);
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return ret ? ret : count;
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}
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static ssize_t get_param(struct file *filp, char __user *buf, size_t count,
|
|
loff_t *pos)
|
|
{
|
|
struct mlx5_ib_dbg_param *param = filp->private_data;
|
|
int offset = param->offset;
|
|
u32 var = 0;
|
|
int ret;
|
|
char lbuf[11];
|
|
|
|
ret = mlx5_ib_get_cc_params(param->dev, param->port_num, offset, &var);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = snprintf(lbuf, sizeof(lbuf), "%d\n", var);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return simple_read_from_buffer(buf, count, pos, lbuf, ret);
|
|
}
|
|
|
|
static const struct file_operations dbg_cc_fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = simple_open,
|
|
.write = set_param,
|
|
.read = get_param,
|
|
};
|
|
|
|
void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num)
|
|
{
|
|
if (!mlx5_debugfs_root ||
|
|
!dev->port[port_num].dbg_cc_params ||
|
|
!dev->port[port_num].dbg_cc_params->root)
|
|
return;
|
|
|
|
debugfs_remove_recursive(dev->port[port_num].dbg_cc_params->root);
|
|
kfree(dev->port[port_num].dbg_cc_params);
|
|
dev->port[port_num].dbg_cc_params = NULL;
|
|
}
|
|
|
|
void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num)
|
|
{
|
|
struct mlx5_ib_dbg_cc_params *dbg_cc_params;
|
|
struct mlx5_core_dev *mdev;
|
|
int i;
|
|
|
|
if (!mlx5_debugfs_root)
|
|
return;
|
|
|
|
/* Takes a 1-based port number */
|
|
mdev = mlx5_ib_get_native_port_mdev(dev, port_num + 1, NULL);
|
|
if (!mdev)
|
|
return;
|
|
|
|
if (!MLX5_CAP_GEN(mdev, cc_query_allowed) ||
|
|
!MLX5_CAP_GEN(mdev, cc_modify_allowed))
|
|
goto put_mdev;
|
|
|
|
dbg_cc_params = kzalloc(sizeof(*dbg_cc_params), GFP_KERNEL);
|
|
if (!dbg_cc_params)
|
|
goto err;
|
|
|
|
dev->port[port_num].dbg_cc_params = dbg_cc_params;
|
|
|
|
dbg_cc_params->root = debugfs_create_dir("cc_params", mlx5_debugfs_get_dev_root(mdev));
|
|
|
|
for (i = 0; i < MLX5_IB_DBG_CC_MAX; i++) {
|
|
dbg_cc_params->params[i].offset = i;
|
|
dbg_cc_params->params[i].dev = dev;
|
|
dbg_cc_params->params[i].port_num = port_num;
|
|
dbg_cc_params->params[i].dentry =
|
|
debugfs_create_file(mlx5_ib_dbg_cc_name[i],
|
|
0600, dbg_cc_params->root,
|
|
&dbg_cc_params->params[i],
|
|
&dbg_cc_fops);
|
|
}
|
|
|
|
put_mdev:
|
|
mlx5_ib_put_native_port_mdev(dev, port_num + 1);
|
|
return;
|
|
|
|
err:
|
|
mlx5_ib_warn(dev, "cong debugfs failure\n");
|
|
mlx5_ib_cleanup_cong_debugfs(dev, port_num);
|
|
mlx5_ib_put_native_port_mdev(dev, port_num + 1);
|
|
|
|
/*
|
|
* We don't want to fail driver if debugfs failed to initialize,
|
|
* so we are not forwarding error to the user.
|
|
*/
|
|
return;
|
|
}
|