253 lines
6.2 KiB
C
253 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Driver for UniPhier AIDET (ARM Interrupt Detector)
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*
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* Copyright (C) 2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <linux/bitops.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#define UNIPHIER_AIDET_NR_IRQS 256
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#define UNIPHIER_AIDET_DETCONF 0x04 /* inverter register base */
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struct uniphier_aidet_priv {
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struct irq_domain *domain;
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void __iomem *reg_base;
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spinlock_t lock;
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u32 saved_vals[UNIPHIER_AIDET_NR_IRQS / 32];
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};
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static void uniphier_aidet_reg_update(struct uniphier_aidet_priv *priv,
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unsigned int reg, u32 mask, u32 val)
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{
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unsigned long flags;
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u32 tmp;
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spin_lock_irqsave(&priv->lock, flags);
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tmp = readl_relaxed(priv->reg_base + reg);
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tmp &= ~mask;
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tmp |= mask & val;
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writel_relaxed(tmp, priv->reg_base + reg);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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static void uniphier_aidet_detconf_update(struct uniphier_aidet_priv *priv,
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unsigned long index, unsigned int val)
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{
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unsigned int reg;
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u32 mask;
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reg = UNIPHIER_AIDET_DETCONF + index / 32 * 4;
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mask = BIT(index % 32);
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uniphier_aidet_reg_update(priv, reg, mask, val ? mask : 0);
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}
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static int uniphier_aidet_irq_set_type(struct irq_data *data, unsigned int type)
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{
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struct uniphier_aidet_priv *priv = data->chip_data;
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unsigned int val;
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/* enable inverter for active low triggers */
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_LEVEL_HIGH:
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val = 0;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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val = 1;
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type = IRQ_TYPE_EDGE_RISING;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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val = 1;
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type = IRQ_TYPE_LEVEL_HIGH;
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break;
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default:
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return -EINVAL;
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}
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uniphier_aidet_detconf_update(priv, data->hwirq, val);
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return irq_chip_set_type_parent(data, type);
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}
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static struct irq_chip uniphier_aidet_irq_chip = {
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.name = "AIDET",
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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.irq_set_type = uniphier_aidet_irq_set_type,
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};
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static int uniphier_aidet_domain_translate(struct irq_domain *domain,
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struct irq_fwspec *fwspec,
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unsigned long *out_hwirq,
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unsigned int *out_type)
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{
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if (WARN_ON(fwspec->param_count < 2))
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return -EINVAL;
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*out_hwirq = fwspec->param[0];
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*out_type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
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return 0;
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}
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static int uniphier_aidet_domain_alloc(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs,
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void *arg)
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{
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struct irq_fwspec parent_fwspec;
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irq_hw_number_t hwirq;
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unsigned int type;
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int ret;
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if (nr_irqs != 1)
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return -EINVAL;
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ret = uniphier_aidet_domain_translate(domain, arg, &hwirq, &type);
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if (ret)
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return ret;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_LEVEL_HIGH:
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break;
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case IRQ_TYPE_EDGE_FALLING:
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type = IRQ_TYPE_EDGE_RISING;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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type = IRQ_TYPE_LEVEL_HIGH;
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break;
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default:
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return -EINVAL;
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}
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if (hwirq >= UNIPHIER_AIDET_NR_IRQS)
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return -ENXIO;
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ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
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&uniphier_aidet_irq_chip,
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domain->host_data);
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if (ret)
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return ret;
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/* parent is GIC */
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parent_fwspec.fwnode = domain->parent->fwnode;
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parent_fwspec.param_count = 3;
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parent_fwspec.param[0] = 0; /* SPI */
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parent_fwspec.param[1] = hwirq;
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parent_fwspec.param[2] = type;
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return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
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}
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static const struct irq_domain_ops uniphier_aidet_domain_ops = {
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.alloc = uniphier_aidet_domain_alloc,
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.free = irq_domain_free_irqs_common,
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.translate = uniphier_aidet_domain_translate,
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};
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static int uniphier_aidet_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *parent_np;
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struct irq_domain *parent_domain;
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struct uniphier_aidet_priv *priv;
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parent_np = of_irq_find_parent(dev->of_node);
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if (!parent_np)
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return -ENXIO;
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parent_domain = irq_find_host(parent_np);
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of_node_put(parent_np);
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if (!parent_domain)
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return -EPROBE_DEFER;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->reg_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->reg_base))
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return PTR_ERR(priv->reg_base);
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spin_lock_init(&priv->lock);
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priv->domain = irq_domain_create_hierarchy(
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parent_domain, 0,
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UNIPHIER_AIDET_NR_IRQS,
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of_node_to_fwnode(dev->of_node),
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&uniphier_aidet_domain_ops, priv);
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if (!priv->domain)
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return -ENOMEM;
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platform_set_drvdata(pdev, priv);
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return 0;
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}
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static int __maybe_unused uniphier_aidet_suspend(struct device *dev)
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{
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struct uniphier_aidet_priv *priv = dev_get_drvdata(dev);
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int i;
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for (i = 0; i < ARRAY_SIZE(priv->saved_vals); i++)
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priv->saved_vals[i] = readl_relaxed(
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priv->reg_base + UNIPHIER_AIDET_DETCONF + i * 4);
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return 0;
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}
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static int __maybe_unused uniphier_aidet_resume(struct device *dev)
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{
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struct uniphier_aidet_priv *priv = dev_get_drvdata(dev);
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int i;
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for (i = 0; i < ARRAY_SIZE(priv->saved_vals); i++)
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writel_relaxed(priv->saved_vals[i],
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priv->reg_base + UNIPHIER_AIDET_DETCONF + i * 4);
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return 0;
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}
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static const struct dev_pm_ops uniphier_aidet_pm_ops = {
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(uniphier_aidet_suspend,
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uniphier_aidet_resume)
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};
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static const struct of_device_id uniphier_aidet_match[] = {
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{ .compatible = "socionext,uniphier-ld4-aidet" },
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{ .compatible = "socionext,uniphier-pro4-aidet" },
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{ .compatible = "socionext,uniphier-sld8-aidet" },
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{ .compatible = "socionext,uniphier-pro5-aidet" },
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{ .compatible = "socionext,uniphier-pxs2-aidet" },
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{ .compatible = "socionext,uniphier-ld11-aidet" },
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{ .compatible = "socionext,uniphier-ld20-aidet" },
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{ .compatible = "socionext,uniphier-pxs3-aidet" },
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{ .compatible = "socionext,uniphier-nx1-aidet" },
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{ /* sentinel */ }
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};
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static struct platform_driver uniphier_aidet_driver = {
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.probe = uniphier_aidet_probe,
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.driver = {
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.name = "uniphier-aidet",
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.of_match_table = uniphier_aidet_match,
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.pm = &uniphier_aidet_pm_ops,
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},
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};
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builtin_platform_driver(uniphier_aidet_driver);
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