818 lines
18 KiB
C
818 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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Driver for M88RS2000 demodulator and tuner
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Copyright (C) 2012 Malcolm Priestley (tvboxspy@gmail.com)
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Beta Driver
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Include various calculation code from DS3000 driver.
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Copyright (C) 2009 Konstantin Dimitrov.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/jiffies.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <media/dvb_frontend.h>
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#include "m88rs2000.h"
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struct m88rs2000_state {
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struct i2c_adapter *i2c;
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const struct m88rs2000_config *config;
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struct dvb_frontend frontend;
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u8 no_lock_count;
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u32 tuner_frequency;
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u32 symbol_rate;
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enum fe_code_rate fec_inner;
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u8 tuner_level;
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int errmode;
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};
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static int m88rs2000_debug;
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module_param_named(debug, m88rs2000_debug, int, 0644);
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MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able)).");
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#define dprintk(level, args...) do { \
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if (level & m88rs2000_debug) \
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printk(KERN_DEBUG "m88rs2000-fe: " args); \
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} while (0)
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#define deb_info(args...) dprintk(0x01, args)
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#define info(format, arg...) \
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printk(KERN_INFO "m88rs2000-fe: " format "\n" , ## arg)
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static int m88rs2000_writereg(struct m88rs2000_state *state,
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u8 reg, u8 data)
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{
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int ret;
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u8 buf[] = { reg, data };
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struct i2c_msg msg = {
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.addr = state->config->demod_addr,
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.flags = 0,
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.buf = buf,
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.len = 2
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};
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ret = i2c_transfer(state->i2c, &msg, 1);
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if (ret != 1)
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deb_info("%s: writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
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__func__, reg, data, ret);
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return (ret != 1) ? -EREMOTEIO : 0;
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}
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static u8 m88rs2000_readreg(struct m88rs2000_state *state, u8 reg)
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{
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int ret;
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u8 b0[] = { reg };
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u8 b1[] = { 0 };
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struct i2c_msg msg[] = {
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{
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.addr = state->config->demod_addr,
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.flags = 0,
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.buf = b0,
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.len = 1
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}, {
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.addr = state->config->demod_addr,
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.flags = I2C_M_RD,
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.buf = b1,
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.len = 1
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}
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};
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ret = i2c_transfer(state->i2c, msg, 2);
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if (ret != 2)
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deb_info("%s: readreg error (reg == 0x%02x, ret == %i)\n",
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__func__, reg, ret);
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return b1[0];
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}
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static u32 m88rs2000_get_mclk(struct dvb_frontend *fe)
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{
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struct m88rs2000_state *state = fe->demodulator_priv;
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u32 mclk;
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u8 reg;
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/* Must not be 0x00 or 0xff */
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reg = m88rs2000_readreg(state, 0x86);
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if (!reg || reg == 0xff)
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return 0;
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reg /= 2;
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reg += 1;
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mclk = (u32)(reg * RS2000_FE_CRYSTAL_KHZ + 28 / 2) / 28;
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return mclk;
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}
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static int m88rs2000_set_carrieroffset(struct dvb_frontend *fe, s16 offset)
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{
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struct m88rs2000_state *state = fe->demodulator_priv;
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u32 mclk;
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s32 tmp;
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u8 reg;
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int ret;
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mclk = m88rs2000_get_mclk(fe);
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if (!mclk)
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return -EINVAL;
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tmp = (offset * 4096 + (s32)mclk / 2) / (s32)mclk;
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if (tmp < 0)
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tmp += 4096;
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/* Carrier Offset */
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ret = m88rs2000_writereg(state, 0x9c, (u8)(tmp >> 4));
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reg = m88rs2000_readreg(state, 0x9d);
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reg &= 0xf;
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reg |= (u8)(tmp & 0xf) << 4;
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ret |= m88rs2000_writereg(state, 0x9d, reg);
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return ret;
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}
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static int m88rs2000_set_symbolrate(struct dvb_frontend *fe, u32 srate)
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{
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struct m88rs2000_state *state = fe->demodulator_priv;
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int ret;
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u64 temp;
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u32 mclk;
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u8 b[3];
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if ((srate < 1000000) || (srate > 45000000))
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return -EINVAL;
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mclk = m88rs2000_get_mclk(fe);
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if (!mclk)
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return -EINVAL;
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temp = srate / 1000;
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temp *= 1 << 24;
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do_div(temp, mclk);
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b[0] = (u8) (temp >> 16) & 0xff;
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b[1] = (u8) (temp >> 8) & 0xff;
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b[2] = (u8) temp & 0xff;
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ret = m88rs2000_writereg(state, 0x93, b[2]);
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ret |= m88rs2000_writereg(state, 0x94, b[1]);
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ret |= m88rs2000_writereg(state, 0x95, b[0]);
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if (srate > 10000000)
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ret |= m88rs2000_writereg(state, 0xa0, 0x20);
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else
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ret |= m88rs2000_writereg(state, 0xa0, 0x60);
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ret |= m88rs2000_writereg(state, 0xa1, 0xe0);
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if (srate > 12000000)
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ret |= m88rs2000_writereg(state, 0xa3, 0x20);
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else if (srate > 2800000)
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ret |= m88rs2000_writereg(state, 0xa3, 0x98);
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else
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ret |= m88rs2000_writereg(state, 0xa3, 0x90);
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deb_info("m88rs2000: m88rs2000_set_symbolrate\n");
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return ret;
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}
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static int m88rs2000_send_diseqc_msg(struct dvb_frontend *fe,
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struct dvb_diseqc_master_cmd *m)
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{
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struct m88rs2000_state *state = fe->demodulator_priv;
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int i;
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u8 reg;
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deb_info("%s\n", __func__);
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m88rs2000_writereg(state, 0x9a, 0x30);
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reg = m88rs2000_readreg(state, 0xb2);
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reg &= 0x3f;
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m88rs2000_writereg(state, 0xb2, reg);
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for (i = 0; i < m->msg_len; i++)
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m88rs2000_writereg(state, 0xb3 + i, m->msg[i]);
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reg = m88rs2000_readreg(state, 0xb1);
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reg &= 0x87;
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reg |= ((m->msg_len - 1) << 3) | 0x07;
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reg &= 0x7f;
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m88rs2000_writereg(state, 0xb1, reg);
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for (i = 0; i < 15; i++) {
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if ((m88rs2000_readreg(state, 0xb1) & 0x40) == 0x0)
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break;
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msleep(20);
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}
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reg = m88rs2000_readreg(state, 0xb1);
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if ((reg & 0x40) > 0x0) {
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reg &= 0x7f;
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reg |= 0x40;
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m88rs2000_writereg(state, 0xb1, reg);
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}
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reg = m88rs2000_readreg(state, 0xb2);
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reg &= 0x3f;
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reg |= 0x80;
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m88rs2000_writereg(state, 0xb2, reg);
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m88rs2000_writereg(state, 0x9a, 0xb0);
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return 0;
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}
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static int m88rs2000_send_diseqc_burst(struct dvb_frontend *fe,
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enum fe_sec_mini_cmd burst)
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{
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struct m88rs2000_state *state = fe->demodulator_priv;
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u8 reg0, reg1;
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deb_info("%s\n", __func__);
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m88rs2000_writereg(state, 0x9a, 0x30);
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msleep(50);
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reg0 = m88rs2000_readreg(state, 0xb1);
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reg1 = m88rs2000_readreg(state, 0xb2);
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/* TODO complete this section */
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m88rs2000_writereg(state, 0xb2, reg1);
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m88rs2000_writereg(state, 0xb1, reg0);
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m88rs2000_writereg(state, 0x9a, 0xb0);
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return 0;
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}
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static int m88rs2000_set_tone(struct dvb_frontend *fe,
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enum fe_sec_tone_mode tone)
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{
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struct m88rs2000_state *state = fe->demodulator_priv;
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u8 reg0, reg1;
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m88rs2000_writereg(state, 0x9a, 0x30);
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reg0 = m88rs2000_readreg(state, 0xb1);
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reg1 = m88rs2000_readreg(state, 0xb2);
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reg1 &= 0x3f;
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switch (tone) {
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case SEC_TONE_ON:
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reg0 |= 0x4;
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reg0 &= 0xbc;
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break;
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case SEC_TONE_OFF:
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reg1 |= 0x80;
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break;
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default:
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break;
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}
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m88rs2000_writereg(state, 0xb2, reg1);
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m88rs2000_writereg(state, 0xb1, reg0);
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m88rs2000_writereg(state, 0x9a, 0xb0);
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return 0;
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}
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struct inittab {
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u8 cmd;
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u8 reg;
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u8 val;
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};
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static struct inittab m88rs2000_setup[] = {
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{DEMOD_WRITE, 0x9a, 0x30},
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{DEMOD_WRITE, 0x00, 0x01},
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{WRITE_DELAY, 0x19, 0x00},
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{DEMOD_WRITE, 0x00, 0x00},
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{DEMOD_WRITE, 0x9a, 0xb0},
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{DEMOD_WRITE, 0x81, 0xc1},
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{DEMOD_WRITE, 0x81, 0x81},
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{DEMOD_WRITE, 0x86, 0xc6},
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{DEMOD_WRITE, 0x9a, 0x30},
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{DEMOD_WRITE, 0xf0, 0x22},
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{DEMOD_WRITE, 0xf1, 0xbf},
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{DEMOD_WRITE, 0xb0, 0x45},
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{DEMOD_WRITE, 0xb2, 0x01}, /* set voltage pin always set 1*/
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{DEMOD_WRITE, 0x9a, 0xb0},
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{0xff, 0xaa, 0xff}
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};
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static struct inittab m88rs2000_shutdown[] = {
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{DEMOD_WRITE, 0x9a, 0x30},
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{DEMOD_WRITE, 0xb0, 0x00},
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{DEMOD_WRITE, 0xf1, 0x89},
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{DEMOD_WRITE, 0x00, 0x01},
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{DEMOD_WRITE, 0x9a, 0xb0},
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{DEMOD_WRITE, 0x81, 0x81},
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{0xff, 0xaa, 0xff}
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};
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static struct inittab fe_reset[] = {
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{DEMOD_WRITE, 0x00, 0x01},
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{DEMOD_WRITE, 0x20, 0x81},
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{DEMOD_WRITE, 0x21, 0x80},
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{DEMOD_WRITE, 0x10, 0x33},
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{DEMOD_WRITE, 0x11, 0x44},
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{DEMOD_WRITE, 0x12, 0x07},
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{DEMOD_WRITE, 0x18, 0x20},
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{DEMOD_WRITE, 0x28, 0x04},
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{DEMOD_WRITE, 0x29, 0x8e},
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{DEMOD_WRITE, 0x3b, 0xff},
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{DEMOD_WRITE, 0x32, 0x10},
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{DEMOD_WRITE, 0x33, 0x02},
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{DEMOD_WRITE, 0x34, 0x30},
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{DEMOD_WRITE, 0x35, 0xff},
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{DEMOD_WRITE, 0x38, 0x50},
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{DEMOD_WRITE, 0x39, 0x68},
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{DEMOD_WRITE, 0x3c, 0x7f},
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{DEMOD_WRITE, 0x3d, 0x0f},
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{DEMOD_WRITE, 0x45, 0x20},
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{DEMOD_WRITE, 0x46, 0x24},
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{DEMOD_WRITE, 0x47, 0x7c},
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{DEMOD_WRITE, 0x48, 0x16},
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{DEMOD_WRITE, 0x49, 0x04},
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{DEMOD_WRITE, 0x4a, 0x01},
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{DEMOD_WRITE, 0x4b, 0x78},
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{DEMOD_WRITE, 0X4d, 0xd2},
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{DEMOD_WRITE, 0x4e, 0x6d},
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{DEMOD_WRITE, 0x50, 0x30},
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{DEMOD_WRITE, 0x51, 0x30},
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{DEMOD_WRITE, 0x54, 0x7b},
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{DEMOD_WRITE, 0x56, 0x09},
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{DEMOD_WRITE, 0x58, 0x59},
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{DEMOD_WRITE, 0x59, 0x37},
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{DEMOD_WRITE, 0x63, 0xfa},
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{0xff, 0xaa, 0xff}
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};
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static struct inittab fe_trigger[] = {
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{DEMOD_WRITE, 0x97, 0x04},
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{DEMOD_WRITE, 0x99, 0x77},
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{DEMOD_WRITE, 0x9b, 0x64},
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{DEMOD_WRITE, 0x9e, 0x00},
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{DEMOD_WRITE, 0x9f, 0xf8},
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{DEMOD_WRITE, 0x98, 0xff},
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{DEMOD_WRITE, 0xc0, 0x0f},
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{DEMOD_WRITE, 0x89, 0x01},
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{DEMOD_WRITE, 0x00, 0x00},
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{WRITE_DELAY, 0x0a, 0x00},
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{DEMOD_WRITE, 0x00, 0x01},
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{DEMOD_WRITE, 0x00, 0x00},
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{DEMOD_WRITE, 0x9a, 0xb0},
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{0xff, 0xaa, 0xff}
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};
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static int m88rs2000_tab_set(struct m88rs2000_state *state,
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struct inittab *tab)
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{
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int ret = 0;
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u8 i;
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if (tab == NULL)
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return -EINVAL;
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for (i = 0; i < 255; i++) {
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switch (tab[i].cmd) {
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case 0x01:
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ret = m88rs2000_writereg(state, tab[i].reg,
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tab[i].val);
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break;
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case 0x10:
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if (tab[i].reg > 0)
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mdelay(tab[i].reg);
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break;
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case 0xff:
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if (tab[i].reg == 0xaa && tab[i].val == 0xff)
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return 0;
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break;
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case 0x00:
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break;
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default:
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return -EINVAL;
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}
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if (ret < 0)
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return -ENODEV;
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}
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return 0;
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}
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static int m88rs2000_set_voltage(struct dvb_frontend *fe,
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enum fe_sec_voltage volt)
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{
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struct m88rs2000_state *state = fe->demodulator_priv;
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u8 data;
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data = m88rs2000_readreg(state, 0xb2);
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data |= 0x03; /* bit0 V/H, bit1 off/on */
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switch (volt) {
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case SEC_VOLTAGE_18:
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data &= ~0x03;
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break;
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case SEC_VOLTAGE_13:
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data &= ~0x03;
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data |= 0x01;
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break;
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case SEC_VOLTAGE_OFF:
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break;
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}
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m88rs2000_writereg(state, 0xb2, data);
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return 0;
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}
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static int m88rs2000_init(struct dvb_frontend *fe)
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{
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struct m88rs2000_state *state = fe->demodulator_priv;
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int ret;
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deb_info("m88rs2000: init chip\n");
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/* Setup frontend from shutdown/cold */
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if (state->config->inittab)
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ret = m88rs2000_tab_set(state,
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(struct inittab *)state->config->inittab);
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else
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ret = m88rs2000_tab_set(state, m88rs2000_setup);
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return ret;
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}
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static int m88rs2000_sleep(struct dvb_frontend *fe)
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{
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struct m88rs2000_state *state = fe->demodulator_priv;
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int ret;
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/* Shutdown the frondend */
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ret = m88rs2000_tab_set(state, m88rs2000_shutdown);
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return ret;
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}
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static int m88rs2000_read_status(struct dvb_frontend *fe,
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enum fe_status *status)
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{
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struct m88rs2000_state *state = fe->demodulator_priv;
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u8 reg = m88rs2000_readreg(state, 0x8c);
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*status = 0;
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if ((reg & 0xee) == 0xee) {
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*status = FE_HAS_CARRIER | FE_HAS_SIGNAL | FE_HAS_VITERBI
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| FE_HAS_SYNC | FE_HAS_LOCK;
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if (state->config->set_ts_params)
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state->config->set_ts_params(fe, CALL_IS_READ);
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}
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return 0;
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}
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static int m88rs2000_read_ber(struct dvb_frontend *fe, u32 *ber)
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{
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struct m88rs2000_state *state = fe->demodulator_priv;
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u8 tmp0, tmp1;
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m88rs2000_writereg(state, 0x9a, 0x30);
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tmp0 = m88rs2000_readreg(state, 0xd8);
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if ((tmp0 & 0x10) != 0) {
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m88rs2000_writereg(state, 0x9a, 0xb0);
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*ber = 0xffffffff;
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return 0;
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}
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*ber = (m88rs2000_readreg(state, 0xd7) << 8) |
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m88rs2000_readreg(state, 0xd6);
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tmp1 = m88rs2000_readreg(state, 0xd9);
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m88rs2000_writereg(state, 0xd9, (tmp1 & ~7) | 4);
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/* needs twice */
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m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30);
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m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30);
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m88rs2000_writereg(state, 0x9a, 0xb0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int m88rs2000_read_signal_strength(struct dvb_frontend *fe,
|
|
u16 *strength)
|
|
{
|
|
if (fe->ops.tuner_ops.get_rf_strength)
|
|
fe->ops.tuner_ops.get_rf_strength(fe, strength);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int m88rs2000_read_snr(struct dvb_frontend *fe, u16 *snr)
|
|
{
|
|
struct m88rs2000_state *state = fe->demodulator_priv;
|
|
|
|
*snr = 512 * m88rs2000_readreg(state, 0x65);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int m88rs2000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
|
|
{
|
|
struct m88rs2000_state *state = fe->demodulator_priv;
|
|
u8 tmp;
|
|
|
|
*ucblocks = (m88rs2000_readreg(state, 0xd5) << 8) |
|
|
m88rs2000_readreg(state, 0xd4);
|
|
tmp = m88rs2000_readreg(state, 0xd8);
|
|
m88rs2000_writereg(state, 0xd8, tmp & ~0x20);
|
|
/* needs two times */
|
|
m88rs2000_writereg(state, 0xd8, tmp | 0x20);
|
|
m88rs2000_writereg(state, 0xd8, tmp | 0x20);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int m88rs2000_set_fec(struct m88rs2000_state *state,
|
|
enum fe_code_rate fec)
|
|
{
|
|
u8 fec_set, reg;
|
|
int ret;
|
|
|
|
switch (fec) {
|
|
case FEC_1_2:
|
|
fec_set = 0x8;
|
|
break;
|
|
case FEC_2_3:
|
|
fec_set = 0x10;
|
|
break;
|
|
case FEC_3_4:
|
|
fec_set = 0x20;
|
|
break;
|
|
case FEC_5_6:
|
|
fec_set = 0x40;
|
|
break;
|
|
case FEC_7_8:
|
|
fec_set = 0x80;
|
|
break;
|
|
case FEC_AUTO:
|
|
default:
|
|
fec_set = 0x0;
|
|
}
|
|
|
|
reg = m88rs2000_readreg(state, 0x70);
|
|
reg &= 0x7;
|
|
ret = m88rs2000_writereg(state, 0x70, reg | fec_set);
|
|
|
|
ret |= m88rs2000_writereg(state, 0x76, 0x8);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static enum fe_code_rate m88rs2000_get_fec(struct m88rs2000_state *state)
|
|
{
|
|
u8 reg;
|
|
m88rs2000_writereg(state, 0x9a, 0x30);
|
|
reg = m88rs2000_readreg(state, 0x76);
|
|
m88rs2000_writereg(state, 0x9a, 0xb0);
|
|
|
|
reg &= 0xf0;
|
|
reg >>= 5;
|
|
|
|
switch (reg) {
|
|
case 0x4:
|
|
return FEC_1_2;
|
|
case 0x3:
|
|
return FEC_2_3;
|
|
case 0x2:
|
|
return FEC_3_4;
|
|
case 0x1:
|
|
return FEC_5_6;
|
|
case 0x0:
|
|
return FEC_7_8;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return FEC_AUTO;
|
|
}
|
|
|
|
static int m88rs2000_set_frontend(struct dvb_frontend *fe)
|
|
{
|
|
struct m88rs2000_state *state = fe->demodulator_priv;
|
|
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
|
|
enum fe_status status = 0;
|
|
int i, ret = 0;
|
|
u32 tuner_freq;
|
|
s16 offset = 0;
|
|
u8 reg;
|
|
|
|
state->no_lock_count = 0;
|
|
|
|
if (c->delivery_system != SYS_DVBS) {
|
|
deb_info("%s: unsupported delivery system selected (%d)\n",
|
|
__func__, c->delivery_system);
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
/* Set Tuner */
|
|
if (fe->ops.tuner_ops.set_params)
|
|
ret = fe->ops.tuner_ops.set_params(fe);
|
|
|
|
if (ret < 0)
|
|
return -ENODEV;
|
|
|
|
if (fe->ops.tuner_ops.get_frequency) {
|
|
ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_freq);
|
|
|
|
if (ret < 0)
|
|
return -ENODEV;
|
|
|
|
offset = (s16)((s32)tuner_freq - c->frequency);
|
|
} else {
|
|
offset = 0;
|
|
}
|
|
|
|
/* default mclk value 96.4285 * 2 * 1000 = 192857 */
|
|
if (((c->frequency % 192857) >= (192857 - 3000)) ||
|
|
(c->frequency % 192857) <= 3000)
|
|
ret = m88rs2000_writereg(state, 0x86, 0xc2);
|
|
else
|
|
ret = m88rs2000_writereg(state, 0x86, 0xc6);
|
|
|
|
ret |= m88rs2000_set_carrieroffset(fe, offset);
|
|
if (ret < 0)
|
|
return -ENODEV;
|
|
|
|
/* Reset demod by symbol rate */
|
|
if (c->symbol_rate > 27500000)
|
|
ret = m88rs2000_writereg(state, 0xf1, 0xa4);
|
|
else
|
|
ret = m88rs2000_writereg(state, 0xf1, 0xbf);
|
|
|
|
ret |= m88rs2000_tab_set(state, fe_reset);
|
|
if (ret < 0)
|
|
return -ENODEV;
|
|
|
|
/* Set FEC */
|
|
ret = m88rs2000_set_fec(state, c->fec_inner);
|
|
ret |= m88rs2000_writereg(state, 0x85, 0x1);
|
|
ret |= m88rs2000_writereg(state, 0x8a, 0xbf);
|
|
ret |= m88rs2000_writereg(state, 0x8d, 0x1e);
|
|
ret |= m88rs2000_writereg(state, 0x90, 0xf1);
|
|
ret |= m88rs2000_writereg(state, 0x91, 0x08);
|
|
|
|
if (ret < 0)
|
|
return -ENODEV;
|
|
|
|
/* Set Symbol Rate */
|
|
ret = m88rs2000_set_symbolrate(fe, c->symbol_rate);
|
|
if (ret < 0)
|
|
return -ENODEV;
|
|
|
|
/* Set up Demod */
|
|
ret = m88rs2000_tab_set(state, fe_trigger);
|
|
if (ret < 0)
|
|
return -ENODEV;
|
|
|
|
for (i = 0; i < 25; i++) {
|
|
reg = m88rs2000_readreg(state, 0x8c);
|
|
if ((reg & 0xee) == 0xee) {
|
|
status = FE_HAS_LOCK;
|
|
break;
|
|
}
|
|
state->no_lock_count++;
|
|
if (state->no_lock_count == 15) {
|
|
reg = m88rs2000_readreg(state, 0x70);
|
|
reg ^= 0x4;
|
|
m88rs2000_writereg(state, 0x70, reg);
|
|
state->no_lock_count = 0;
|
|
}
|
|
msleep(20);
|
|
}
|
|
|
|
if (status & FE_HAS_LOCK) {
|
|
state->fec_inner = m88rs2000_get_fec(state);
|
|
/* Unknown suspect SNR level */
|
|
reg = m88rs2000_readreg(state, 0x65);
|
|
}
|
|
|
|
state->tuner_frequency = c->frequency;
|
|
state->symbol_rate = c->symbol_rate;
|
|
return 0;
|
|
}
|
|
|
|
static int m88rs2000_get_frontend(struct dvb_frontend *fe,
|
|
struct dtv_frontend_properties *c)
|
|
{
|
|
struct m88rs2000_state *state = fe->demodulator_priv;
|
|
|
|
c->fec_inner = state->fec_inner;
|
|
c->frequency = state->tuner_frequency;
|
|
c->symbol_rate = state->symbol_rate;
|
|
return 0;
|
|
}
|
|
|
|
static int m88rs2000_get_tune_settings(struct dvb_frontend *fe,
|
|
struct dvb_frontend_tune_settings *tune)
|
|
{
|
|
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
|
|
|
|
if (c->symbol_rate > 3000000)
|
|
tune->min_delay_ms = 2000;
|
|
else
|
|
tune->min_delay_ms = 3000;
|
|
|
|
tune->step_size = c->symbol_rate / 16000;
|
|
tune->max_drift = c->symbol_rate / 2000;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int m88rs2000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
|
|
{
|
|
struct m88rs2000_state *state = fe->demodulator_priv;
|
|
|
|
if (enable)
|
|
m88rs2000_writereg(state, 0x81, 0x84);
|
|
else
|
|
m88rs2000_writereg(state, 0x81, 0x81);
|
|
udelay(10);
|
|
return 0;
|
|
}
|
|
|
|
static void m88rs2000_release(struct dvb_frontend *fe)
|
|
{
|
|
struct m88rs2000_state *state = fe->demodulator_priv;
|
|
kfree(state);
|
|
}
|
|
|
|
static const struct dvb_frontend_ops m88rs2000_ops = {
|
|
.delsys = { SYS_DVBS },
|
|
.info = {
|
|
.name = "M88RS2000 DVB-S",
|
|
.frequency_min_hz = 950 * MHz,
|
|
.frequency_max_hz = 2150 * MHz,
|
|
.frequency_stepsize_hz = 1 * MHz,
|
|
.frequency_tolerance_hz = 5 * MHz,
|
|
.symbol_rate_min = 1000000,
|
|
.symbol_rate_max = 45000000,
|
|
.symbol_rate_tolerance = 500, /* ppm */
|
|
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
|
|
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
|
|
FE_CAN_QPSK | FE_CAN_INVERSION_AUTO |
|
|
FE_CAN_FEC_AUTO
|
|
},
|
|
|
|
.release = m88rs2000_release,
|
|
.init = m88rs2000_init,
|
|
.sleep = m88rs2000_sleep,
|
|
.i2c_gate_ctrl = m88rs2000_i2c_gate_ctrl,
|
|
.read_status = m88rs2000_read_status,
|
|
.read_ber = m88rs2000_read_ber,
|
|
.read_signal_strength = m88rs2000_read_signal_strength,
|
|
.read_snr = m88rs2000_read_snr,
|
|
.read_ucblocks = m88rs2000_read_ucblocks,
|
|
.diseqc_send_master_cmd = m88rs2000_send_diseqc_msg,
|
|
.diseqc_send_burst = m88rs2000_send_diseqc_burst,
|
|
.set_tone = m88rs2000_set_tone,
|
|
.set_voltage = m88rs2000_set_voltage,
|
|
|
|
.set_frontend = m88rs2000_set_frontend,
|
|
.get_frontend = m88rs2000_get_frontend,
|
|
.get_tune_settings = m88rs2000_get_tune_settings,
|
|
};
|
|
|
|
struct dvb_frontend *m88rs2000_attach(const struct m88rs2000_config *config,
|
|
struct i2c_adapter *i2c)
|
|
{
|
|
struct m88rs2000_state *state = NULL;
|
|
|
|
/* allocate memory for the internal state */
|
|
state = kzalloc(sizeof(struct m88rs2000_state), GFP_KERNEL);
|
|
if (state == NULL)
|
|
goto error;
|
|
|
|
/* setup the state */
|
|
state->config = config;
|
|
state->i2c = i2c;
|
|
state->tuner_frequency = 0;
|
|
state->symbol_rate = 0;
|
|
state->fec_inner = 0;
|
|
|
|
/* create dvb_frontend */
|
|
memcpy(&state->frontend.ops, &m88rs2000_ops,
|
|
sizeof(struct dvb_frontend_ops));
|
|
state->frontend.demodulator_priv = state;
|
|
return &state->frontend;
|
|
|
|
error:
|
|
kfree(state);
|
|
|
|
return NULL;
|
|
}
|
|
EXPORT_SYMBOL_GPL(m88rs2000_attach);
|
|
|
|
MODULE_DESCRIPTION("M88RS2000 DVB-S Demodulator driver");
|
|
MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_VERSION("1.13");
|
|
|