928 lines
19 KiB
C
928 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2022-2023, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <soc/tegra/mc.h>
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#include <dt-bindings/memory/tegra234-mc.h>
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#include <linux/interconnect.h>
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#include <linux/tegra-icc.h>
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#include <soc/tegra/bpmp.h>
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#include "mc.h"
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static const struct tegra_mc_client tegra234_mc_clients[] = {
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{
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.id = TEGRA234_MEMORY_CLIENT_HDAR,
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.name = "hdar",
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.bpmp_id = TEGRA_ICC_BPMP_HDA,
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.type = TEGRA_ICC_ISO_AUDIO,
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.sid = TEGRA234_SID_HDA,
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.regs = {
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.sid = {
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.override = 0xa8,
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.security = 0xac,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_HDAW,
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.name = "hdaw",
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.bpmp_id = TEGRA_ICC_BPMP_HDA,
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.type = TEGRA_ICC_ISO_AUDIO,
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.sid = TEGRA234_SID_HDA,
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.regs = {
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.sid = {
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.override = 0x1a8,
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.security = 0x1ac,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_MGBEARD,
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.name = "mgbeard",
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.bpmp_id = TEGRA_ICC_BPMP_EQOS,
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.type = TEGRA_ICC_NISO,
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.sid = TEGRA234_SID_MGBE,
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.regs = {
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.sid = {
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.override = 0x2c0,
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.security = 0x2c4,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_MGBEBRD,
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.name = "mgbebrd",
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.bpmp_id = TEGRA_ICC_BPMP_EQOS,
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.type = TEGRA_ICC_NISO,
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.sid = TEGRA234_SID_MGBE_VF1,
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.regs = {
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.sid = {
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.override = 0x2c8,
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.security = 0x2cc,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_MGBECRD,
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.name = "mgbecrd",
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.bpmp_id = TEGRA_ICC_BPMP_EQOS,
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.type = TEGRA_ICC_NISO,
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.sid = TEGRA234_SID_MGBE_VF2,
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.regs = {
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.sid = {
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.override = 0x2d0,
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.security = 0x2d4,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_MGBEDRD,
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.name = "mgbedrd",
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.bpmp_id = TEGRA_ICC_BPMP_EQOS,
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.type = TEGRA_ICC_NISO,
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.sid = TEGRA234_SID_MGBE_VF3,
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.regs = {
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.sid = {
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.override = 0x2d8,
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.security = 0x2dc,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_MGBEAWR,
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.bpmp_id = TEGRA_ICC_BPMP_EQOS,
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.type = TEGRA_ICC_NISO,
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.name = "mgbeawr",
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.sid = TEGRA234_SID_MGBE,
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.regs = {
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.sid = {
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.override = 0x2e0,
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.security = 0x2e4,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_MGBEBWR,
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.name = "mgbebwr",
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.bpmp_id = TEGRA_ICC_BPMP_EQOS,
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.type = TEGRA_ICC_NISO,
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.sid = TEGRA234_SID_MGBE_VF1,
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.regs = {
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.sid = {
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.override = 0x2f8,
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.security = 0x2fc,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_MGBECWR,
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.name = "mgbecwr",
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.bpmp_id = TEGRA_ICC_BPMP_EQOS,
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.type = TEGRA_ICC_NISO,
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.sid = TEGRA234_SID_MGBE_VF2,
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.regs = {
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.sid = {
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.override = 0x308,
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.security = 0x30c,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_SDMMCRAB,
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.name = "sdmmcrab",
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.bpmp_id = TEGRA_ICC_BPMP_SDMMC_4,
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.type = TEGRA_ICC_NISO,
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.sid = TEGRA234_SID_SDMMC4,
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.regs = {
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.sid = {
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.override = 0x318,
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.security = 0x31c,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_MGBEDWR,
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.name = "mgbedwr",
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.bpmp_id = TEGRA_ICC_BPMP_EQOS,
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.type = TEGRA_ICC_NISO,
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.sid = TEGRA234_SID_MGBE_VF3,
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.regs = {
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.sid = {
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.override = 0x328,
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.security = 0x32c,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_SDMMCWAB,
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.name = "sdmmcwab",
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.bpmp_id = TEGRA_ICC_BPMP_SDMMC_4,
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.type = TEGRA_ICC_NISO,
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.sid = TEGRA234_SID_SDMMC4,
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.regs = {
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.sid = {
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.override = 0x338,
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.security = 0x33c,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_VI2W,
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.name = "vi2w",
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.bpmp_id = TEGRA_ICC_BPMP_VI2,
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.type = TEGRA_ICC_ISO_VI,
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.sid = TEGRA234_SID_ISO_VI2,
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.regs = {
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.sid = {
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.override = 0x380,
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.security = 0x384,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_VI2FALR,
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.name = "vi2falr",
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.bpmp_id = TEGRA_ICC_BPMP_VI2FAL,
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.type = TEGRA_ICC_ISO_VIFAL,
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.sid = TEGRA234_SID_ISO_VI2FALC,
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.regs = {
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.sid = {
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.override = 0x388,
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.security = 0x38c,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_VI2FALW,
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.name = "vi2falw",
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.bpmp_id = TEGRA_ICC_BPMP_VI2FAL,
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.type = TEGRA_ICC_ISO_VIFAL,
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.sid = TEGRA234_SID_ISO_VI2FALC,
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.regs = {
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.sid = {
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.override = 0x3e0,
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.security = 0x3e4,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_APER,
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.name = "aper",
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.bpmp_id = TEGRA_ICC_BPMP_APE,
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.type = TEGRA_ICC_ISO_AUDIO,
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.sid = TEGRA234_SID_APE,
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.regs = {
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.sid = {
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.override = 0x3d0,
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.security = 0x3d4,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_APEW,
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.name = "apew",
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.bpmp_id = TEGRA_ICC_BPMP_APE,
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.type = TEGRA_ICC_ISO_AUDIO,
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.sid = TEGRA234_SID_APE,
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.regs = {
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.sid = {
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.override = 0x3d8,
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.security = 0x3dc,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR,
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.name = "nvdisplayr",
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.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
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.type = TEGRA_ICC_ISO_DISPLAY,
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.sid = TEGRA234_SID_ISO_NVDISPLAY,
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.regs = {
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.sid = {
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.override = 0x490,
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.security = 0x494,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1,
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.name = "nvdisplayr1",
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.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
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.type = TEGRA_ICC_ISO_DISPLAY,
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.sid = TEGRA234_SID_ISO_NVDISPLAY,
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.regs = {
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.sid = {
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.override = 0x508,
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.security = 0x50c,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_BPMPR,
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.name = "bpmpr",
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.sid = TEGRA234_SID_BPMP,
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.regs = {
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.sid = {
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.override = 0x498,
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.security = 0x49c,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_BPMPW,
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.name = "bpmpw",
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.sid = TEGRA234_SID_BPMP,
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.regs = {
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.sid = {
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.override = 0x4a0,
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.security = 0x4a4,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_BPMPDMAR,
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.name = "bpmpdmar",
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.sid = TEGRA234_SID_BPMP,
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.regs = {
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.sid = {
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.override = 0x4a8,
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.security = 0x4ac,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_BPMPDMAW,
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.name = "bpmpdmaw",
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.sid = TEGRA234_SID_BPMP,
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.regs = {
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.sid = {
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.override = 0x4b0,
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.security = 0x4b4,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_APEDMAR,
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.name = "apedmar",
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.bpmp_id = TEGRA_ICC_BPMP_APEDMA,
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.type = TEGRA_ICC_ISO_AUDIO,
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.sid = TEGRA234_SID_APE,
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.regs = {
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.sid = {
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.override = 0x4f8,
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.security = 0x4fc,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_APEDMAW,
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.name = "apedmaw",
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.bpmp_id = TEGRA_ICC_BPMP_APEDMA,
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.type = TEGRA_ICC_ISO_AUDIO,
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.sid = TEGRA234_SID_APE,
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.regs = {
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.sid = {
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.override = 0x500,
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.security = 0x504,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_DLA0RDA,
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.name = "dla0rda",
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.sid = TEGRA234_SID_NVDLA0,
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.regs = {
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.sid = {
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.override = 0x5f0,
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.security = 0x5f4,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_DLA0FALRDB,
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.name = "dla0falrdb",
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.sid = TEGRA234_SID_NVDLA0,
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.regs = {
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.sid = {
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.override = 0x5f8,
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.security = 0x5fc,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_DLA0WRA,
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.name = "dla0wra",
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.sid = TEGRA234_SID_NVDLA0,
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.regs = {
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.sid = {
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.override = 0x600,
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.security = 0x604,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_DLA0RDB,
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.name = "dla0rdb",
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.sid = TEGRA234_SID_NVDLA0,
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.regs = {
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.sid = {
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.override = 0x160,
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.security = 0x164,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_DLA0RDA1,
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.name = "dla0rda1",
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.sid = TEGRA234_SID_NVDLA0,
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.regs = {
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.sid = {
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.override = 0x748,
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.security = 0x74c,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_DLA0FALWRB,
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.name = "dla0falwrb",
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.sid = TEGRA234_SID_NVDLA0,
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.regs = {
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.sid = {
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.override = 0x608,
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.security = 0x60c,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_DLA0RDB1,
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.name = "dla0rdb1",
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.sid = TEGRA234_SID_NVDLA0,
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.regs = {
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.sid = {
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.override = 0x168,
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.security = 0x16c,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_DLA0WRB,
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.name = "dla0wrb",
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.sid = TEGRA234_SID_NVDLA0,
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.regs = {
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.sid = {
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.override = 0x170,
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.security = 0x174,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_DLA1RDA,
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.name = "dla0rda",
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.sid = TEGRA234_SID_NVDLA1,
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.regs = {
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.sid = {
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.override = 0x610,
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.security = 0x614,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_DLA1FALRDB,
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.name = "dla0falrdb",
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.sid = TEGRA234_SID_NVDLA1,
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.regs = {
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.sid = {
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.override = 0x618,
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.security = 0x61c,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_DLA1WRA,
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.name = "dla0wra",
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.sid = TEGRA234_SID_NVDLA1,
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.regs = {
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.sid = {
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.override = 0x620,
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.security = 0x624,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_DLA1RDB,
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.name = "dla0rdb",
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.sid = TEGRA234_SID_NVDLA1,
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.regs = {
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.sid = {
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.override = 0x178,
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.security = 0x17c,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_DLA1RDA1,
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.name = "dla0rda1",
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.sid = TEGRA234_SID_NVDLA1,
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.regs = {
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.sid = {
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.override = 0x750,
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.security = 0x754,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_DLA1FALWRB,
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.name = "dla0falwrb",
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.sid = TEGRA234_SID_NVDLA1,
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.regs = {
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.sid = {
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.override = 0x628,
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.security = 0x62c,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_DLA1RDB1,
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.name = "dla0rdb1",
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.sid = TEGRA234_SID_NVDLA1,
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.regs = {
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.sid = {
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.override = 0x370,
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.security = 0x374,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_DLA1WRB,
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.name = "dla0wrb",
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.sid = TEGRA234_SID_NVDLA1,
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.regs = {
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.sid = {
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.override = 0x378,
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.security = 0x37c,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_PCIE0R,
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.name = "pcie0r",
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.bpmp_id = TEGRA_ICC_BPMP_PCIE_0,
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.type = TEGRA_ICC_NISO,
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.sid = TEGRA234_SID_PCIE0,
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.regs = {
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.sid = {
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.override = 0x6c0,
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.security = 0x6c4,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_PCIE0W,
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.name = "pcie0w",
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.bpmp_id = TEGRA_ICC_BPMP_PCIE_0,
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.type = TEGRA_ICC_NISO,
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.sid = TEGRA234_SID_PCIE0,
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.regs = {
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.sid = {
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.override = 0x6c8,
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.security = 0x6cc,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_PCIE1R,
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.name = "pcie1r",
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.bpmp_id = TEGRA_ICC_BPMP_PCIE_1,
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.type = TEGRA_ICC_NISO,
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.sid = TEGRA234_SID_PCIE1,
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.regs = {
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.sid = {
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.override = 0x6d0,
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.security = 0x6d4,
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},
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},
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}, {
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.id = TEGRA234_MEMORY_CLIENT_PCIE1W,
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.name = "pcie1w",
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.bpmp_id = TEGRA_ICC_BPMP_PCIE_1,
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.type = TEGRA_ICC_NISO,
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|
.sid = TEGRA234_SID_PCIE1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x6d8,
|
|
.security = 0x6dc,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE2AR,
|
|
.name = "pcie2ar",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_2,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE2,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x6e0,
|
|
.security = 0x6e4,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE2AW,
|
|
.name = "pcie2aw",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_2,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE2,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x6e8,
|
|
.security = 0x6ec,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE3R,
|
|
.name = "pcie3r",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_3,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE3,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x6f0,
|
|
.security = 0x6f4,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE3W,
|
|
.name = "pcie3w",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_3,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE3,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x6f8,
|
|
.security = 0x6fc,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE4R,
|
|
.name = "pcie4r",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_4,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE4,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x700,
|
|
.security = 0x704,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE4W,
|
|
.name = "pcie4w",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_4,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE4,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x708,
|
|
.security = 0x70c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE5R,
|
|
.name = "pcie5r",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE5,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x710,
|
|
.security = 0x714,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE5W,
|
|
.name = "pcie5w",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE5,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x718,
|
|
.security = 0x71c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE5R1,
|
|
.name = "pcie5r1",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE5,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x778,
|
|
.security = 0x77c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE6AR,
|
|
.name = "pcie6ar",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE6,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x140,
|
|
.security = 0x144,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE6AW,
|
|
.name = "pcie6aw",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE6,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x148,
|
|
.security = 0x14c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE6AR1,
|
|
.name = "pcie6ar1",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE6,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x1e8,
|
|
.security = 0x1ec,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE7AR,
|
|
.name = "pcie7ar",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE7,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x150,
|
|
.security = 0x154,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE7AW,
|
|
.name = "pcie7aw",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE7,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x180,
|
|
.security = 0x184,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE7AR1,
|
|
.name = "pcie7ar1",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE7,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x248,
|
|
.security = 0x24c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE8AR,
|
|
.name = "pcie8ar",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE8,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x190,
|
|
.security = 0x194,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE8AW,
|
|
.name = "pcie8aw",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE8,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x1d8,
|
|
.security = 0x1dc,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE9AR,
|
|
.name = "pcie9ar",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE9,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x1e0,
|
|
.security = 0x1e4,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE9AW,
|
|
.name = "pcie9aw",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE9,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x1f0,
|
|
.security = 0x1f4,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE10AR,
|
|
.name = "pcie10ar",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE10,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x1f8,
|
|
.security = 0x1fc,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE10AW,
|
|
.name = "pcie10aw",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE10,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x200,
|
|
.security = 0x204,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA234_MEMORY_CLIENT_PCIE10AR1,
|
|
.name = "pcie10ar1",
|
|
.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
|
|
.type = TEGRA_ICC_NISO,
|
|
.sid = TEGRA234_SID_PCIE10,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x240,
|
|
.security = 0x244,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA_ICC_MC_CPU_CLUSTER0,
|
|
.name = "sw_cluster0",
|
|
.bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER0,
|
|
.type = TEGRA_ICC_NISO,
|
|
}, {
|
|
.id = TEGRA_ICC_MC_CPU_CLUSTER1,
|
|
.name = "sw_cluster1",
|
|
.bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER1,
|
|
.type = TEGRA_ICC_NISO,
|
|
}, {
|
|
.id = TEGRA_ICC_MC_CPU_CLUSTER2,
|
|
.name = "sw_cluster2",
|
|
.bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER2,
|
|
.type = TEGRA_ICC_NISO,
|
|
},
|
|
};
|
|
|
|
/*
|
|
* tegra234_mc_icc_set() - Pass MC client info to the BPMP-FW
|
|
* @src: ICC node for Memory Controller's (MC) Client
|
|
* @dst: ICC node for Memory Controller (MC)
|
|
*
|
|
* Passing the current request info from the MC to the BPMP-FW where
|
|
* LA and PTSA registers are accessed and the final EMC freq is set
|
|
* based on client_id, type, latency and bandwidth.
|
|
* icc_set_bw() makes set_bw calls for both MC and EMC providers in
|
|
* sequence. Both the calls are protected by 'mutex_lock(&icc_lock)'.
|
|
* So, the data passed won't be updated by concurrent set calls from
|
|
* other clients.
|
|
*/
|
|
static int tegra234_mc_icc_set(struct icc_node *src, struct icc_node *dst)
|
|
{
|
|
struct tegra_mc *mc = icc_provider_to_tegra_mc(dst->provider);
|
|
struct mrq_bwmgr_int_request bwmgr_req = { 0 };
|
|
struct mrq_bwmgr_int_response bwmgr_resp = { 0 };
|
|
const struct tegra_mc_client *pclient = src->data;
|
|
struct tegra_bpmp_message msg;
|
|
int ret;
|
|
|
|
/*
|
|
* Same Src and Dst node will happen during boot from icc_node_add().
|
|
* This can be used to pre-initialize and set bandwidth for all clients
|
|
* before their drivers are loaded. We are skipping this case as for us,
|
|
* the pre-initialization already happened in Bootloader(MB2) and BPMP-FW.
|
|
*/
|
|
if (src->id == dst->id)
|
|
return 0;
|
|
|
|
if (!mc->bwmgr_mrq_supported)
|
|
return 0;
|
|
|
|
if (!mc->bpmp) {
|
|
dev_err(mc->dev, "BPMP reference NULL\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
if (pclient->type == TEGRA_ICC_NISO)
|
|
bwmgr_req.bwmgr_calc_set_req.niso_bw = src->avg_bw;
|
|
else
|
|
bwmgr_req.bwmgr_calc_set_req.iso_bw = src->avg_bw;
|
|
|
|
bwmgr_req.bwmgr_calc_set_req.client_id = pclient->bpmp_id;
|
|
|
|
bwmgr_req.cmd = CMD_BWMGR_INT_CALC_AND_SET;
|
|
bwmgr_req.bwmgr_calc_set_req.mc_floor = src->peak_bw;
|
|
bwmgr_req.bwmgr_calc_set_req.floor_unit = BWMGR_INT_UNIT_KBPS;
|
|
|
|
memset(&msg, 0, sizeof(msg));
|
|
msg.mrq = MRQ_BWMGR_INT;
|
|
msg.tx.data = &bwmgr_req;
|
|
msg.tx.size = sizeof(bwmgr_req);
|
|
msg.rx.data = &bwmgr_resp;
|
|
msg.rx.size = sizeof(bwmgr_resp);
|
|
|
|
ret = tegra_bpmp_transfer(mc->bpmp, &msg);
|
|
if (ret < 0) {
|
|
dev_err(mc->dev, "BPMP transfer failed: %d\n", ret);
|
|
goto error;
|
|
}
|
|
if (msg.rx.ret < 0) {
|
|
pr_err("failed to set bandwidth for %u: %d\n",
|
|
bwmgr_req.bwmgr_calc_set_req.client_id, msg.rx.ret);
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
error:
|
|
return ret;
|
|
}
|
|
|
|
static int tegra234_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
|
|
u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
|
|
{
|
|
struct icc_provider *p = node->provider;
|
|
struct tegra_mc *mc = icc_provider_to_tegra_mc(p);
|
|
|
|
if (!mc->bwmgr_mrq_supported)
|
|
return 0;
|
|
|
|
if (node->id == TEGRA_ICC_MC_CPU_CLUSTER0 ||
|
|
node->id == TEGRA_ICC_MC_CPU_CLUSTER1 ||
|
|
node->id == TEGRA_ICC_MC_CPU_CLUSTER2) {
|
|
if (mc)
|
|
peak_bw = peak_bw * mc->num_channels;
|
|
}
|
|
|
|
*agg_avg += avg_bw;
|
|
*agg_peak = max(*agg_peak, peak_bw);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra234_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak)
|
|
{
|
|
*avg = 0;
|
|
*peak = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct tegra_mc_icc_ops tegra234_mc_icc_ops = {
|
|
.xlate = tegra_mc_icc_xlate,
|
|
.aggregate = tegra234_mc_icc_aggregate,
|
|
.get_bw = tegra234_mc_icc_get_init_bw,
|
|
.set = tegra234_mc_icc_set,
|
|
};
|
|
|
|
const struct tegra_mc_soc tegra234_mc_soc = {
|
|
.num_clients = ARRAY_SIZE(tegra234_mc_clients),
|
|
.clients = tegra234_mc_clients,
|
|
.num_address_bits = 40,
|
|
.num_channels = 16,
|
|
.client_id_mask = 0x1ff,
|
|
.intmask = MC_INT_DECERR_ROUTE_SANITY |
|
|
MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
|
|
MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
|
|
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
|
|
.has_addr_hi_reg = true,
|
|
.ops = &tegra186_mc_ops,
|
|
.icc_ops = &tegra234_mc_icc_ops,
|
|
.ch_intmask = 0x0000ff00,
|
|
.global_intstatus_channel_shift = 8,
|
|
/*
|
|
* Additionally, there are lite carveouts but those are not currently
|
|
* supported.
|
|
*/
|
|
.num_carveouts = 32,
|
|
};
|