392 lines
11 KiB
C
392 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/G2L Multi-Function Timer Pulse Unit 3(MTU3a) Core driver
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*
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* Copyright (C) 2023 Renesas Electronics Corporation
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/rz-mtu3.h>
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#include <linux/of_platform.h>
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#include <linux/reset.h>
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#include <linux/spinlock.h>
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#include "rz-mtu3.h"
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struct rz_mtu3_priv {
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void __iomem *mmio;
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struct reset_control *rstc;
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raw_spinlock_t lock;
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};
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/******* MTU3 registers (original offset is +0x1200) *******/
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static const unsigned long rz_mtu3_8bit_ch_reg_offs[][13] = {
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[RZ_MTU3_CHAN_0] = MTU_8BIT_CH_0(0x104, 0x090, 0x100, 0x128, 0x101, 0x102, 0x103, 0x126),
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[RZ_MTU3_CHAN_1] = MTU_8BIT_CH_1_2(0x184, 0x091, 0x185, 0x180, 0x194, 0x181, 0x182),
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[RZ_MTU3_CHAN_2] = MTU_8BIT_CH_1_2(0x204, 0x092, 0x205, 0x200, 0x20c, 0x201, 0x202),
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[RZ_MTU3_CHAN_3] = MTU_8BIT_CH_3_4_6_7(0x008, 0x093, 0x02c, 0x000, 0x04c, 0x002, 0x004, 0x005, 0x038),
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[RZ_MTU3_CHAN_4] = MTU_8BIT_CH_3_4_6_7(0x009, 0x094, 0x02d, 0x001, 0x04d, 0x003, 0x006, 0x007, 0x039),
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[RZ_MTU3_CHAN_5] = MTU_8BIT_CH_5(0xab2, 0x1eb, 0xab4, 0xab6, 0xa84, 0xa85, 0xa86, 0xa94, 0xa95, 0xa96, 0xaa4, 0xaa5, 0xaa6),
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[RZ_MTU3_CHAN_6] = MTU_8BIT_CH_3_4_6_7(0x808, 0x893, 0x82c, 0x800, 0x84c, 0x802, 0x804, 0x805, 0x838),
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[RZ_MTU3_CHAN_7] = MTU_8BIT_CH_3_4_6_7(0x809, 0x894, 0x82d, 0x801, 0x84d, 0x803, 0x806, 0x807, 0x839),
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[RZ_MTU3_CHAN_8] = MTU_8BIT_CH_8(0x404, 0x098, 0x400, 0x406, 0x401, 0x402, 0x403)
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};
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static const unsigned long rz_mtu3_16bit_ch_reg_offs[][12] = {
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[RZ_MTU3_CHAN_0] = MTU_16BIT_CH_0(0x106, 0x108, 0x10a, 0x10c, 0x10e, 0x120, 0x122),
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[RZ_MTU3_CHAN_1] = MTU_16BIT_CH_1_2(0x186, 0x188, 0x18a),
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[RZ_MTU3_CHAN_2] = MTU_16BIT_CH_1_2(0x206, 0x208, 0x20a),
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[RZ_MTU3_CHAN_3] = MTU_16BIT_CH_3_6(0x010, 0x018, 0x01a, 0x024, 0x026, 0x072),
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[RZ_MTU3_CHAN_4] = MTU_16BIT_CH_4_7(0x012, 0x01c, 0x01e, 0x028, 0x2a, 0x074, 0x076, 0x040, 0x044, 0x046, 0x048, 0x04a),
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[RZ_MTU3_CHAN_5] = MTU_16BIT_CH_5(0xa80, 0xa82, 0xa90, 0xa92, 0xaa0, 0xaa2),
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[RZ_MTU3_CHAN_6] = MTU_16BIT_CH_3_6(0x810, 0x818, 0x81a, 0x824, 0x826, 0x872),
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[RZ_MTU3_CHAN_7] = MTU_16BIT_CH_4_7(0x812, 0x81c, 0x81e, 0x828, 0x82a, 0x874, 0x876, 0x840, 0x844, 0x846, 0x848, 0x84a)
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};
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static const unsigned long rz_mtu3_32bit_ch_reg_offs[][5] = {
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[RZ_MTU3_CHAN_1] = MTU_32BIT_CH_1(0x1a0, 0x1a4, 0x1a8),
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[RZ_MTU3_CHAN_8] = MTU_32BIT_CH_8(0x408, 0x40c, 0x410, 0x414, 0x418)
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};
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static bool rz_mtu3_is_16bit_shared_reg(u16 offset)
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{
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return (offset == RZ_MTU3_TDDRA || offset == RZ_MTU3_TDDRB ||
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offset == RZ_MTU3_TCDRA || offset == RZ_MTU3_TCDRB ||
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offset == RZ_MTU3_TCBRA || offset == RZ_MTU3_TCBRB ||
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offset == RZ_MTU3_TCNTSA || offset == RZ_MTU3_TCNTSB);
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}
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u16 rz_mtu3_shared_reg_read(struct rz_mtu3_channel *ch, u16 offset)
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{
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struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
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struct rz_mtu3_priv *priv = mtu->priv_data;
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if (rz_mtu3_is_16bit_shared_reg(offset))
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return readw(priv->mmio + offset);
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else
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return readb(priv->mmio + offset);
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}
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EXPORT_SYMBOL_GPL(rz_mtu3_shared_reg_read);
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u8 rz_mtu3_8bit_ch_read(struct rz_mtu3_channel *ch, u16 offset)
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{
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struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
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struct rz_mtu3_priv *priv = mtu->priv_data;
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u16 ch_offs;
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ch_offs = rz_mtu3_8bit_ch_reg_offs[ch->channel_number][offset];
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return readb(priv->mmio + ch_offs);
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}
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EXPORT_SYMBOL_GPL(rz_mtu3_8bit_ch_read);
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u16 rz_mtu3_16bit_ch_read(struct rz_mtu3_channel *ch, u16 offset)
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{
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struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
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struct rz_mtu3_priv *priv = mtu->priv_data;
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u16 ch_offs;
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/* MTU8 doesn't have 16-bit registers */
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if (ch->channel_number == RZ_MTU3_CHAN_8)
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return 0;
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ch_offs = rz_mtu3_16bit_ch_reg_offs[ch->channel_number][offset];
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return readw(priv->mmio + ch_offs);
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}
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EXPORT_SYMBOL_GPL(rz_mtu3_16bit_ch_read);
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u32 rz_mtu3_32bit_ch_read(struct rz_mtu3_channel *ch, u16 offset)
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{
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struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
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struct rz_mtu3_priv *priv = mtu->priv_data;
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u16 ch_offs;
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if (ch->channel_number != RZ_MTU3_CHAN_1 && ch->channel_number != RZ_MTU3_CHAN_8)
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return 0;
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ch_offs = rz_mtu3_32bit_ch_reg_offs[ch->channel_number][offset];
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return readl(priv->mmio + ch_offs);
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}
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EXPORT_SYMBOL_GPL(rz_mtu3_32bit_ch_read);
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void rz_mtu3_8bit_ch_write(struct rz_mtu3_channel *ch, u16 offset, u8 val)
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{
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struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
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struct rz_mtu3_priv *priv = mtu->priv_data;
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u16 ch_offs;
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ch_offs = rz_mtu3_8bit_ch_reg_offs[ch->channel_number][offset];
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writeb(val, priv->mmio + ch_offs);
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}
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EXPORT_SYMBOL_GPL(rz_mtu3_8bit_ch_write);
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void rz_mtu3_16bit_ch_write(struct rz_mtu3_channel *ch, u16 offset, u16 val)
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{
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struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
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struct rz_mtu3_priv *priv = mtu->priv_data;
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u16 ch_offs;
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/* MTU8 doesn't have 16-bit registers */
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if (ch->channel_number == RZ_MTU3_CHAN_8)
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return;
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ch_offs = rz_mtu3_16bit_ch_reg_offs[ch->channel_number][offset];
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writew(val, priv->mmio + ch_offs);
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}
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EXPORT_SYMBOL_GPL(rz_mtu3_16bit_ch_write);
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void rz_mtu3_32bit_ch_write(struct rz_mtu3_channel *ch, u16 offset, u32 val)
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{
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struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
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struct rz_mtu3_priv *priv = mtu->priv_data;
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u16 ch_offs;
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if (ch->channel_number != RZ_MTU3_CHAN_1 && ch->channel_number != RZ_MTU3_CHAN_8)
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return;
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ch_offs = rz_mtu3_32bit_ch_reg_offs[ch->channel_number][offset];
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writel(val, priv->mmio + ch_offs);
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}
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EXPORT_SYMBOL_GPL(rz_mtu3_32bit_ch_write);
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void rz_mtu3_shared_reg_write(struct rz_mtu3_channel *ch, u16 offset, u16 value)
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{
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struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
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struct rz_mtu3_priv *priv = mtu->priv_data;
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if (rz_mtu3_is_16bit_shared_reg(offset))
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writew(value, priv->mmio + offset);
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else
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writeb((u8)value, priv->mmio + offset);
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}
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EXPORT_SYMBOL_GPL(rz_mtu3_shared_reg_write);
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void rz_mtu3_shared_reg_update_bit(struct rz_mtu3_channel *ch, u16 offset,
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u16 pos, u8 val)
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{
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struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
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struct rz_mtu3_priv *priv = mtu->priv_data;
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unsigned long tmdr, flags;
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raw_spin_lock_irqsave(&priv->lock, flags);
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tmdr = rz_mtu3_shared_reg_read(ch, offset);
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__assign_bit(pos, &tmdr, !!val);
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rz_mtu3_shared_reg_write(ch, offset, tmdr);
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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}
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EXPORT_SYMBOL_GPL(rz_mtu3_shared_reg_update_bit);
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static u16 rz_mtu3_get_tstr_offset(struct rz_mtu3_channel *ch)
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{
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u16 offset;
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switch (ch->channel_number) {
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case RZ_MTU3_CHAN_0:
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case RZ_MTU3_CHAN_1:
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case RZ_MTU3_CHAN_2:
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case RZ_MTU3_CHAN_3:
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case RZ_MTU3_CHAN_4:
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case RZ_MTU3_CHAN_8:
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offset = RZ_MTU3_TSTRA;
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break;
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case RZ_MTU3_CHAN_5:
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offset = RZ_MTU3_TSTR;
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break;
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case RZ_MTU3_CHAN_6:
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case RZ_MTU3_CHAN_7:
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offset = RZ_MTU3_TSTRB;
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break;
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default:
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offset = 0;
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break;
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}
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return offset;
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}
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static u8 rz_mtu3_get_tstr_bit_pos(struct rz_mtu3_channel *ch)
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{
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u8 bitpos;
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switch (ch->channel_number) {
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case RZ_MTU3_CHAN_0:
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case RZ_MTU3_CHAN_1:
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case RZ_MTU3_CHAN_2:
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case RZ_MTU3_CHAN_6:
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case RZ_MTU3_CHAN_7:
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bitpos = ch->channel_number;
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break;
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case RZ_MTU3_CHAN_3:
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bitpos = 6;
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break;
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case RZ_MTU3_CHAN_4:
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bitpos = 7;
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break;
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case RZ_MTU3_CHAN_5:
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bitpos = 2;
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break;
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case RZ_MTU3_CHAN_8:
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bitpos = 3;
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break;
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default:
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bitpos = 0;
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break;
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}
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return bitpos;
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}
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static void rz_mtu3_start_stop_ch(struct rz_mtu3_channel *ch, bool start)
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{
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struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
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struct rz_mtu3_priv *priv = mtu->priv_data;
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unsigned long flags, tstr;
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u16 offset;
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u8 bitpos;
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/* start stop register shared by multiple timer channels */
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raw_spin_lock_irqsave(&priv->lock, flags);
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offset = rz_mtu3_get_tstr_offset(ch);
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bitpos = rz_mtu3_get_tstr_bit_pos(ch);
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tstr = rz_mtu3_shared_reg_read(ch, offset);
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__assign_bit(bitpos, &tstr, start);
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rz_mtu3_shared_reg_write(ch, offset, tstr);
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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}
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bool rz_mtu3_is_enabled(struct rz_mtu3_channel *ch)
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{
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struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
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struct rz_mtu3_priv *priv = mtu->priv_data;
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unsigned long flags, tstr;
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bool ret = false;
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u16 offset;
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u8 bitpos;
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/* start stop register shared by multiple timer channels */
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raw_spin_lock_irqsave(&priv->lock, flags);
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offset = rz_mtu3_get_tstr_offset(ch);
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bitpos = rz_mtu3_get_tstr_bit_pos(ch);
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tstr = rz_mtu3_shared_reg_read(ch, offset);
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ret = tstr & BIT(bitpos);
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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return ret;
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}
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EXPORT_SYMBOL_GPL(rz_mtu3_is_enabled);
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int rz_mtu3_enable(struct rz_mtu3_channel *ch)
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{
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/* enable channel */
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rz_mtu3_start_stop_ch(ch, true);
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return 0;
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}
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EXPORT_SYMBOL_GPL(rz_mtu3_enable);
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void rz_mtu3_disable(struct rz_mtu3_channel *ch)
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{
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/* disable channel */
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rz_mtu3_start_stop_ch(ch, false);
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}
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EXPORT_SYMBOL_GPL(rz_mtu3_disable);
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static void rz_mtu3_reset_assert(void *data)
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{
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struct rz_mtu3 *mtu = dev_get_drvdata(data);
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struct rz_mtu3_priv *priv = mtu->priv_data;
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mfd_remove_devices(data);
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reset_control_assert(priv->rstc);
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}
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static const struct mfd_cell rz_mtu3_devs[] = {
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{
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.name = "rz-mtu3-counter",
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},
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{
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.name = "pwm-rz-mtu3",
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},
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};
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static int rz_mtu3_probe(struct platform_device *pdev)
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{
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struct rz_mtu3_priv *priv;
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struct rz_mtu3 *ddata;
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unsigned int i;
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int ret;
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ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
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if (!ddata)
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return -ENOMEM;
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ddata->priv_data = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!ddata->priv_data)
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return -ENOMEM;
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priv = ddata->priv_data;
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priv->mmio = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->mmio))
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return PTR_ERR(priv->mmio);
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priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
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if (IS_ERR(priv->rstc))
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return PTR_ERR(priv->rstc);
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ddata->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(ddata->clk))
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return PTR_ERR(ddata->clk);
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reset_control_deassert(priv->rstc);
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raw_spin_lock_init(&priv->lock);
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platform_set_drvdata(pdev, ddata);
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for (i = 0; i < RZ_MTU_NUM_CHANNELS; i++) {
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ddata->channels[i].channel_number = i;
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ddata->channels[i].is_busy = false;
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mutex_init(&ddata->channels[i].lock);
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}
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ret = mfd_add_devices(&pdev->dev, 0, rz_mtu3_devs,
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ARRAY_SIZE(rz_mtu3_devs), NULL, 0, NULL);
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if (ret < 0)
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goto err_assert;
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return devm_add_action_or_reset(&pdev->dev, rz_mtu3_reset_assert,
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&pdev->dev);
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err_assert:
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reset_control_assert(priv->rstc);
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return ret;
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}
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static const struct of_device_id rz_mtu3_of_match[] = {
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{ .compatible = "renesas,rz-mtu3", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, rz_mtu3_of_match);
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static struct platform_driver rz_mtu3_driver = {
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.probe = rz_mtu3_probe,
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.driver = {
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.name = "rz-mtu3",
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.of_match_table = rz_mtu3_of_match,
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},
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};
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module_platform_driver(rz_mtu3_driver);
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MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
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MODULE_DESCRIPTION("Renesas RZ/G2L MTU3a Core Driver");
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MODULE_LICENSE("GPL");
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