523 lines
12 KiB
C
523 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Freescale eSDHC ColdFire family controller driver, platform bus.
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*
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* Copyright (c) 2020 Timesys Corporation
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* Author: Angelo Dureghello <angelo.dureghello@timesys.it>
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/platform_data/mmc-esdhc-mcf.h>
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#include <linux/mmc/mmc.h>
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#include "sdhci-pltfm.h"
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#include "sdhci-esdhc.h"
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#define ESDHC_PROCTL_D3CD 0x08
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#define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
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#define ESDHC_DEFAULT_HOST_CONTROL 0x28
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/*
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* Freescale eSDHC has DMA ERR flag at bit 28, not as std spec says, bit 25.
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*/
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#define ESDHC_INT_VENDOR_SPEC_DMA_ERR BIT(28)
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struct pltfm_mcf_data {
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struct clk *clk_ipg;
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struct clk *clk_ahb;
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struct clk *clk_per;
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int aside;
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int current_bus_width;
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};
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static inline void esdhc_mcf_buffer_swap32(u32 *buf, int len)
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{
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int i;
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u32 temp;
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len = (len + 3) >> 2;
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for (i = 0; i < len; i++) {
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temp = swab32(*buf);
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*buf++ = temp;
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}
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}
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static inline void esdhc_clrset_be(struct sdhci_host *host,
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u32 mask, u32 val, int reg)
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{
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void __iomem *base = host->ioaddr + (reg & ~3);
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u8 shift = (reg & 3) << 3;
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mask <<= shift;
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val <<= shift;
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if (reg == SDHCI_HOST_CONTROL)
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val |= ESDHC_PROCTL_D3CD;
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writel((readl(base) & ~mask) | val, base);
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}
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/*
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* Note: mcf is big-endian, single bytes need to be accessed at big endian
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* offsets.
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*/
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static void esdhc_mcf_writeb_be(struct sdhci_host *host, u8 val, int reg)
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{
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void __iomem *base = host->ioaddr + (reg & ~3);
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u8 shift = (reg & 3) << 3;
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u32 mask = ~(0xff << shift);
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if (reg == SDHCI_HOST_CONTROL) {
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u32 host_ctrl = ESDHC_DEFAULT_HOST_CONTROL;
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u8 dma_bits = (val & SDHCI_CTRL_DMA_MASK) >> 3;
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u8 tmp = readb(host->ioaddr + SDHCI_HOST_CONTROL + 1);
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tmp &= ~0x03;
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tmp |= dma_bits;
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/*
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* Recomposition needed, restore always endianness and
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* keep D3CD and AI, just setting bus width.
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*/
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host_ctrl |= val;
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host_ctrl |= (dma_bits << 8);
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writel(host_ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
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return;
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}
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writel((readl(base) & mask) | (val << shift), base);
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}
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static void esdhc_mcf_writew_be(struct sdhci_host *host, u16 val, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
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void __iomem *base = host->ioaddr + (reg & ~3);
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u8 shift = (reg & 3) << 3;
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u32 mask = ~(0xffff << shift);
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switch (reg) {
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case SDHCI_TRANSFER_MODE:
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mcf_data->aside = val;
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return;
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case SDHCI_COMMAND:
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if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
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val |= SDHCI_CMD_ABORTCMD;
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/*
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* As for the fsl driver,
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* we have to set the mode in a single write here.
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*/
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writel(val << 16 | mcf_data->aside,
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host->ioaddr + SDHCI_TRANSFER_MODE);
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return;
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}
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writel((readl(base) & mask) | (val << shift), base);
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}
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static void esdhc_mcf_writel_be(struct sdhci_host *host, u32 val, int reg)
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{
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writel(val, host->ioaddr + reg);
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}
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static u8 esdhc_mcf_readb_be(struct sdhci_host *host, int reg)
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{
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if (reg == SDHCI_HOST_CONTROL) {
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u8 __iomem *base = host->ioaddr + (reg & ~3);
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u16 val = readw(base + 2);
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u8 dma_bits = (val >> 5) & SDHCI_CTRL_DMA_MASK;
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u8 host_ctrl = val & 0xff;
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host_ctrl &= ~SDHCI_CTRL_DMA_MASK;
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host_ctrl |= dma_bits;
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return host_ctrl;
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}
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return readb(host->ioaddr + (reg ^ 0x3));
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}
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static u16 esdhc_mcf_readw_be(struct sdhci_host *host, int reg)
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{
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/*
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* For SDHCI_HOST_VERSION, sdhci specs defines 0xFE,
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* a wrong offset for us, we are at 0xFC.
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*/
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if (reg == SDHCI_HOST_VERSION)
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reg -= 2;
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return readw(host->ioaddr + (reg ^ 0x2));
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}
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static u32 esdhc_mcf_readl_be(struct sdhci_host *host, int reg)
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{
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u32 val;
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val = readl(host->ioaddr + reg);
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/*
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* RM (25.3.9) sd pin clock must never exceed 25Mhz.
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* So forcing legacy mode at 25Mhz.
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*/
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if (unlikely(reg == SDHCI_CAPABILITIES))
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val &= ~SDHCI_CAN_DO_HISPD;
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if (unlikely(reg == SDHCI_INT_STATUS)) {
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if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
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val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
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val |= SDHCI_INT_ADMA_ERROR;
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}
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}
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return val;
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}
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static unsigned int esdhc_mcf_get_max_timeout_count(struct sdhci_host *host)
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{
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return 1 << 27;
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}
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static void esdhc_mcf_set_timeout(struct sdhci_host *host,
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struct mmc_command *cmd)
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{
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/* Use maximum timeout counter */
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esdhc_clrset_be(host, ESDHC_SYS_CTRL_DTOCV_MASK, 0xE,
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SDHCI_TIMEOUT_CONTROL);
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}
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static void esdhc_mcf_reset(struct sdhci_host *host, u8 mask)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
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sdhci_reset(host, mask);
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esdhc_clrset_be(host, ESDHC_CTRL_BUSWIDTH_MASK,
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mcf_data->current_bus_width, SDHCI_HOST_CONTROL);
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sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
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sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
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}
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static unsigned int esdhc_mcf_pltfm_get_max_clock(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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return pltfm_host->clock;
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}
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static unsigned int esdhc_mcf_pltfm_get_min_clock(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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return pltfm_host->clock / 256 / 16;
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}
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static void esdhc_mcf_pltfm_set_clock(struct sdhci_host *host,
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unsigned int clock)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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unsigned long *pll_dr = (unsigned long *)MCF_PLL_DR;
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u32 fvco, fsys, fesdhc, temp;
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const int sdclkfs[] = {2, 4, 8, 16, 32, 64, 128, 256};
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int delta, old_delta = clock;
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int i, q, ri, rq;
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if (clock == 0) {
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host->mmc->actual_clock = 0;
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return;
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}
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/*
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* ColdFire eSDHC clock.s
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*
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* pll -+-> / outdiv1 --> fsys
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* +-> / outdiv3 --> eSDHC clock ---> / SDCCLKFS / DVS
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*
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* mcf5441x datasheet says:
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* (8.1.2) eSDHC should be 40 MHz max
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* (25.3.9) eSDHC input is, as example, 96 Mhz ...
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* (25.3.9) sd pin clock must never exceed 25Mhz
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*
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* fvco = fsys * outdvi1 + 1
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* fshdc = fvco / outdiv3 + 1
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*/
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temp = readl(pll_dr);
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fsys = pltfm_host->clock;
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fvco = fsys * ((temp & 0x1f) + 1);
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fesdhc = fvco / (((temp >> 10) & 0x1f) + 1);
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for (i = 0; i < 8; ++i) {
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int result = fesdhc / sdclkfs[i];
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for (q = 1; q < 17; ++q) {
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int finale = result / q;
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delta = abs(clock - finale);
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if (delta < old_delta) {
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old_delta = delta;
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ri = i;
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rq = q;
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}
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}
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}
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/*
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* Apply divisors and re-enable all the clocks
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*/
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temp = ((sdclkfs[ri] >> 1) << 8) | ((rq - 1) << 4) |
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(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN);
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esdhc_clrset_be(host, 0x0000fff7, temp, SDHCI_CLOCK_CONTROL);
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host->mmc->actual_clock = clock;
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mdelay(1);
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}
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static void esdhc_mcf_pltfm_set_bus_width(struct sdhci_host *host, int width)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
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switch (width) {
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case MMC_BUS_WIDTH_4:
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mcf_data->current_bus_width = ESDHC_CTRL_4BITBUS;
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break;
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default:
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mcf_data->current_bus_width = 0;
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break;
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}
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esdhc_clrset_be(host, ESDHC_CTRL_BUSWIDTH_MASK,
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mcf_data->current_bus_width, SDHCI_HOST_CONTROL);
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}
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static void esdhc_mcf_request_done(struct sdhci_host *host,
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struct mmc_request *mrq)
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{
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struct scatterlist *sg;
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u32 *buffer;
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int i;
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if (!mrq->data || !mrq->data->bytes_xfered)
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goto exit_done;
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if (mmc_get_dma_dir(mrq->data) != DMA_FROM_DEVICE)
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goto exit_done;
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/*
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* On mcf5441x there is no hw sdma option/flag to select the dma
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* transfer endiannes. A swap after the transfer is needed.
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*/
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for_each_sg(mrq->data->sg, sg, mrq->data->sg_len, i) {
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buffer = (u32 *)sg_virt(sg);
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esdhc_mcf_buffer_swap32(buffer, sg->length);
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}
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exit_done:
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mmc_request_done(host->mmc, mrq);
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}
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static void esdhc_mcf_copy_to_bounce_buffer(struct sdhci_host *host,
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struct mmc_data *data,
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unsigned int length)
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{
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sg_copy_to_buffer(data->sg, data->sg_len,
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host->bounce_buffer, length);
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esdhc_mcf_buffer_swap32((u32 *)host->bounce_buffer,
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data->blksz * data->blocks);
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}
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static struct sdhci_ops sdhci_esdhc_ops = {
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.reset = esdhc_mcf_reset,
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.set_clock = esdhc_mcf_pltfm_set_clock,
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.get_max_clock = esdhc_mcf_pltfm_get_max_clock,
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.get_min_clock = esdhc_mcf_pltfm_get_min_clock,
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.set_bus_width = esdhc_mcf_pltfm_set_bus_width,
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.get_max_timeout_count = esdhc_mcf_get_max_timeout_count,
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.set_timeout = esdhc_mcf_set_timeout,
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.write_b = esdhc_mcf_writeb_be,
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.write_w = esdhc_mcf_writew_be,
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.write_l = esdhc_mcf_writel_be,
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.read_b = esdhc_mcf_readb_be,
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.read_w = esdhc_mcf_readw_be,
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.read_l = esdhc_mcf_readl_be,
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.copy_to_bounce_buffer = esdhc_mcf_copy_to_bounce_buffer,
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.request_done = esdhc_mcf_request_done,
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};
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static const struct sdhci_pltfm_data sdhci_esdhc_mcf_pdata = {
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.ops = &sdhci_esdhc_ops,
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.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_FORCE_DMA,
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/*
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* Mandatory quirk,
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* controller does not support cmd23,
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* without, on > 8G cards cmd23 is used, and
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* driver times out.
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*/
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SDHCI_QUIRK2_HOST_NO_CMD23,
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};
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static int esdhc_mcf_plat_init(struct sdhci_host *host,
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struct pltfm_mcf_data *mcf_data)
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{
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struct mcf_esdhc_platform_data *plat_data;
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struct device *dev = mmc_dev(host->mmc);
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if (!dev->platform_data) {
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dev_err(dev, "no platform data!\n");
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return -EINVAL;
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}
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plat_data = (struct mcf_esdhc_platform_data *)dev->platform_data;
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/* Card_detect */
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switch (plat_data->cd_type) {
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default:
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case ESDHC_CD_CONTROLLER:
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/* We have a working card_detect back */
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host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
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break;
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case ESDHC_CD_PERMANENT:
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host->mmc->caps |= MMC_CAP_NONREMOVABLE;
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break;
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case ESDHC_CD_NONE:
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break;
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}
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switch (plat_data->max_bus_width) {
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case 4:
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host->mmc->caps |= MMC_CAP_4_BIT_DATA;
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break;
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case 1:
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default:
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host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
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break;
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}
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return 0;
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}
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static int sdhci_esdhc_mcf_probe(struct platform_device *pdev)
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{
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struct sdhci_host *host;
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struct sdhci_pltfm_host *pltfm_host;
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struct pltfm_mcf_data *mcf_data;
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int err;
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host = sdhci_pltfm_init(pdev, &sdhci_esdhc_mcf_pdata,
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sizeof(*mcf_data));
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if (IS_ERR(host))
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return PTR_ERR(host);
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pltfm_host = sdhci_priv(host);
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mcf_data = sdhci_pltfm_priv(pltfm_host);
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host->sdma_boundary = 0;
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host->flags |= SDHCI_AUTO_CMD12;
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mcf_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
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if (IS_ERR(mcf_data->clk_ipg)) {
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err = PTR_ERR(mcf_data->clk_ipg);
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goto err_exit;
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}
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mcf_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
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if (IS_ERR(mcf_data->clk_ahb)) {
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err = PTR_ERR(mcf_data->clk_ahb);
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goto err_exit;
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}
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mcf_data->clk_per = devm_clk_get(&pdev->dev, "per");
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if (IS_ERR(mcf_data->clk_per)) {
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err = PTR_ERR(mcf_data->clk_per);
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goto err_exit;
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}
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pltfm_host->clk = mcf_data->clk_per;
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pltfm_host->clock = clk_get_rate(pltfm_host->clk);
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err = clk_prepare_enable(mcf_data->clk_per);
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if (err)
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goto err_exit;
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err = clk_prepare_enable(mcf_data->clk_ipg);
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if (err)
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goto unprep_per;
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err = clk_prepare_enable(mcf_data->clk_ahb);
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if (err)
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goto unprep_ipg;
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err = esdhc_mcf_plat_init(host, mcf_data);
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if (err)
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goto unprep_ahb;
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err = sdhci_setup_host(host);
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if (err)
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goto unprep_ahb;
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if (!host->bounce_buffer) {
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dev_err(&pdev->dev, "bounce buffer not allocated");
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err = -ENOMEM;
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goto cleanup;
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}
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err = __sdhci_add_host(host);
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if (err)
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goto cleanup;
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return 0;
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cleanup:
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sdhci_cleanup_host(host);
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unprep_ahb:
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clk_disable_unprepare(mcf_data->clk_ahb);
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unprep_ipg:
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clk_disable_unprepare(mcf_data->clk_ipg);
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unprep_per:
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clk_disable_unprepare(mcf_data->clk_per);
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err_exit:
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sdhci_pltfm_free(pdev);
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return err;
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}
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static int sdhci_esdhc_mcf_remove(struct platform_device *pdev)
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{
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|
struct sdhci_host *host = platform_get_drvdata(pdev);
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
|
|
|
|
sdhci_remove_host(host, 0);
|
|
|
|
clk_disable_unprepare(mcf_data->clk_ipg);
|
|
clk_disable_unprepare(mcf_data->clk_ahb);
|
|
clk_disable_unprepare(mcf_data->clk_per);
|
|
|
|
sdhci_pltfm_free(pdev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver sdhci_esdhc_mcf_driver = {
|
|
.driver = {
|
|
.name = "sdhci-esdhc-mcf",
|
|
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
|
|
},
|
|
.probe = sdhci_esdhc_mcf_probe,
|
|
.remove = sdhci_esdhc_mcf_remove,
|
|
};
|
|
|
|
module_platform_driver(sdhci_esdhc_mcf_driver);
|
|
|
|
MODULE_DESCRIPTION("SDHCI driver for Freescale ColdFire eSDHC");
|
|
MODULE_AUTHOR("Angelo Dureghello <angelo.dureghello@timesys.com>");
|
|
MODULE_LICENSE("GPL v2");
|