667 lines
18 KiB
C
667 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for Synopsys DesignWare Cores Mobile Storage Host Controller
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*
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* Copyright (C) 2018 Synaptics Incorporated
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*
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* Author: Jisheng Zhang <jszhang@kernel.org>
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*/
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#include <linux/acpi.h>
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/reset.h>
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#include <linux/sizes.h>
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#include "sdhci-pltfm.h"
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#define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16)
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/* DWCMSHC specific Mode Select value */
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#define DWCMSHC_CTRL_HS400 0x7
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/* DWC IP vendor area 1 pointer */
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#define DWCMSHC_P_VENDOR_AREA1 0xe8
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#define DWCMSHC_AREA1_MASK GENMASK(11, 0)
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/* Offset inside the vendor area 1 */
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#define DWCMSHC_HOST_CTRL3 0x8
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#define DWCMSHC_EMMC_CONTROL 0x2c
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#define DWCMSHC_CARD_IS_EMMC BIT(0)
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#define DWCMSHC_ENHANCED_STROBE BIT(8)
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#define DWCMSHC_EMMC_ATCTRL 0x40
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/* Rockchip specific Registers */
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#define DWCMSHC_EMMC_DLL_CTRL 0x800
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#define DWCMSHC_EMMC_DLL_RXCLK 0x804
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#define DWCMSHC_EMMC_DLL_TXCLK 0x808
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#define DWCMSHC_EMMC_DLL_STRBIN 0x80c
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#define DECMSHC_EMMC_DLL_CMDOUT 0x810
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#define DWCMSHC_EMMC_DLL_STATUS0 0x840
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#define DWCMSHC_EMMC_DLL_START BIT(0)
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#define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
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#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
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#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
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#define DWCMSHC_EMMC_DLL_START_POINT 16
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#define DWCMSHC_EMMC_DLL_INC 8
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#define DWCMSHC_EMMC_DLL_BYPASS BIT(24)
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#define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
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#define DLL_TXCLK_TAPNUM_DEFAULT 0x10
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#define DLL_TXCLK_TAPNUM_90_DEGREES 0xA
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#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
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#define DLL_STRBIN_TAPNUM_DEFAULT 0x8
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#define DLL_STRBIN_TAPNUM_FROM_SW BIT(24)
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#define DLL_STRBIN_DELAY_NUM_SEL BIT(26)
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#define DLL_STRBIN_DELAY_NUM_OFFSET 16
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#define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16
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#define DLL_RXCLK_NO_INVERTER 1
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#define DLL_RXCLK_INVERTER 0
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#define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8
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#define DLL_RXCLK_ORI_GATE BIT(31)
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#define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24)
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#define DLL_CMDOUT_SRC_CLK_NEG BIT(28)
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#define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)
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#define DLL_LOCK_WO_TMOUT(x) \
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((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
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(((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
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#define RK35xx_MAX_CLKS 3
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#define BOUNDARY_OK(addr, len) \
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((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
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enum dwcmshc_rk_type {
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DWCMSHC_RK3568,
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DWCMSHC_RK3588,
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};
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struct rk35xx_priv {
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/* Rockchip specified optional clocks */
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struct clk_bulk_data rockchip_clks[RK35xx_MAX_CLKS];
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struct reset_control *reset;
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enum dwcmshc_rk_type devtype;
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u8 txclk_tapnum;
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};
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struct dwcmshc_priv {
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struct clk *bus_clk;
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int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA reg */
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void *priv; /* pointer to SoC private stuff */
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};
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/*
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* If DMA addr spans 128MB boundary, we split the DMA transfer into two
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* so that each DMA transfer doesn't exceed the boundary.
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*/
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static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
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dma_addr_t addr, int len, unsigned int cmd)
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{
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int tmplen, offset;
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if (likely(!len || BOUNDARY_OK(addr, len))) {
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sdhci_adma_write_desc(host, desc, addr, len, cmd);
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return;
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}
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offset = addr & (SZ_128M - 1);
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tmplen = SZ_128M - offset;
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sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
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addr += tmplen;
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len -= tmplen;
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sdhci_adma_write_desc(host, desc, addr, len, cmd);
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}
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static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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if (pltfm_host->clk)
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return sdhci_pltfm_clk_get_max_clock(host);
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else
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return pltfm_host->clock;
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}
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static unsigned int rk35xx_get_max_clock(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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return clk_round_rate(pltfm_host->clk, ULONG_MAX);
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}
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static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
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struct mmc_request *mrq)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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/*
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* No matter V4 is enabled or not, ARGUMENT2 register is 32-bit
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* block count register which doesn't support stuff bits of
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* CMD23 argument on dwcmsch host controller.
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*/
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if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF))
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host->flags &= ~SDHCI_AUTO_CMD23;
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else
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host->flags |= SDHCI_AUTO_CMD23;
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}
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static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq)
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{
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dwcmshc_check_auto_cmd23(mmc, mrq);
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sdhci_request(mmc, mrq);
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}
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static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
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unsigned int timing)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
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u16 ctrl, ctrl_2;
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ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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/* Select Bus Speed Mode for host */
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ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
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if ((timing == MMC_TIMING_MMC_HS200) ||
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(timing == MMC_TIMING_UHS_SDR104))
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ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
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else if (timing == MMC_TIMING_UHS_SDR12)
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ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
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else if ((timing == MMC_TIMING_UHS_SDR25) ||
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(timing == MMC_TIMING_MMC_HS))
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ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
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else if (timing == MMC_TIMING_UHS_SDR50)
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ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
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else if ((timing == MMC_TIMING_UHS_DDR50) ||
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(timing == MMC_TIMING_MMC_DDR52))
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ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
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else if (timing == MMC_TIMING_MMC_HS400) {
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/* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
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ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
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ctrl |= DWCMSHC_CARD_IS_EMMC;
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sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
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ctrl_2 |= DWCMSHC_CTRL_HS400;
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}
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sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
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}
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static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc,
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struct mmc_ios *ios)
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{
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u32 vendor;
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struct sdhci_host *host = mmc_priv(mmc);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
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int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL;
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vendor = sdhci_readl(host, reg);
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if (ios->enhanced_strobe)
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vendor |= DWCMSHC_ENHANCED_STROBE;
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else
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vendor &= ~DWCMSHC_ENHANCED_STROBE;
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sdhci_writel(host, vendor, reg);
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}
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static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
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struct rk35xx_priv *priv = dwc_priv->priv;
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u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
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u32 extra, reg;
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int err;
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host->mmc->actual_clock = 0;
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if (clock == 0) {
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/* Disable interface clock at initial state. */
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sdhci_set_clock(host, clock);
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return;
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}
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/* Rockchip platform only support 375KHz for identify mode */
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if (clock <= 400000)
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clock = 375000;
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err = clk_set_rate(pltfm_host->clk, clock);
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if (err)
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dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);
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sdhci_set_clock(host, clock);
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/* Disable cmd conflict check */
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reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3;
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extra = sdhci_readl(host, reg);
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extra &= ~BIT(0);
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sdhci_writel(host, extra, reg);
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if (clock <= 52000000) {
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/*
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* Disable DLL and reset both of sample and drive clock.
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* The bypass bit and start bit need to be set if DLL is not locked.
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*/
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sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL);
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sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
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sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
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sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
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/*
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* Before switching to hs400es mode, the driver will enable
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* enhanced strobe first. PHY needs to configure the parameters
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* of enhanced strobe first.
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*/
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extra = DWCMSHC_EMMC_DLL_DLYENA |
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DLL_STRBIN_DELAY_NUM_SEL |
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DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
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return;
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}
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/* Reset DLL */
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sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL);
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udelay(1);
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sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL);
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/*
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* We shouldn't set DLL_RXCLK_NO_INVERTER for identify mode but
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* we must set it in higher speed mode.
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*/
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extra = DWCMSHC_EMMC_DLL_DLYENA;
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if (priv->devtype == DWCMSHC_RK3568)
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extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
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/* Init DLL settings */
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extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT |
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0x2 << DWCMSHC_EMMC_DLL_INC |
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DWCMSHC_EMMC_DLL_START;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
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err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
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extra, DLL_LOCK_WO_TMOUT(extra), 1,
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500 * USEC_PER_MSEC);
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if (err) {
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dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n");
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return;
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}
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extra = 0x1 << 16 | /* tune clock stop en */
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0x3 << 17 | /* pre-change delay */
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0x3 << 19; /* post-change delay */
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sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
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if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
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host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
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txclk_tapnum = priv->txclk_tapnum;
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if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
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txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES;
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extra = DLL_CMDOUT_SRC_CLK_NEG |
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DLL_CMDOUT_EN_SRC_CLK_NEG |
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DWCMSHC_EMMC_DLL_DLYENA |
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DLL_CMDOUT_TAPNUM_90_DEGREES |
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DLL_CMDOUT_TAPNUM_FROM_SW;
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sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
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}
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extra = DWCMSHC_EMMC_DLL_DLYENA |
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DLL_TXCLK_TAPNUM_FROM_SW |
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DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL |
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txclk_tapnum;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
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extra = DWCMSHC_EMMC_DLL_DLYENA |
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DLL_STRBIN_TAPNUM_DEFAULT |
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DLL_STRBIN_TAPNUM_FROM_SW;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
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}
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static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
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struct rk35xx_priv *priv = dwc_priv->priv;
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if (mask & SDHCI_RESET_ALL && priv->reset) {
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reset_control_assert(priv->reset);
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udelay(1);
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reset_control_deassert(priv->reset);
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}
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sdhci_reset(host, mask);
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}
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static const struct sdhci_ops sdhci_dwcmshc_ops = {
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.set_clock = sdhci_set_clock,
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.set_bus_width = sdhci_set_bus_width,
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.set_uhs_signaling = dwcmshc_set_uhs_signaling,
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.get_max_clock = dwcmshc_get_max_clock,
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.reset = sdhci_reset,
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.adma_write_desc = dwcmshc_adma_write_desc,
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};
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static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = {
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.set_clock = dwcmshc_rk3568_set_clock,
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.set_bus_width = sdhci_set_bus_width,
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.set_uhs_signaling = dwcmshc_set_uhs_signaling,
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.get_max_clock = rk35xx_get_max_clock,
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.reset = rk35xx_sdhci_reset,
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.adma_write_desc = dwcmshc_adma_write_desc,
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};
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static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
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.ops = &sdhci_dwcmshc_ops,
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.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
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.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
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};
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#ifdef CONFIG_ACPI
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static const struct sdhci_pltfm_data sdhci_dwcmshc_bf3_pdata = {
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.ops = &sdhci_dwcmshc_ops,
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.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
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.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
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SDHCI_QUIRK2_ACMD23_BROKEN,
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};
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#endif
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static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = {
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.ops = &sdhci_dwcmshc_rk35xx_ops,
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.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
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SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
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.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
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SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
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};
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static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
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{
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int err;
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struct rk35xx_priv *priv = dwc_priv->priv;
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priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));
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if (IS_ERR(priv->reset)) {
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err = PTR_ERR(priv->reset);
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dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err);
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return err;
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}
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priv->rockchip_clks[0].id = "axi";
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priv->rockchip_clks[1].id = "block";
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priv->rockchip_clks[2].id = "timer";
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err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK35xx_MAX_CLKS,
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priv->rockchip_clks);
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if (err) {
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dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err);
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return err;
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}
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err = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, priv->rockchip_clks);
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if (err) {
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dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err);
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return err;
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}
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if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum",
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&priv->txclk_tapnum))
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priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
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/* Disable cmd conflict check */
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sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
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/* Reset previous settings */
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sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
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sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
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return 0;
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}
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static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
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{
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/*
|
|
* Don't support highspeed bus mode with low clk speed as we
|
|
* cannot use DLL for this condition.
|
|
*/
|
|
if (host->mmc->f_max <= 52000000) {
|
|
dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n",
|
|
host->mmc->f_max);
|
|
host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400);
|
|
host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR);
|
|
}
|
|
}
|
|
|
|
static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
|
|
{
|
|
.compatible = "rockchip,rk3588-dwcmshc",
|
|
.data = &sdhci_dwcmshc_rk35xx_pdata,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3568-dwcmshc",
|
|
.data = &sdhci_dwcmshc_rk35xx_pdata,
|
|
},
|
|
{
|
|
.compatible = "snps,dwcmshc-sdhci",
|
|
.data = &sdhci_dwcmshc_pdata,
|
|
},
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
|
|
|
|
#ifdef CONFIG_ACPI
|
|
static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = {
|
|
{
|
|
.id = "MLNXBF30",
|
|
.driver_data = (kernel_ulong_t)&sdhci_dwcmshc_bf3_pdata,
|
|
},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(acpi, sdhci_dwcmshc_acpi_ids);
|
|
#endif
|
|
|
|
static int dwcmshc_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct sdhci_pltfm_host *pltfm_host;
|
|
struct sdhci_host *host;
|
|
struct dwcmshc_priv *priv;
|
|
struct rk35xx_priv *rk_priv = NULL;
|
|
const struct sdhci_pltfm_data *pltfm_data;
|
|
int err;
|
|
u32 extra;
|
|
|
|
pltfm_data = device_get_match_data(&pdev->dev);
|
|
if (!pltfm_data) {
|
|
dev_err(&pdev->dev, "Error: No device match data found\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
host = sdhci_pltfm_init(pdev, pltfm_data,
|
|
sizeof(struct dwcmshc_priv));
|
|
if (IS_ERR(host))
|
|
return PTR_ERR(host);
|
|
|
|
/*
|
|
* extra adma table cnt for cross 128M boundary handling.
|
|
*/
|
|
extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M);
|
|
if (extra > SDHCI_MAX_SEGS)
|
|
extra = SDHCI_MAX_SEGS;
|
|
host->adma_table_cnt += extra;
|
|
|
|
pltfm_host = sdhci_priv(host);
|
|
priv = sdhci_pltfm_priv(pltfm_host);
|
|
|
|
if (dev->of_node) {
|
|
pltfm_host->clk = devm_clk_get(dev, "core");
|
|
if (IS_ERR(pltfm_host->clk)) {
|
|
err = PTR_ERR(pltfm_host->clk);
|
|
dev_err(dev, "failed to get core clk: %d\n", err);
|
|
goto free_pltfm;
|
|
}
|
|
err = clk_prepare_enable(pltfm_host->clk);
|
|
if (err)
|
|
goto free_pltfm;
|
|
|
|
priv->bus_clk = devm_clk_get(dev, "bus");
|
|
if (!IS_ERR(priv->bus_clk))
|
|
clk_prepare_enable(priv->bus_clk);
|
|
}
|
|
|
|
err = mmc_of_parse(host->mmc);
|
|
if (err)
|
|
goto err_clk;
|
|
|
|
sdhci_get_of_property(pdev);
|
|
|
|
priv->vendor_specific_area1 =
|
|
sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK;
|
|
|
|
host->mmc_host_ops.request = dwcmshc_request;
|
|
host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;
|
|
|
|
if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) {
|
|
rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL);
|
|
if (!rk_priv) {
|
|
err = -ENOMEM;
|
|
goto err_clk;
|
|
}
|
|
|
|
if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3588-dwcmshc"))
|
|
rk_priv->devtype = DWCMSHC_RK3588;
|
|
else
|
|
rk_priv->devtype = DWCMSHC_RK3568;
|
|
|
|
priv->priv = rk_priv;
|
|
|
|
err = dwcmshc_rk35xx_init(host, priv);
|
|
if (err)
|
|
goto err_clk;
|
|
}
|
|
|
|
#ifdef CONFIG_ACPI
|
|
if (pltfm_data == &sdhci_dwcmshc_bf3_pdata)
|
|
sdhci_enable_v4_mode(host);
|
|
#endif
|
|
|
|
host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
|
|
|
|
err = sdhci_setup_host(host);
|
|
if (err)
|
|
goto err_clk;
|
|
|
|
if (rk_priv)
|
|
dwcmshc_rk35xx_postinit(host, priv);
|
|
|
|
err = __sdhci_add_host(host);
|
|
if (err)
|
|
goto err_setup_host;
|
|
|
|
return 0;
|
|
|
|
err_setup_host:
|
|
sdhci_cleanup_host(host);
|
|
err_clk:
|
|
clk_disable_unprepare(pltfm_host->clk);
|
|
clk_disable_unprepare(priv->bus_clk);
|
|
if (rk_priv)
|
|
clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
|
|
rk_priv->rockchip_clks);
|
|
free_pltfm:
|
|
sdhci_pltfm_free(pdev);
|
|
return err;
|
|
}
|
|
|
|
static int dwcmshc_remove(struct platform_device *pdev)
|
|
{
|
|
struct sdhci_host *host = platform_get_drvdata(pdev);
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
|
|
struct rk35xx_priv *rk_priv = priv->priv;
|
|
|
|
sdhci_remove_host(host, 0);
|
|
|
|
clk_disable_unprepare(pltfm_host->clk);
|
|
clk_disable_unprepare(priv->bus_clk);
|
|
if (rk_priv)
|
|
clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
|
|
rk_priv->rockchip_clks);
|
|
sdhci_pltfm_free(pdev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int dwcmshc_suspend(struct device *dev)
|
|
{
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
|
|
struct rk35xx_priv *rk_priv = priv->priv;
|
|
int ret;
|
|
|
|
ret = sdhci_suspend_host(host);
|
|
if (ret)
|
|
return ret;
|
|
|
|
clk_disable_unprepare(pltfm_host->clk);
|
|
if (!IS_ERR(priv->bus_clk))
|
|
clk_disable_unprepare(priv->bus_clk);
|
|
|
|
if (rk_priv)
|
|
clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
|
|
rk_priv->rockchip_clks);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dwcmshc_resume(struct device *dev)
|
|
{
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
|
|
struct rk35xx_priv *rk_priv = priv->priv;
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(pltfm_host->clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (!IS_ERR(priv->bus_clk)) {
|
|
ret = clk_prepare_enable(priv->bus_clk);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
if (rk_priv) {
|
|
ret = clk_bulk_prepare_enable(RK35xx_MAX_CLKS,
|
|
rk_priv->rockchip_clks);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return sdhci_resume_host(host);
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(dwcmshc_pmops, dwcmshc_suspend, dwcmshc_resume);
|
|
|
|
static struct platform_driver sdhci_dwcmshc_driver = {
|
|
.driver = {
|
|
.name = "sdhci-dwcmshc",
|
|
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
|
|
.of_match_table = sdhci_dwcmshc_dt_ids,
|
|
.acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids),
|
|
.pm = &dwcmshc_pmops,
|
|
},
|
|
.probe = dwcmshc_probe,
|
|
.remove = dwcmshc_remove,
|
|
};
|
|
module_platform_driver(sdhci_dwcmshc_driver);
|
|
|
|
MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC");
|
|
MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
|
|
MODULE_LICENSE("GPL v2");
|