625 lines
21 KiB
C
625 lines
21 KiB
C
/* typhoon.h: chip info for the 3Com 3CR990 family of controllers */
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/*
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Written 2002-2003 by David Dillow <dave@thedillows.org>
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This software may be used and distributed according to the terms of
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the GNU General Public License (GPL), incorporated herein by reference.
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Drivers based on or derived from this code fall under the GPL and must
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retain the authorship, copyright and license notice. This file is not
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a complete program and may only be used when the entire operating
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system is licensed under the GPL.
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This software is available on a public web site. It may enable
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cryptographic capabilities of the 3Com hardware, and may be
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exported from the United States under License Exception "TSU"
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pursuant to 15 C.F.R. Section 740.13(e).
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This work was funded by the National Library of Medicine under
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the Department of Energy project number 0274DD06D1 and NLM project
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number Y1-LM-2015-01.
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*/
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/* All Typhoon ring positions are specificed in bytes, and point to the
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* first "clean" entry in the ring -- ie the next entry we use for whatever
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* purpose.
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*/
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/* The Typhoon basic ring
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* ringBase: where this ring lives (our virtual address)
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* lastWrite: the next entry we'll use
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*/
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struct basic_ring {
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u8 *ringBase;
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u32 lastWrite;
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};
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/* The Typhoon transmit ring -- same as a basic ring, plus:
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* lastRead: where we're at in regard to cleaning up the ring
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* writeRegister: register to use for writing (different for Hi & Lo rings)
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*/
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struct transmit_ring {
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u8 *ringBase;
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u32 lastWrite;
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u32 lastRead;
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int writeRegister;
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};
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/* The host<->Typhoon ring index structure
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* This indicates the current positions in the rings
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*
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* All values must be in little endian format for the 3XP
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*
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* rxHiCleared: entry we've cleared to in the Hi receive ring
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* rxLoCleared: entry we've cleared to in the Lo receive ring
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* rxBuffReady: next entry we'll put a free buffer in
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* respCleared: entry we've cleared to in the response ring
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*
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* txLoCleared: entry the NIC has cleared to in the Lo transmit ring
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* txHiCleared: entry the NIC has cleared to in the Hi transmit ring
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* rxLoReady: entry the NIC has filled to in the Lo receive ring
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* rxBuffCleared: entry the NIC has cleared in the free buffer ring
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* cmdCleared: entry the NIC has cleared in the command ring
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* respReady: entry the NIC has filled to in the response ring
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* rxHiReady: entry the NIC has filled to in the Hi receive ring
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*/
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struct typhoon_indexes {
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/* The first four are written by the host, and read by the NIC */
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volatile __le32 rxHiCleared;
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volatile __le32 rxLoCleared;
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volatile __le32 rxBuffReady;
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volatile __le32 respCleared;
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/* The remaining are written by the NIC, and read by the host */
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volatile __le32 txLoCleared;
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volatile __le32 txHiCleared;
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volatile __le32 rxLoReady;
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volatile __le32 rxBuffCleared;
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volatile __le32 cmdCleared;
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volatile __le32 respReady;
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volatile __le32 rxHiReady;
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} __packed;
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/* The host<->Typhoon interface
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* Our means of communicating where things are
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*
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* All values must be in little endian format for the 3XP
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*
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* ringIndex: 64 bit bus address of the index structure
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* txLoAddr: 64 bit bus address of the Lo transmit ring
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* txLoSize: size (in bytes) of the Lo transmit ring
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* txHi*: as above for the Hi priority transmit ring
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* rxLo*: as above for the Lo priority receive ring
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* rxBuff*: as above for the free buffer ring
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* cmd*: as above for the command ring
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* resp*: as above for the response ring
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* zeroAddr: 64 bit bus address of a zero word (for DMA)
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* rxHi*: as above for the Hi Priority receive ring
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*
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* While there is room for 64 bit addresses, current versions of the 3XP
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* only do 32 bit addresses, so the *Hi for each of the above will always
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* be zero.
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*/
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struct typhoon_interface {
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__le32 ringIndex;
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__le32 ringIndexHi;
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__le32 txLoAddr;
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__le32 txLoAddrHi;
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__le32 txLoSize;
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__le32 txHiAddr;
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__le32 txHiAddrHi;
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__le32 txHiSize;
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__le32 rxLoAddr;
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__le32 rxLoAddrHi;
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__le32 rxLoSize;
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__le32 rxBuffAddr;
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__le32 rxBuffAddrHi;
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__le32 rxBuffSize;
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__le32 cmdAddr;
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__le32 cmdAddrHi;
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__le32 cmdSize;
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__le32 respAddr;
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__le32 respAddrHi;
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__le32 respSize;
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__le32 zeroAddr;
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__le32 zeroAddrHi;
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__le32 rxHiAddr;
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__le32 rxHiAddrHi;
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__le32 rxHiSize;
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} __packed;
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/* The Typhoon transmit/fragment descriptor
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*
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* A packet is described by a packet descriptor, followed by option descriptors,
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* if any, then one or more fragment descriptors.
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*
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* Packet descriptor:
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* flags: Descriptor type
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* len:i zero, or length of this packet
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* addr*: 8 bytes of opaque data to the firmware -- for skb pointer
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* processFlags: Determine offload tasks to perform on this packet.
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*
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* Fragment descriptor:
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* flags: Descriptor type
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* len:i length of this fragment
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* addr: low bytes of DMA address for this part of the packet
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* addrHi: hi bytes of DMA address for this part of the packet
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* processFlags: must be zero
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*
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* TYPHOON_DESC_VALID is not mentioned in their docs, but their Linux
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* driver uses it.
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*/
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struct tx_desc {
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u8 flags;
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#define TYPHOON_TYPE_MASK 0x07
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#define TYPHOON_FRAG_DESC 0x00
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#define TYPHOON_TX_DESC 0x01
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#define TYPHOON_CMD_DESC 0x02
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#define TYPHOON_OPT_DESC 0x03
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#define TYPHOON_RX_DESC 0x04
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#define TYPHOON_RESP_DESC 0x05
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#define TYPHOON_OPT_TYPE_MASK 0xf0
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#define TYPHOON_OPT_IPSEC 0x00
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#define TYPHOON_OPT_TCP_SEG 0x10
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#define TYPHOON_CMD_RESPOND 0x40
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#define TYPHOON_RESP_ERROR 0x40
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#define TYPHOON_RX_ERROR 0x40
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#define TYPHOON_DESC_VALID 0x80
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u8 numDesc;
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__le16 len;
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union {
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struct {
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__le32 addr;
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__le32 addrHi;
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} frag;
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u64 tx_addr; /* opaque for hardware, for TX_DESC */
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};
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__le32 processFlags;
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#define TYPHOON_TX_PF_NO_CRC cpu_to_le32(0x00000001)
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#define TYPHOON_TX_PF_IP_CHKSUM cpu_to_le32(0x00000002)
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#define TYPHOON_TX_PF_TCP_CHKSUM cpu_to_le32(0x00000004)
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#define TYPHOON_TX_PF_TCP_SEGMENT cpu_to_le32(0x00000008)
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#define TYPHOON_TX_PF_INSERT_VLAN cpu_to_le32(0x00000010)
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#define TYPHOON_TX_PF_IPSEC cpu_to_le32(0x00000020)
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#define TYPHOON_TX_PF_VLAN_PRIORITY cpu_to_le32(0x00000040)
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#define TYPHOON_TX_PF_UDP_CHKSUM cpu_to_le32(0x00000080)
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#define TYPHOON_TX_PF_PAD_FRAME cpu_to_le32(0x00000100)
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#define TYPHOON_TX_PF_RESERVED cpu_to_le32(0x00000e00)
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#define TYPHOON_TX_PF_VLAN_MASK cpu_to_le32(0x0ffff000)
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#define TYPHOON_TX_PF_INTERNAL cpu_to_le32(0xf0000000)
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#define TYPHOON_TX_PF_VLAN_TAG_SHIFT 12
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} __packed;
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/* The TCP Segmentation offload option descriptor
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*
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* flags: descriptor type
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* numDesc: must be 1
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* mss_flags: bits 0-11 (little endian) are MSS, 12 is first TSO descriptor
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* 13 is list TSO descriptor, set both if only one TSO
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* respAddrLo: low bytes of address of the bytesTx field of this descriptor
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* bytesTx: total number of bytes in this TSO request
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* status: 0 on completion
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*/
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struct tcpopt_desc {
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u8 flags;
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u8 numDesc;
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__le16 mss_flags;
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#define TYPHOON_TSO_FIRST cpu_to_le16(0x1000)
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#define TYPHOON_TSO_LAST cpu_to_le16(0x2000)
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__le32 respAddrLo;
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__le32 bytesTx;
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__le32 status;
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} __packed;
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/* The IPSEC Offload descriptor
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*
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* flags: descriptor type
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* numDesc: must be 1
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* ipsecFlags: bit 0: 0 -- generate IV, 1 -- use supplied IV
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* sa1, sa2: Security Association IDs for this packet
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* reserved: set to 0
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*/
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struct ipsec_desc {
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u8 flags;
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u8 numDesc;
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__le16 ipsecFlags;
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#define TYPHOON_IPSEC_GEN_IV cpu_to_le16(0x0000)
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#define TYPHOON_IPSEC_USE_IV cpu_to_le16(0x0001)
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__le32 sa1;
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__le32 sa2;
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__le32 reserved;
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} __packed;
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/* The Typhoon receive descriptor (Updated by NIC)
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*
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* flags: Descriptor type, error indication
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* numDesc: Always zero
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* frameLen: the size of the packet received
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* addr: low 32 bytes of the virtual addr passed in for this buffer
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* addrHi: high 32 bytes of the virtual addr passed in for this buffer
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* rxStatus: Error if set in flags, otherwise result of offload processing
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* filterResults: results of filtering on packet, not used
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* ipsecResults: Results of IPSEC processing
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* vlanTag: the 801.2q TCI from the packet
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*/
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struct rx_desc {
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u8 flags;
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u8 numDesc;
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__le16 frameLen;
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u32 addr; /* opaque, comes from virtAddr */
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u32 addrHi; /* opaque, comes from virtAddrHi */
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__le32 rxStatus;
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#define TYPHOON_RX_ERR_INTERNAL cpu_to_le32(0x00000000)
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#define TYPHOON_RX_ERR_FIFO_UNDERRUN cpu_to_le32(0x00000001)
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#define TYPHOON_RX_ERR_BAD_SSD cpu_to_le32(0x00000002)
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#define TYPHOON_RX_ERR_RUNT cpu_to_le32(0x00000003)
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#define TYPHOON_RX_ERR_CRC cpu_to_le32(0x00000004)
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#define TYPHOON_RX_ERR_OVERSIZE cpu_to_le32(0x00000005)
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#define TYPHOON_RX_ERR_ALIGN cpu_to_le32(0x00000006)
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#define TYPHOON_RX_ERR_DRIBBLE cpu_to_le32(0x00000007)
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#define TYPHOON_RX_PROTO_MASK cpu_to_le32(0x00000003)
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#define TYPHOON_RX_PROTO_UNKNOWN cpu_to_le32(0x00000000)
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#define TYPHOON_RX_PROTO_IP cpu_to_le32(0x00000001)
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#define TYPHOON_RX_PROTO_IPX cpu_to_le32(0x00000002)
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#define TYPHOON_RX_VLAN cpu_to_le32(0x00000004)
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#define TYPHOON_RX_IP_FRAG cpu_to_le32(0x00000008)
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#define TYPHOON_RX_IPSEC cpu_to_le32(0x00000010)
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#define TYPHOON_RX_IP_CHK_FAIL cpu_to_le32(0x00000020)
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#define TYPHOON_RX_TCP_CHK_FAIL cpu_to_le32(0x00000040)
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#define TYPHOON_RX_UDP_CHK_FAIL cpu_to_le32(0x00000080)
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#define TYPHOON_RX_IP_CHK_GOOD cpu_to_le32(0x00000100)
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#define TYPHOON_RX_TCP_CHK_GOOD cpu_to_le32(0x00000200)
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#define TYPHOON_RX_UDP_CHK_GOOD cpu_to_le32(0x00000400)
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__le16 filterResults;
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#define TYPHOON_RX_FILTER_MASK cpu_to_le16(0x7fff)
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#define TYPHOON_RX_FILTERED cpu_to_le16(0x8000)
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__le16 ipsecResults;
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#define TYPHOON_RX_OUTER_AH_GOOD cpu_to_le16(0x0001)
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#define TYPHOON_RX_OUTER_ESP_GOOD cpu_to_le16(0x0002)
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#define TYPHOON_RX_INNER_AH_GOOD cpu_to_le16(0x0004)
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#define TYPHOON_RX_INNER_ESP_GOOD cpu_to_le16(0x0008)
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#define TYPHOON_RX_OUTER_AH_FAIL cpu_to_le16(0x0010)
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#define TYPHOON_RX_OUTER_ESP_FAIL cpu_to_le16(0x0020)
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#define TYPHOON_RX_INNER_AH_FAIL cpu_to_le16(0x0040)
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#define TYPHOON_RX_INNER_ESP_FAIL cpu_to_le16(0x0080)
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#define TYPHOON_RX_UNKNOWN_SA cpu_to_le16(0x0100)
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#define TYPHOON_RX_ESP_FORMAT_ERR cpu_to_le16(0x0200)
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__be32 vlanTag;
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} __packed;
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/* The Typhoon free buffer descriptor, used to give a buffer to the NIC
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*
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* physAddr: low 32 bits of the bus address of the buffer
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* physAddrHi: high 32 bits of the bus address of the buffer, always zero
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* virtAddr: low 32 bits of the skb address
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* virtAddrHi: high 32 bits of the skb address, always zero
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*
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* the virt* address is basically two 32 bit cookies, just passed back
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* from the NIC
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*/
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struct rx_free {
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__le32 physAddr;
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__le32 physAddrHi;
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u32 virtAddr;
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u32 virtAddrHi;
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} __packed;
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/* The Typhoon command descriptor, used for commands and responses
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*
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* flags: descriptor type
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* numDesc: number of descriptors following in this command/response,
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* ie, zero for a one descriptor command
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* cmd: the command
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* seqNo: sequence number (unused)
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* parm1: use varies by command
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* parm2: use varies by command
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* parm3: use varies by command
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*/
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struct cmd_desc {
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u8 flags;
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u8 numDesc;
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__le16 cmd;
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#define TYPHOON_CMD_TX_ENABLE cpu_to_le16(0x0001)
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#define TYPHOON_CMD_TX_DISABLE cpu_to_le16(0x0002)
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#define TYPHOON_CMD_RX_ENABLE cpu_to_le16(0x0003)
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#define TYPHOON_CMD_RX_DISABLE cpu_to_le16(0x0004)
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#define TYPHOON_CMD_SET_RX_FILTER cpu_to_le16(0x0005)
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#define TYPHOON_CMD_READ_STATS cpu_to_le16(0x0007)
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#define TYPHOON_CMD_XCVR_SELECT cpu_to_le16(0x0013)
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#define TYPHOON_CMD_SET_MAX_PKT_SIZE cpu_to_le16(0x001a)
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#define TYPHOON_CMD_READ_MEDIA_STATUS cpu_to_le16(0x001b)
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#define TYPHOON_CMD_GOTO_SLEEP cpu_to_le16(0x0023)
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#define TYPHOON_CMD_SET_MULTICAST_HASH cpu_to_le16(0x0025)
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#define TYPHOON_CMD_SET_MAC_ADDRESS cpu_to_le16(0x0026)
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#define TYPHOON_CMD_READ_MAC_ADDRESS cpu_to_le16(0x0027)
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#define TYPHOON_CMD_VLAN_TYPE_WRITE cpu_to_le16(0x002b)
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#define TYPHOON_CMD_CREATE_SA cpu_to_le16(0x0034)
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#define TYPHOON_CMD_DELETE_SA cpu_to_le16(0x0035)
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#define TYPHOON_CMD_READ_VERSIONS cpu_to_le16(0x0043)
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#define TYPHOON_CMD_IRQ_COALESCE_CTRL cpu_to_le16(0x0045)
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#define TYPHOON_CMD_ENABLE_WAKE_EVENTS cpu_to_le16(0x0049)
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#define TYPHOON_CMD_SET_OFFLOAD_TASKS cpu_to_le16(0x004f)
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#define TYPHOON_CMD_HELLO_RESP cpu_to_le16(0x0057)
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#define TYPHOON_CMD_HALT cpu_to_le16(0x005d)
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#define TYPHOON_CMD_READ_IPSEC_INFO cpu_to_le16(0x005e)
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#define TYPHOON_CMD_GET_IPSEC_ENABLE cpu_to_le16(0x0067)
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#define TYPHOON_CMD_GET_CMD_LVL cpu_to_le16(0x0069)
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u16 seqNo;
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__le16 parm1;
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__le32 parm2;
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__le32 parm3;
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} __packed;
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/* The Typhoon response descriptor, see command descriptor for details
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*/
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struct resp_desc {
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u8 flags;
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u8 numDesc;
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__le16 cmd;
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__le16 seqNo;
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__le16 parm1;
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__le32 parm2;
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__le32 parm3;
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} __packed;
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#define INIT_COMMAND_NO_RESPONSE(x, command) \
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do { struct cmd_desc *_ptr = (x); \
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memset(_ptr, 0, sizeof(struct cmd_desc)); \
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_ptr->flags = TYPHOON_CMD_DESC | TYPHOON_DESC_VALID; \
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_ptr->cmd = command; \
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} while (0)
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/* We set seqNo to 1 if we're expecting a response from this command */
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#define INIT_COMMAND_WITH_RESPONSE(x, command) \
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do { struct cmd_desc *_ptr = (x); \
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memset(_ptr, 0, sizeof(struct cmd_desc)); \
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_ptr->flags = TYPHOON_CMD_RESPOND | TYPHOON_CMD_DESC; \
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_ptr->flags |= TYPHOON_DESC_VALID; \
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_ptr->cmd = command; \
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_ptr->seqNo = 1; \
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} while (0)
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/* TYPHOON_CMD_SET_RX_FILTER filter bits (cmd.parm1)
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*/
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#define TYPHOON_RX_FILTER_DIRECTED cpu_to_le16(0x0001)
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#define TYPHOON_RX_FILTER_ALL_MCAST cpu_to_le16(0x0002)
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#define TYPHOON_RX_FILTER_BROADCAST cpu_to_le16(0x0004)
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#define TYPHOON_RX_FILTER_PROMISCOUS cpu_to_le16(0x0008)
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#define TYPHOON_RX_FILTER_MCAST_HASH cpu_to_le16(0x0010)
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/* TYPHOON_CMD_READ_STATS response format
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*/
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struct stats_resp {
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u8 flags;
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u8 numDesc;
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__le16 cmd;
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__le16 seqNo;
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__le16 unused;
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__le32 txPackets;
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__le64 txBytes;
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__le32 txDeferred;
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__le32 txLateCollisions;
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__le32 txCollisions;
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__le32 txCarrierLost;
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__le32 txMultipleCollisions;
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__le32 txExcessiveCollisions;
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__le32 txFifoUnderruns;
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__le32 txMulticastTxOverflows;
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__le32 txFiltered;
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__le32 rxPacketsGood;
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__le64 rxBytesGood;
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__le32 rxFifoOverruns;
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__le32 BadSSD;
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__le32 rxCrcErrors;
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__le32 rxOversized;
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__le32 rxBroadcast;
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__le32 rxMulticast;
|
|
__le32 rxOverflow;
|
|
__le32 rxFiltered;
|
|
__le32 linkStatus;
|
|
#define TYPHOON_LINK_STAT_MASK cpu_to_le32(0x00000001)
|
|
#define TYPHOON_LINK_GOOD cpu_to_le32(0x00000001)
|
|
#define TYPHOON_LINK_BAD cpu_to_le32(0x00000000)
|
|
#define TYPHOON_LINK_SPEED_MASK cpu_to_le32(0x00000002)
|
|
#define TYPHOON_LINK_100MBPS cpu_to_le32(0x00000002)
|
|
#define TYPHOON_LINK_10MBPS cpu_to_le32(0x00000000)
|
|
#define TYPHOON_LINK_DUPLEX_MASK cpu_to_le32(0x00000004)
|
|
#define TYPHOON_LINK_FULL_DUPLEX cpu_to_le32(0x00000004)
|
|
#define TYPHOON_LINK_HALF_DUPLEX cpu_to_le32(0x00000000)
|
|
__le32 unused2;
|
|
__le32 unused3;
|
|
} __packed;
|
|
|
|
/* TYPHOON_CMD_XCVR_SELECT xcvr values (resp.parm1)
|
|
*/
|
|
#define TYPHOON_XCVR_10HALF cpu_to_le16(0x0000)
|
|
#define TYPHOON_XCVR_10FULL cpu_to_le16(0x0001)
|
|
#define TYPHOON_XCVR_100HALF cpu_to_le16(0x0002)
|
|
#define TYPHOON_XCVR_100FULL cpu_to_le16(0x0003)
|
|
#define TYPHOON_XCVR_AUTONEG cpu_to_le16(0x0004)
|
|
|
|
/* TYPHOON_CMD_READ_MEDIA_STATUS (resp.parm1)
|
|
*/
|
|
#define TYPHOON_MEDIA_STAT_CRC_STRIP_DISABLE cpu_to_le16(0x0004)
|
|
#define TYPHOON_MEDIA_STAT_COLLISION_DETECT cpu_to_le16(0x0010)
|
|
#define TYPHOON_MEDIA_STAT_CARRIER_SENSE cpu_to_le16(0x0020)
|
|
#define TYPHOON_MEDIA_STAT_POLARITY_REV cpu_to_le16(0x0400)
|
|
#define TYPHOON_MEDIA_STAT_NO_LINK cpu_to_le16(0x0800)
|
|
|
|
/* TYPHOON_CMD_SET_MULTICAST_HASH enable values (cmd.parm1)
|
|
*/
|
|
#define TYPHOON_MCAST_HASH_DISABLE cpu_to_le16(0x0000)
|
|
#define TYPHOON_MCAST_HASH_ENABLE cpu_to_le16(0x0001)
|
|
#define TYPHOON_MCAST_HASH_SET cpu_to_le16(0x0002)
|
|
|
|
/* TYPHOON_CMD_CREATE_SA descriptor and settings
|
|
*/
|
|
struct sa_descriptor {
|
|
u8 flags;
|
|
u8 numDesc;
|
|
u16 cmd;
|
|
u16 seqNo;
|
|
u16 mode;
|
|
#define TYPHOON_SA_MODE_NULL cpu_to_le16(0x0000)
|
|
#define TYPHOON_SA_MODE_AH cpu_to_le16(0x0001)
|
|
#define TYPHOON_SA_MODE_ESP cpu_to_le16(0x0002)
|
|
u8 hashFlags;
|
|
#define TYPHOON_SA_HASH_ENABLE 0x01
|
|
#define TYPHOON_SA_HASH_SHA1 0x02
|
|
#define TYPHOON_SA_HASH_MD5 0x04
|
|
u8 direction;
|
|
#define TYPHOON_SA_DIR_RX 0x00
|
|
#define TYPHOON_SA_DIR_TX 0x01
|
|
u8 encryptionFlags;
|
|
#define TYPHOON_SA_ENCRYPT_ENABLE 0x01
|
|
#define TYPHOON_SA_ENCRYPT_DES 0x02
|
|
#define TYPHOON_SA_ENCRYPT_3DES 0x00
|
|
#define TYPHOON_SA_ENCRYPT_3DES_2KEY 0x00
|
|
#define TYPHOON_SA_ENCRYPT_3DES_3KEY 0x04
|
|
#define TYPHOON_SA_ENCRYPT_CBC 0x08
|
|
#define TYPHOON_SA_ENCRYPT_ECB 0x00
|
|
u8 specifyIndex;
|
|
#define TYPHOON_SA_SPECIFY_INDEX 0x01
|
|
#define TYPHOON_SA_GENERATE_INDEX 0x00
|
|
u32 SPI;
|
|
u32 destAddr;
|
|
u32 destMask;
|
|
u8 integKey[20];
|
|
u8 confKey[24];
|
|
u32 index;
|
|
u32 unused;
|
|
u32 unused2;
|
|
} __packed;
|
|
|
|
/* TYPHOON_CMD_SET_OFFLOAD_TASKS bits (cmd.parm2 (Tx) & cmd.parm3 (Rx))
|
|
* This is all for IPv4.
|
|
*/
|
|
#define TYPHOON_OFFLOAD_TCP_CHKSUM cpu_to_le32(0x00000002)
|
|
#define TYPHOON_OFFLOAD_UDP_CHKSUM cpu_to_le32(0x00000004)
|
|
#define TYPHOON_OFFLOAD_IP_CHKSUM cpu_to_le32(0x00000008)
|
|
#define TYPHOON_OFFLOAD_IPSEC cpu_to_le32(0x00000010)
|
|
#define TYPHOON_OFFLOAD_BCAST_THROTTLE cpu_to_le32(0x00000020)
|
|
#define TYPHOON_OFFLOAD_DHCP_PREVENT cpu_to_le32(0x00000040)
|
|
#define TYPHOON_OFFLOAD_VLAN cpu_to_le32(0x00000080)
|
|
#define TYPHOON_OFFLOAD_FILTERING cpu_to_le32(0x00000100)
|
|
#define TYPHOON_OFFLOAD_TCP_SEGMENT cpu_to_le32(0x00000200)
|
|
|
|
/* TYPHOON_CMD_ENABLE_WAKE_EVENTS bits (cmd.parm1)
|
|
*/
|
|
#define TYPHOON_WAKE_MAGIC_PKT cpu_to_le16(0x01)
|
|
#define TYPHOON_WAKE_LINK_EVENT cpu_to_le16(0x02)
|
|
#define TYPHOON_WAKE_ICMP_ECHO cpu_to_le16(0x04)
|
|
#define TYPHOON_WAKE_ARP cpu_to_le16(0x08)
|
|
|
|
/* These are used to load the firmware image on the NIC
|
|
*/
|
|
struct typhoon_file_header {
|
|
u8 tag[8];
|
|
__le32 version;
|
|
__le32 numSections;
|
|
__le32 startAddr;
|
|
__le32 hmacDigest[5];
|
|
} __packed;
|
|
|
|
struct typhoon_section_header {
|
|
__le32 len;
|
|
u16 checksum;
|
|
u16 reserved;
|
|
__le32 startAddr;
|
|
} __packed;
|
|
|
|
/* The Typhoon Register offsets
|
|
*/
|
|
#define TYPHOON_REG_SOFT_RESET 0x00
|
|
#define TYPHOON_REG_INTR_STATUS 0x04
|
|
#define TYPHOON_REG_INTR_ENABLE 0x08
|
|
#define TYPHOON_REG_INTR_MASK 0x0c
|
|
#define TYPHOON_REG_SELF_INTERRUPT 0x10
|
|
#define TYPHOON_REG_HOST2ARM7 0x14
|
|
#define TYPHOON_REG_HOST2ARM6 0x18
|
|
#define TYPHOON_REG_HOST2ARM5 0x1c
|
|
#define TYPHOON_REG_HOST2ARM4 0x20
|
|
#define TYPHOON_REG_HOST2ARM3 0x24
|
|
#define TYPHOON_REG_HOST2ARM2 0x28
|
|
#define TYPHOON_REG_HOST2ARM1 0x2c
|
|
#define TYPHOON_REG_HOST2ARM0 0x30
|
|
#define TYPHOON_REG_ARM2HOST3 0x34
|
|
#define TYPHOON_REG_ARM2HOST2 0x38
|
|
#define TYPHOON_REG_ARM2HOST1 0x3c
|
|
#define TYPHOON_REG_ARM2HOST0 0x40
|
|
|
|
#define TYPHOON_REG_BOOT_DATA_LO TYPHOON_REG_HOST2ARM5
|
|
#define TYPHOON_REG_BOOT_DATA_HI TYPHOON_REG_HOST2ARM4
|
|
#define TYPHOON_REG_BOOT_DEST_ADDR TYPHOON_REG_HOST2ARM3
|
|
#define TYPHOON_REG_BOOT_CHECKSUM TYPHOON_REG_HOST2ARM2
|
|
#define TYPHOON_REG_BOOT_LENGTH TYPHOON_REG_HOST2ARM1
|
|
|
|
#define TYPHOON_REG_DOWNLOAD_BOOT_ADDR TYPHOON_REG_HOST2ARM1
|
|
#define TYPHOON_REG_DOWNLOAD_HMAC_0 TYPHOON_REG_HOST2ARM2
|
|
#define TYPHOON_REG_DOWNLOAD_HMAC_1 TYPHOON_REG_HOST2ARM3
|
|
#define TYPHOON_REG_DOWNLOAD_HMAC_2 TYPHOON_REG_HOST2ARM4
|
|
#define TYPHOON_REG_DOWNLOAD_HMAC_3 TYPHOON_REG_HOST2ARM5
|
|
#define TYPHOON_REG_DOWNLOAD_HMAC_4 TYPHOON_REG_HOST2ARM6
|
|
|
|
#define TYPHOON_REG_BOOT_RECORD_ADDR_HI TYPHOON_REG_HOST2ARM2
|
|
#define TYPHOON_REG_BOOT_RECORD_ADDR_LO TYPHOON_REG_HOST2ARM1
|
|
|
|
#define TYPHOON_REG_TX_LO_READY TYPHOON_REG_HOST2ARM3
|
|
#define TYPHOON_REG_CMD_READY TYPHOON_REG_HOST2ARM2
|
|
#define TYPHOON_REG_TX_HI_READY TYPHOON_REG_HOST2ARM1
|
|
|
|
#define TYPHOON_REG_COMMAND TYPHOON_REG_HOST2ARM0
|
|
#define TYPHOON_REG_HEARTBEAT TYPHOON_REG_ARM2HOST3
|
|
#define TYPHOON_REG_STATUS TYPHOON_REG_ARM2HOST0
|
|
|
|
/* 3XP Reset values (TYPHOON_REG_SOFT_RESET)
|
|
*/
|
|
#define TYPHOON_RESET_ALL 0x7f
|
|
#define TYPHOON_RESET_NONE 0x00
|
|
|
|
/* 3XP irq bits (TYPHOON_REG_INTR{STATUS,ENABLE,MASK})
|
|
*
|
|
* Some of these came from OpenBSD, as the 3Com docs have it wrong
|
|
* (INTR_SELF) or don't list it at all (INTR_*_ABORT)
|
|
*
|
|
* Enabling irqs on the Heartbeat reg (ArmToHost3) gets you an irq
|
|
* about every 8ms, so don't do it.
|
|
*/
|
|
#define TYPHOON_INTR_HOST_INT 0x00000001
|
|
#define TYPHOON_INTR_ARM2HOST0 0x00000002
|
|
#define TYPHOON_INTR_ARM2HOST1 0x00000004
|
|
#define TYPHOON_INTR_ARM2HOST2 0x00000008
|
|
#define TYPHOON_INTR_ARM2HOST3 0x00000010
|
|
#define TYPHOON_INTR_DMA0 0x00000020
|
|
#define TYPHOON_INTR_DMA1 0x00000040
|
|
#define TYPHOON_INTR_DMA2 0x00000080
|
|
#define TYPHOON_INTR_DMA3 0x00000100
|
|
#define TYPHOON_INTR_MASTER_ABORT 0x00000200
|
|
#define TYPHOON_INTR_TARGET_ABORT 0x00000400
|
|
#define TYPHOON_INTR_SELF 0x00000800
|
|
#define TYPHOON_INTR_RESERVED 0xfffff000
|
|
|
|
#define TYPHOON_INTR_BOOTCMD TYPHOON_INTR_ARM2HOST0
|
|
|
|
#define TYPHOON_INTR_ENABLE_ALL 0xffffffef
|
|
#define TYPHOON_INTR_ALL 0xffffffff
|
|
#define TYPHOON_INTR_NONE 0x00000000
|
|
|
|
/* The commands for the 3XP chip (TYPHOON_REG_COMMAND)
|
|
*/
|
|
#define TYPHOON_BOOTCMD_BOOT 0x00
|
|
#define TYPHOON_BOOTCMD_WAKEUP 0xfa
|
|
#define TYPHOON_BOOTCMD_DNLD_COMPLETE 0xfb
|
|
#define TYPHOON_BOOTCMD_SEG_AVAILABLE 0xfc
|
|
#define TYPHOON_BOOTCMD_RUNTIME_IMAGE 0xfd
|
|
#define TYPHOON_BOOTCMD_REG_BOOT_RECORD 0xff
|
|
|
|
/* 3XP Status values (TYPHOON_REG_STATUS)
|
|
*/
|
|
#define TYPHOON_STATUS_WAITING_FOR_BOOT 0x07
|
|
#define TYPHOON_STATUS_SECOND_INIT 0x08
|
|
#define TYPHOON_STATUS_RUNNING 0x09
|
|
#define TYPHOON_STATUS_WAITING_FOR_HOST 0x0d
|
|
#define TYPHOON_STATUS_WAITING_FOR_SEGMENT 0x10
|
|
#define TYPHOON_STATUS_SLEEPING 0x11
|
|
#define TYPHOON_STATUS_HALTED 0x14
|