388 lines
11 KiB
C
388 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/platform_device.h>
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#include <linux/of_device.h>
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#include <linux/module.h>
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#include <linux/stmmac.h>
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#include <linux/clk.h>
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#include "stmmac_platform.h"
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static const char *const mgbe_clks[] = {
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"rx-pcs", "tx", "tx-pcs", "mac-divider", "mac", "mgbe", "ptp-ref", "mac"
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};
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struct tegra_mgbe {
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struct device *dev;
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struct clk_bulk_data *clks;
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struct reset_control *rst_mac;
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struct reset_control *rst_pcs;
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void __iomem *hv;
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void __iomem *regs;
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void __iomem *xpcs;
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struct mii_bus *mii;
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};
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#define XPCS_WRAP_UPHY_RX_CONTROL 0x801c
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#define XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD BIT(31)
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#define XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY BIT(10)
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#define XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET BIT(9)
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#define XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN BIT(8)
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#define XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP (BIT(7) | BIT(6))
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#define XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ BIT(5)
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#define XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ BIT(4)
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#define XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN BIT(0)
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#define XPCS_WRAP_UPHY_HW_INIT_CTRL 0x8020
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#define XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN BIT(0)
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#define XPCS_WRAP_UPHY_HW_INIT_CTRL_RX_EN BIT(2)
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#define XPCS_WRAP_UPHY_STATUS 0x8044
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#define XPCS_WRAP_UPHY_STATUS_TX_P_UP BIT(0)
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#define XPCS_WRAP_IRQ_STATUS 0x8050
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#define XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS BIT(6)
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#define XPCS_REG_ADDR_SHIFT 10
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#define XPCS_REG_ADDR_MASK 0x1fff
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#define XPCS_ADDR 0x3fc
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#define MGBE_WRAP_COMMON_INTR_ENABLE 0x8704
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#define MAC_SBD_INTR BIT(2)
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#define MGBE_WRAP_AXI_ASID0_CTRL 0x8400
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#define MGBE_SID 0x6
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static int __maybe_unused tegra_mgbe_suspend(struct device *dev)
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{
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struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(dev);
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int err;
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err = stmmac_suspend(dev);
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if (err)
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return err;
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clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);
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return reset_control_assert(mgbe->rst_mac);
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}
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static int __maybe_unused tegra_mgbe_resume(struct device *dev)
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{
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struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(dev);
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u32 value;
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int err;
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err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks);
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if (err < 0)
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return err;
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err = reset_control_deassert(mgbe->rst_mac);
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if (err < 0)
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return err;
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/* Enable common interrupt at wrapper level */
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writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE);
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/* Program SID */
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writel(MGBE_SID, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL);
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value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS);
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if ((value & XPCS_WRAP_UPHY_STATUS_TX_P_UP) == 0) {
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value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);
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value |= XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN;
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writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);
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}
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err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL, value,
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(value & XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN) == 0,
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500, 500 * 2000);
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if (err < 0) {
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dev_err(mgbe->dev, "timeout waiting for TX lane to become enabled\n");
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clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);
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return err;
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}
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err = stmmac_resume(dev);
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if (err < 0)
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clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);
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return err;
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}
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static int mgbe_uphy_lane_bringup_serdes_up(struct net_device *ndev, void *mgbe_data)
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{
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struct tegra_mgbe *mgbe = (struct tegra_mgbe *)mgbe_data;
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u32 value;
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int err;
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value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD;
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writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ;
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writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value &= ~XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ;
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writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP;
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writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN;
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writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL, value,
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(value & XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN) == 0,
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1000, 1000 * 2000);
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if (err < 0) {
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dev_err(mgbe->dev, "timeout waiting for RX calibration to become enabled\n");
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return err;
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}
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value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN;
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writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET;
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writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET;
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writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY;
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writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_IRQ_STATUS, value,
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value & XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS,
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500, 500 * 2000);
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if (err < 0) {
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dev_err(mgbe->dev, "timeout waiting for link to become ready\n");
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return err;
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}
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/* clear status */
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writel(value, mgbe->xpcs + XPCS_WRAP_IRQ_STATUS);
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return 0;
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}
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static void mgbe_uphy_lane_bringup_serdes_down(struct net_device *ndev, void *mgbe_data)
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{
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struct tegra_mgbe *mgbe = (struct tegra_mgbe *)mgbe_data;
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u32 value;
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value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD;
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writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN;
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writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP;
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writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value |= XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ;
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writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ;
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writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
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}
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static int tegra_mgbe_probe(struct platform_device *pdev)
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{
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struct plat_stmmacenet_data *plat;
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struct stmmac_resources res;
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struct tegra_mgbe *mgbe;
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int irq, err, i;
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u32 value;
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mgbe = devm_kzalloc(&pdev->dev, sizeof(*mgbe), GFP_KERNEL);
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if (!mgbe)
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return -ENOMEM;
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mgbe->dev = &pdev->dev;
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memset(&res, 0, sizeof(res));
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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mgbe->hv = devm_platform_ioremap_resource_byname(pdev, "hypervisor");
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if (IS_ERR(mgbe->hv))
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return PTR_ERR(mgbe->hv);
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mgbe->regs = devm_platform_ioremap_resource_byname(pdev, "mac");
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if (IS_ERR(mgbe->regs))
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return PTR_ERR(mgbe->regs);
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mgbe->xpcs = devm_platform_ioremap_resource_byname(pdev, "xpcs");
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if (IS_ERR(mgbe->xpcs))
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return PTR_ERR(mgbe->xpcs);
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res.addr = mgbe->regs;
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res.irq = irq;
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mgbe->clks = devm_kcalloc(&pdev->dev, ARRAY_SIZE(mgbe_clks),
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sizeof(*mgbe->clks), GFP_KERNEL);
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if (!mgbe->clks)
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return -ENOMEM;
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for (i = 0; i < ARRAY_SIZE(mgbe_clks); i++)
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mgbe->clks[i].id = mgbe_clks[i];
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err = devm_clk_bulk_get(mgbe->dev, ARRAY_SIZE(mgbe_clks), mgbe->clks);
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if (err < 0)
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return err;
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err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks);
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if (err < 0)
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return err;
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/* Perform MAC reset */
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mgbe->rst_mac = devm_reset_control_get(&pdev->dev, "mac");
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if (IS_ERR(mgbe->rst_mac)) {
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err = PTR_ERR(mgbe->rst_mac);
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goto disable_clks;
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}
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err = reset_control_assert(mgbe->rst_mac);
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if (err < 0)
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goto disable_clks;
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usleep_range(2000, 4000);
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err = reset_control_deassert(mgbe->rst_mac);
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if (err < 0)
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goto disable_clks;
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/* Perform PCS reset */
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mgbe->rst_pcs = devm_reset_control_get(&pdev->dev, "pcs");
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if (IS_ERR(mgbe->rst_pcs)) {
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err = PTR_ERR(mgbe->rst_pcs);
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goto disable_clks;
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}
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err = reset_control_assert(mgbe->rst_pcs);
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if (err < 0)
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goto disable_clks;
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usleep_range(2000, 4000);
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err = reset_control_deassert(mgbe->rst_pcs);
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if (err < 0)
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goto disable_clks;
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plat = stmmac_probe_config_dt(pdev, res.mac);
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if (IS_ERR(plat)) {
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err = PTR_ERR(plat);
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goto disable_clks;
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}
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plat->has_xgmac = 1;
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plat->tso_en = 1;
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plat->pmt = 1;
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plat->bsp_priv = mgbe;
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if (!plat->mdio_node)
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plat->mdio_node = of_get_child_by_name(pdev->dev.of_node, "mdio");
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if (!plat->mdio_bus_data) {
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plat->mdio_bus_data = devm_kzalloc(&pdev->dev, sizeof(*plat->mdio_bus_data),
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GFP_KERNEL);
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if (!plat->mdio_bus_data) {
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err = -ENOMEM;
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goto remove;
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}
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}
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plat->mdio_bus_data->needs_reset = true;
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value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS);
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if ((value & XPCS_WRAP_UPHY_STATUS_TX_P_UP) == 0) {
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value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);
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value |= XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN;
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writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);
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}
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err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL, value,
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(value & XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN) == 0,
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500, 500 * 2000);
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if (err < 0) {
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dev_err(mgbe->dev, "timeout waiting for TX lane to become enabled\n");
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goto remove;
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}
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plat->serdes_powerup = mgbe_uphy_lane_bringup_serdes_up;
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plat->serdes_powerdown = mgbe_uphy_lane_bringup_serdes_down;
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/* Tx FIFO Size - 128KB */
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plat->tx_fifo_size = 131072;
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/* Rx FIFO Size - 192KB */
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plat->rx_fifo_size = 196608;
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/* Enable common interrupt at wrapper level */
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writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE);
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/* Program SID */
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writel(MGBE_SID, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL);
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plat->serdes_up_after_phy_linkup = 1;
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err = stmmac_dvr_probe(&pdev->dev, plat, &res);
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if (err < 0)
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goto remove;
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return 0;
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remove:
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stmmac_remove_config_dt(pdev, plat);
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disable_clks:
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clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);
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return err;
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}
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static void tegra_mgbe_remove(struct platform_device *pdev)
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{
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struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(&pdev->dev);
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clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);
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stmmac_pltfr_remove(pdev);
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}
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static const struct of_device_id tegra_mgbe_match[] = {
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{ .compatible = "nvidia,tegra234-mgbe", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, tegra_mgbe_match);
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static SIMPLE_DEV_PM_OPS(tegra_mgbe_pm_ops, tegra_mgbe_suspend, tegra_mgbe_resume);
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static struct platform_driver tegra_mgbe_driver = {
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.probe = tegra_mgbe_probe,
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.remove_new = tegra_mgbe_remove,
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.driver = {
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.name = "tegra-mgbe",
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.pm = &tegra_mgbe_pm_ops,
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.of_match_table = tegra_mgbe_match,
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},
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};
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module_platform_driver(tegra_mgbe_driver);
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MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
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MODULE_DESCRIPTION("NVIDIA Tegra MGBE driver");
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MODULE_LICENSE("GPL");
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