327 lines
8.0 KiB
C
327 lines
8.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*******************************************************************************
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This contains the functions to handle the normal descriptors.
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include <linux/stmmac.h>
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#include "common.h"
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#include "descs_com.h"
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static int ndesc_get_tx_status(struct net_device_stats *stats,
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struct stmmac_extra_stats *x,
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struct dma_desc *p, void __iomem *ioaddr)
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{
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unsigned int tdes0 = le32_to_cpu(p->des0);
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unsigned int tdes1 = le32_to_cpu(p->des1);
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int ret = tx_done;
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/* Get tx owner first */
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if (unlikely(tdes0 & TDES0_OWN))
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return tx_dma_own;
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/* Verify tx error by looking at the last segment. */
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if (likely(!(tdes1 & TDES1_LAST_SEGMENT)))
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return tx_not_ls;
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if (unlikely(tdes0 & TDES0_ERROR_SUMMARY)) {
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if (unlikely(tdes0 & TDES0_UNDERFLOW_ERROR)) {
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x->tx_underflow++;
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stats->tx_fifo_errors++;
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}
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if (unlikely(tdes0 & TDES0_NO_CARRIER)) {
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x->tx_carrier++;
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stats->tx_carrier_errors++;
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}
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if (unlikely(tdes0 & TDES0_LOSS_CARRIER)) {
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x->tx_losscarrier++;
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stats->tx_carrier_errors++;
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}
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if (unlikely((tdes0 & TDES0_EXCESSIVE_DEFERRAL) ||
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(tdes0 & TDES0_EXCESSIVE_COLLISIONS) ||
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(tdes0 & TDES0_LATE_COLLISION))) {
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unsigned int collisions;
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collisions = (tdes0 & TDES0_COLLISION_COUNT_MASK) >> 3;
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stats->collisions += collisions;
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}
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ret = tx_err;
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}
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if (tdes0 & TDES0_VLAN_FRAME)
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x->tx_vlan++;
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if (unlikely(tdes0 & TDES0_DEFERRED))
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x->tx_deferred++;
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return ret;
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}
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static int ndesc_get_tx_len(struct dma_desc *p)
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{
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return (le32_to_cpu(p->des1) & RDES1_BUFFER1_SIZE_MASK);
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}
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/* This function verifies if each incoming frame has some errors
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* and, if required, updates the multicast statistics.
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* In case of success, it returns good_frame because the GMAC device
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* is supposed to be able to compute the csum in HW. */
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static int ndesc_get_rx_status(struct net_device_stats *stats,
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struct stmmac_extra_stats *x,
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struct dma_desc *p)
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{
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int ret = good_frame;
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unsigned int rdes0 = le32_to_cpu(p->des0);
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if (unlikely(rdes0 & RDES0_OWN))
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return dma_own;
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if (unlikely(!(rdes0 & RDES0_LAST_DESCRIPTOR))) {
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stats->rx_length_errors++;
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return discard_frame;
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}
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if (unlikely(rdes0 & RDES0_ERROR_SUMMARY)) {
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if (unlikely(rdes0 & RDES0_DESCRIPTOR_ERROR))
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x->rx_desc++;
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if (unlikely(rdes0 & RDES0_SA_FILTER_FAIL))
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x->sa_filter_fail++;
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if (unlikely(rdes0 & RDES0_OVERFLOW_ERROR))
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x->overflow_error++;
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if (unlikely(rdes0 & RDES0_IPC_CSUM_ERROR))
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x->ipc_csum_error++;
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if (unlikely(rdes0 & RDES0_COLLISION)) {
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x->rx_collision++;
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stats->collisions++;
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}
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if (unlikely(rdes0 & RDES0_CRC_ERROR)) {
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x->rx_crc_errors++;
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stats->rx_crc_errors++;
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}
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ret = discard_frame;
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}
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if (unlikely(rdes0 & RDES0_DRIBBLING))
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x->dribbling_bit++;
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if (unlikely(rdes0 & RDES0_LENGTH_ERROR)) {
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x->rx_length++;
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ret = discard_frame;
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}
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if (unlikely(rdes0 & RDES0_MII_ERROR)) {
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x->rx_mii++;
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ret = discard_frame;
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}
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#ifdef STMMAC_VLAN_TAG_USED
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if (rdes0 & RDES0_VLAN_TAG)
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x->vlan_tag++;
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#endif
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return ret;
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}
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static void ndesc_init_rx_desc(struct dma_desc *p, int disable_rx_ic, int mode,
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int end, int bfsize)
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{
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int bfsize1;
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p->des0 |= cpu_to_le32(RDES0_OWN);
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bfsize1 = min(bfsize, BUF_SIZE_2KiB - 1);
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p->des1 |= cpu_to_le32(bfsize1 & RDES1_BUFFER1_SIZE_MASK);
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if (mode == STMMAC_CHAIN_MODE)
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ndesc_rx_set_on_chain(p, end);
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else
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ndesc_rx_set_on_ring(p, end, bfsize);
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if (disable_rx_ic)
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p->des1 |= cpu_to_le32(RDES1_DISABLE_IC);
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}
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static void ndesc_init_tx_desc(struct dma_desc *p, int mode, int end)
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{
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p->des0 &= cpu_to_le32(~TDES0_OWN);
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if (mode == STMMAC_CHAIN_MODE)
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ndesc_tx_set_on_chain(p);
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else
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ndesc_end_tx_desc_on_ring(p, end);
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}
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static int ndesc_get_tx_owner(struct dma_desc *p)
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{
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return (le32_to_cpu(p->des0) & TDES0_OWN) >> 31;
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}
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static void ndesc_set_tx_owner(struct dma_desc *p)
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{
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p->des0 |= cpu_to_le32(TDES0_OWN);
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}
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static void ndesc_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
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{
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p->des0 |= cpu_to_le32(RDES0_OWN);
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}
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static int ndesc_get_tx_ls(struct dma_desc *p)
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{
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return (le32_to_cpu(p->des1) & TDES1_LAST_SEGMENT) >> 30;
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}
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static void ndesc_release_tx_desc(struct dma_desc *p, int mode)
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{
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int ter = (le32_to_cpu(p->des1) & TDES1_END_RING) >> 25;
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memset(p, 0, offsetof(struct dma_desc, des2));
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if (mode == STMMAC_CHAIN_MODE)
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ndesc_tx_set_on_chain(p);
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else
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ndesc_end_tx_desc_on_ring(p, ter);
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}
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static void ndesc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
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bool csum_flag, int mode, bool tx_own,
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bool ls, unsigned int tot_pkt_len)
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{
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unsigned int tdes1 = le32_to_cpu(p->des1);
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if (is_fs)
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tdes1 |= TDES1_FIRST_SEGMENT;
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else
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tdes1 &= ~TDES1_FIRST_SEGMENT;
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if (likely(csum_flag))
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tdes1 |= (TX_CIC_FULL) << TDES1_CHECKSUM_INSERTION_SHIFT;
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else
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tdes1 &= ~(TX_CIC_FULL << TDES1_CHECKSUM_INSERTION_SHIFT);
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if (ls)
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tdes1 |= TDES1_LAST_SEGMENT;
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p->des1 = cpu_to_le32(tdes1);
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if (mode == STMMAC_CHAIN_MODE)
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norm_set_tx_desc_len_on_chain(p, len);
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else
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norm_set_tx_desc_len_on_ring(p, len);
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if (tx_own)
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p->des0 |= cpu_to_le32(TDES0_OWN);
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}
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static void ndesc_set_tx_ic(struct dma_desc *p)
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{
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p->des1 |= cpu_to_le32(TDES1_INTERRUPT);
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}
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static int ndesc_get_rx_frame_len(struct dma_desc *p, int rx_coe_type)
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{
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unsigned int csum = 0;
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/* The type-1 checksum offload engines append the checksum at
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* the end of frame and the two bytes of checksum are added in
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* the length.
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* Adjust for that in the framelen for type-1 checksum offload
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* engines
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*/
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if (rx_coe_type == STMMAC_RX_COE_TYPE1)
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csum = 2;
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return (((le32_to_cpu(p->des0) & RDES0_FRAME_LEN_MASK)
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>> RDES0_FRAME_LEN_SHIFT) -
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csum);
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}
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static void ndesc_enable_tx_timestamp(struct dma_desc *p)
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{
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p->des1 |= cpu_to_le32(TDES1_TIME_STAMP_ENABLE);
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}
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static int ndesc_get_tx_timestamp_status(struct dma_desc *p)
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{
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return (le32_to_cpu(p->des0) & TDES0_TIME_STAMP_STATUS) >> 17;
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}
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static void ndesc_get_timestamp(void *desc, u32 ats, u64 *ts)
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{
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struct dma_desc *p = (struct dma_desc *)desc;
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u64 ns;
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ns = le32_to_cpu(p->des2);
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/* convert high/sec time stamp value to nanosecond */
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ns += le32_to_cpu(p->des3) * 1000000000ULL;
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*ts = ns;
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}
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static int ndesc_get_rx_timestamp_status(void *desc, void *next_desc, u32 ats)
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{
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struct dma_desc *p = (struct dma_desc *)desc;
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if ((le32_to_cpu(p->des2) == 0xffffffff) &&
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(le32_to_cpu(p->des3) == 0xffffffff))
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/* timestamp is corrupted, hence don't store it */
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return 0;
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else
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return 1;
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}
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static void ndesc_display_ring(void *head, unsigned int size, bool rx,
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dma_addr_t dma_rx_phy, unsigned int desc_size)
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{
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struct dma_desc *p = (struct dma_desc *)head;
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dma_addr_t dma_addr;
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int i;
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pr_info("%s descriptor ring:\n", rx ? "RX" : "TX");
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for (i = 0; i < size; i++) {
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u64 x;
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dma_addr = dma_rx_phy + i * sizeof(*p);
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x = *(u64 *)p;
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pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x",
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i, &dma_addr,
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(unsigned int)x, (unsigned int)(x >> 32),
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p->des2, p->des3);
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p++;
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}
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pr_info("\n");
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}
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static void ndesc_set_addr(struct dma_desc *p, dma_addr_t addr)
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{
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p->des2 = cpu_to_le32(addr);
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}
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static void ndesc_clear(struct dma_desc *p)
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{
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p->des2 = 0;
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}
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const struct stmmac_desc_ops ndesc_ops = {
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.tx_status = ndesc_get_tx_status,
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.rx_status = ndesc_get_rx_status,
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.get_tx_len = ndesc_get_tx_len,
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.init_rx_desc = ndesc_init_rx_desc,
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.init_tx_desc = ndesc_init_tx_desc,
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.get_tx_owner = ndesc_get_tx_owner,
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.release_tx_desc = ndesc_release_tx_desc,
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.prepare_tx_desc = ndesc_prepare_tx_desc,
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.set_tx_ic = ndesc_set_tx_ic,
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.get_tx_ls = ndesc_get_tx_ls,
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.set_tx_owner = ndesc_set_tx_owner,
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.set_rx_owner = ndesc_set_rx_owner,
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.get_rx_frame_len = ndesc_get_rx_frame_len,
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.enable_tx_timestamp = ndesc_enable_tx_timestamp,
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.get_tx_timestamp_status = ndesc_get_tx_timestamp_status,
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.get_timestamp = ndesc_get_timestamp,
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.get_rx_timestamp_status = ndesc_get_rx_timestamp_status,
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.display_ring = ndesc_display_ring,
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.set_addr = ndesc_set_addr,
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.clear = ndesc_clear,
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};
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